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91. 发明申请

WO2004100374A3 TIME DELAY APPARATUS AND METHOD OF USING SAME 审中-公开
标题翻译：时间延迟装置及其使用方法
公开(公告)号：WO2004100374A3
公开(公告)日：2005-05-19
申请号：PCT/US0330603
申请日：2003-09-25
申请人： HRL LAB LLC , ELLIOTT KEN , MORTON SUSAN , RODWELL MARK
发明人： ELLIOTT KEN , MORTON SUSAN , RODWELL MARK
IPC分类号： H03K5/00 , H03K5/13 , H03K17/60 , H03K17/62
CPC分类号： H03K17/603 , H03K5/131 , H03K17/6264 , H03K2005/00065 , H03K2005/00176
摘要： Disclosed is a time delay generator 200 apparatus and method. The apparatus includes a time delay gate 212, a mixer 216 (a Gilbert cell circuit), and a current digital to analog converter 206. The mixer 216, comprised of first and second transistor differential pairs 218 and 220, receives an analog input signal 202 without a delay as well as a delayed input signal 210 produced by the time gate delay. The digital to analog converter regulates the relative current flow between a first control signal 232 and a second control signal 238, effectively altering the mixing of the undelayed input signal 208 and the delayed input signal 210 to generate a delayed output signal 214 with a time or phase delay substantially equal to the temporal delay represented by the digital signal input 204. The time delay generator exhibits reduced phase noise and a linear time delay response.
摘要翻译：公开了一种时间延迟发生器200的装置和方法。该装置包括时间延迟门212，混合器216（吉尔伯特单元电路）和当前数模转换器206.由第一和第二晶体管差分对218和220组成的混频器216接收模拟输入信号202 没有延迟，以及由时间门延迟产生的延迟输入信号210。数模转换器调节第一控制信号232和第二控制信号238之间的相对电流，有效地改变未延迟的输入信号208和延迟输入信号210的混合，以产生具有时间的延迟的输出信号214，或者相位延迟基本上等于由数字信号输入204表示的时间延迟。时间延迟发生器表现出降低的相位噪声和线性时间延迟响应。

92. 发明申请

WO2004109917A1 HIGH RESOLUTION PWM GENERATOR OR DIGITALLY CONTROLLED OSCILLATOR 审中-公开
标题翻译：高分辨率PWM发生器或数字控制振荡器
公开(公告)号：WO2004109917A1
公开(公告)日：2004-12-16
申请号：PCT/IB2004/050866
申请日：2004-06-08
申请人： KONINKLIJKE PHILIPS ELECTRONICS, N.V. , LI, Qiong, M. , GIANNOPOULOS, Demetri
发明人： LI, Qiong, M. , GIANNOPOULOS, Demetri
IPC分类号： H03K5/13
CPC分类号： H03K3/0315 , H03K5/133 , H03K7/08 , H03K2005/00026 , H03K2005/00032 , H03L7/0812
摘要： A high resolution pulse width modulation (PWM) or voltage controlled output (DCO) generator is disclosed. The resolution is increased over that of the circuit clock by delaying the generated signal through a series of delays, all of which are controlled by a delay locked loop. The delays are a small fraction of the clock period, thus providing resolution greater than that of the circuit clock.
摘要翻译：公开了一种高分辨率脉宽调制（PWM）或压控输出（DCO）发生器。通过将生成的信号延迟一系列延迟，所有这些都由延迟锁定环控制，分辨率比电路时钟的分辨率增加。延迟是时钟周期的一小部分，因此提供比电路时钟更大的分辨率。

93. 发明申请

WO2004100372A1 タイミング発生回路及びその方法审中-公开
标题翻译：用于产生时序的电路和方法
公开(公告)号：WO2004100372A1
公开(公告)日：2004-11-18
申请号：PCT/JP1995/000070
申请日：1995-01-24
申请人：秀野精二 , 増田則之 , 鈴木雅之 , 佐藤政利
发明人：秀野精二 , 増田則之 , 鈴木雅之 , 佐藤政利
IPC分类号： H03K5/13
CPC分类号： H03K5/135
摘要： A timing generating circuit is constituted in an LSI comprising CMOSFETs. The variation of delay resulting from the heat generated from the CMOSFETs when pulses are propagated in eliminated. A main delay element 21 by which timing is set and an auxiliary delay element 22 are closely arranged and connected in series in the same cell and the sum of the initial values of the delays by the elements 21 and 22 is maintained at a fixed value. The pulse inputted to the element 21 is also fed to a reference signal generating section 27, which outputs a reference signal by using a reference clock after the time equal to the above-mentioned fixed value has elapsed from the input of the pulse. The time difference between the reference signal and the output of the element 22 is measured by means of a detecting section 29 and a correcting value is calculated by dividing the difference at the ration between the above-mentioned initial values. The correcting value is used to make the sum of the initial values of the elements 21 and 22 fixed.
摘要翻译：定时发生电路由包括CMOSFET的LSI构成。当消除脉冲时，由CMOSFET产生的热量产生的延迟的变化。设置定时的主延迟元件21和辅助延迟元件22在同一单元中串联紧密并且串联连接，元件21和22的延迟初始值之和保持在固定值。输入到元件21的脉冲也被馈送到参考信号产生部分27，该基准信号产生部分27在等于从脉冲的输入经过上述固定值的时间之后通过使用参考时钟输出参考信号。通过检测部分29测量参考信号和元件22的输出之间的时间差，并且通过除以上述初始值之间的比率的差来计算校正值。校正值用于使元件21和22的初始值之和固定。

94. 发明申请

WO2004082140A1 CURRENT MODE LOGIC (CML) CIRCUIT CONCEPT FOR A VARIABLE DELAY ELEMENT 审中-公开
标题翻译：电流模式逻辑（CML）可变延迟元件的电路概念
公开(公告)号：WO2004082140A1
公开(公告)日：2004-09-23
申请号：PCT/EP2004/002133
申请日：2004-03-03
申请人： INFINEON TECHNOLOGIES AG , LAMMERS, Stefan , VIEHMANN, Hans-Heinrich
发明人： LAMMERS, Stefan , VIEHMANN, Hans-Heinrich
IPC分类号： H03K5/13
CPC分类号： H03K5/133 , H03K2005/00026 , H03K2005/00156 , H03K2005/00208
摘要： An apparatus for a current mode logic variable delay element. A preferred embodiment comprises an input signal that is provided to a multiplexer (for example, multiplexer 210) in both buffered (via a buffer (for example, buffer 205)) and unbuffered form. A control signal of the multiplexer may be used to select from either the buffered or unbuffered input signals. By using a control signal at an intermediate value (somewhere in between values that selects the buffered or unbuffered input signals), the multiplexer may then combine the buffered and unbuffered input signals in proportion with the value of the control signal and imparts a delay upon the input signal that may be in between the delay imparted by the buffer.
摘要翻译：一种用于电流模式逻辑可变延迟元件的装置。优选实施例包括提供给缓冲（经由缓冲器（例如，缓冲器205））和非缓冲形式的多路复用器（例如，多路复用器210）的输入信号。可以使用多路复用器的控制信号来从缓冲的或非缓冲的输入信号中进行选择。通过使用中间值（选择缓冲或非缓冲输入信号的值之间的某处）的控制信号，多路复用器然后可以将缓冲和非缓冲的输入信号与控制信号的值成比例地组合，并且在可能在由缓冲器赋予的延迟之间的输入信号。

95. 发明申请

WO2004059839A1 CIRCUIT ARRANGEMENT 审中-公开
标题翻译：电路布置
公开(公告)号：WO2004059839A1
公开(公告)日：2004-07-15
申请号：PCT/IB2003/006215
申请日：2003-12-22
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , NEGISHI, Nobuji , KISHIDA, Masaya
发明人： NEGISHI, Nobuji , KISHIDA, Masaya
IPC分类号： H03K5/13
CPC分类号： H03K5/135 , G11C19/00 , G11C19/28 , H03K2005/00241
摘要： An object of the present invention is to provide a circuit device in which the power consumption can be reduced without the dedicated signal. A circuit device (1) comprising a D flip-flop (F0) for receiving a pulse of a clock signal (CK) to introduce data thereinto and output said introduced data and a shift register (2), comprising the D flip-flops (F1 to F7) for introducing the data thereinto in accordance with the pulse to output the introduced data, for processing the outputted data from the D flip-flop (F0), wherein the circuit device (1) comprises a control circuit (3) for controlling whether the D flip-flops (F1 to F7) are supplied with the pulse of the clock signal (CK) on the basis of outputted data from the D flip-flop (F0) in accordance with the pulse of the clock signal (CK) and data to be introduced into the D flip-flop (F0) in accordance with the next pulse.
摘要翻译：本发明的目的是提供一种电路装置，其中可以在没有专用信号的情况下降低功耗。一种电路装置（1），包括用于接收时钟信号（CK）的脉冲以引入数据并输出所述引入的数据的D触发器（F0）和移位寄存器（2），包括D个触发器（ F1至F7），用于根据脉冲引入数据以输出引入的数据，用于处理来自D触发器（F0）的输出数据，其中电路装置（1）包括控制电路（3），用于基于来自D触发器（F0）的输出数据，根据时钟信号（CK）的脉冲来控制D触发器（F1〜F7）是否被提供时钟信号（CK）的脉冲）和根据下一个脉冲引入D触发器（F0）的数据。

96. 发明申请

WO2004015743A3 CLOCK DISTRIBUTOR CIRCUIT FOR MAINTAINING A PHASE RELATIONSHIP BETWEEN REMOTE OPERATING NODES AND A REFERENCE CLOCK ON A CHIP 审中-公开
标题翻译：用于维持远程操作数和芯片上的参考时钟之间的相位关系的时钟分配器电路
公开(公告)号：WO2004015743A3
公开(公告)日：2004-06-17
申请号：PCT/US0324315
申请日：2003-08-05
申请人： TIMELAB CORP
发明人： CARLEY ADAM L
IPC分类号： G06F1/10 , H03K5/13 , H03K5/15 , G06F17/50
CPC分类号： G06F1/10
摘要： A clock signal distributor circuit (12) for maintaining a phase relationship between one or more remote operating nodes (15, 17) and a reference clock on a chip, wherein there is a clock signal drive path and a clock signal sense path in a distribution limb (14, 16) for each remote node (15, 17). The clock signal distributor circuit (12) comprises a variable signal delay circuit in the clock signal drive path, a variable signal delay circuit in the clock signal sense path, and a feedback circuit that causes at least one variable signal delay circuit to change its signal delay based on phase of signal on the clock signal sense path.
摘要翻译：一种用于维持一个或多个远程操作节点（15,17）和芯片上的参考时钟之间的相位关系的时钟信号分配器电路（12），其中在分配中存在时钟信号驱动路径和时钟信号检测路径肢体（14,16），用于每个远程节点（15,17）。时钟信号分配器电路（12）包括时钟信号驱动路径中的可变信号延迟电路，时钟信号检测路径中的可变信号延迟电路和使至少一个可变信号延迟电路改变其信号的反馈电路基于时钟信号感测路径上的信号相位延迟。

97. 发明申请

WO0231980A3 CYCLIC PHASE SIGNAL GENERATION FROM A SINGLE CLOCK SOURCE USING CURRENT PHASE INTERPOLATION 审中-公开
标题翻译：使用当前相位插值从单个时钟源产生的循环相位信号
公开(公告)号：WO0231980A3
公开(公告)日：2003-11-06
申请号：PCT/US0131941
申请日：2001-10-12
申请人： SILICON COMM LAB INC , CHIEH-YUAN CHAO , YUMING CAO
发明人： CHIEH-YUAN CHAO , YUMING CAO
IPC分类号： H03K5/08 , H03K5/13 , H03K5/135 , H03K5/15 , G06F5/00
CPC分类号： H03K5/1502 , H03K5/08 , H03K5/131 , H03K5/135
摘要： A system (10) and corresponding method for generating multiple phases within a single clock cycle of an input signal. The method includes the steps of generating a plurality of output signals (clk1-clk4) from an input source signal (clock), where each of the plurality of output signals represents a phase-shifted version of the input signal. Next, a pair of signals (clk_a 36, clk_b 38) from the plural output signals is selected to act as clock signals and to define the operating region within which the multiple phases are bounded.A pair of complementary weighted bias currents (I A, IB) are then provided in response to a control signal, each of the complementary bias currents being used to generate the multiple phases of the invention. The pair of weighted bias currents presented to a node are adjusted in response to the selected clock signals, the selected clock signals operating to adjust the rate of change of the weighted bias currents. Finally, a plurality of signals are provided which represent the frequency difference between the first adjusted weighted bias current and a second frequency.
摘要翻译：一种用于在输入信号的单个时钟周期内产生多个相位的系统（10）和相应的方法。该方法包括从输入源信号（时钟）产生多个输出信号（clk1-clk4）的步骤，其中多个输出信号中的每一个表示输入信号的相移版本。接下来，选择来自多个输出信号的一对信号（clk_a 36，clk_b 38）作为时钟信号，并定义多相界限的工作区域。一对补充加权偏置电流（IA，IB ）响应于控制信号被提供，每个互补偏置电流用于产生本发明的多个相。响应于所选择的时钟信号调整呈现给节点的一对加权偏置电流，所选择的时钟信号用于调整加权偏置电流的变化率。最后，提供表示第一调整加权偏置电流和第二频率之间的频率差的多个信号。

98. 发明申请

WO2003088485A1 THE TIME OF FLIGHT SYSTEM ON A CHIP 审中-公开
标题翻译：飞行系统在芯片上的时间
公开(公告)号：WO2003088485A1
公开(公告)日：2003-10-23
申请号：PCT/US2003/011205
申请日：2003-04-10
申请人： THE JOHNS HOPKINS UNIVERSITY , PASCHALIDIS, Nicholas, P.
发明人： PASCHALIDIS, Nicholas, P.
IPC分类号： H03K5/13
CPC分类号： H01J49/40 , G04F10/00 , H03K5/133 , H03K2005/00032 , H03L7/0805 , H03L7/0812
摘要： A CMOS time-of-flight "TOF" system-on-a-chip "SoC" for precise time interval measurement with low power consumption and high counting rate has been developed. The analog and digital TOF chip may include two Constant Fraction Discriminators "CFDs" and a Time-to-Digital Converter "TDC". The CFDs can interface to start and stop anodes through two preamplifiers and perform signal processing for time walk compensation (110). The TDC digitizes the time difference with reference to an off-chip precise external clock (114). One TOF output is an 11-bit digital word and a valid event trigger output indicating a valid event on the 11-bit output bus (116).
摘要翻译：已经开发了CMOS时间飞行“TOF”系统级芯片“SoC”，用于精确的时间间隔测量，具有低功耗和高计数率。模拟和数字TOF芯片可以包括两个恒定分数辨别器“CFD”和一个时间到数字转换器“TDC”。 CFD可以通过两个前置放大器连接起始和停止阳极，并执行信号处理进行时差补偿（110）。参考片外精确的外部时钟（114），TDC对时差进行数字化处理。一个TOF输出是一个11位数字字和一个有效的事件触发输出，指示11位输出总线上的有效事件（116）。

99. 发明申请

WO02056474A3 CLOCK INTERPOLATION THROUGH CAPACITIVE WEIGHTING 审中-公开
标题翻译：通过电容加权的时钟插值
公开(公告)号：WO02056474A3
公开(公告)日：2003-04-24
申请号：PCT/US0200810
申请日：2002-01-11
申请人： SUN MICROSYSTEMS INC
发明人： DROST ROBERT J , BOSNYAK ROBERT J
IPC分类号： H03K5/08 , H03K5/13
CPC分类号： H03K5/13 , H03K5/08
摘要： A clock interpolation circuit for setting and controlling a phase of an output clock that is derived from an interpolation of multiple input clocks. Interpolation is performed by capacitively weighting the multiple clocks. A select and control circuit provides the ability to select different capacitance values to control the weighting. An optional buffer stage is also provided to sharpen the edge transitions of the interpolated clock.
摘要翻译：一种用于设置和控制从多个输入时钟的内插导出的输出时钟的相位的时钟插值电路。通过对多个时钟进行电容加权来执行插值。选择和控制电路提供选择不同电容值以控制加权的能力。还提供了可选的缓冲级，以锐化内插时钟的边沿转换。

100. 发明申请

WO2002099970A1 CONTROLLABLE DELAY CIRCUIT FOR DELAYING AN ELECTRIC SIGNAL 审中-公开
标题翻译：用于延迟电信号的可控延迟电路
公开(公告)号：WO2002099970A1
公开(公告)日：2002-12-12
申请号：PCT/IB2002/002039
申请日：2002-06-04
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN DIJK, Victor, E., S. , MEIJER, Rinze, I., M., P. , VEENDRICK, Hendricus, J., M.
发明人： VAN DIJK, Victor, E., S. , MEIJER, Rinze, I., M., P. , VEENDRICK, Hendricus, J., M.
IPC分类号： H03K5/13
CPC分类号： H03K5/131 , H03K5/15013
摘要： The invention relates to a controllable delay circuit (2) for delaying an electrical input signal (4) wherein the controllable delay circuit (2) is arranged for receiving an input signal (4) and at least one control signal (6), wherein, in use, the delay circuit (2) delays the input signal (4) by a delay for generating an output signal (8), wherein the delay is a function of the at least one control signal (6), wherein the delay circuit (2) comprises a first module (10) for generating a base signal (11) and at least one support signal (12) on the basis of the input signal (4) and the at least one control signal (6), wherein, in use, the phase and/or the amplitude of the at least one support signal (12) is controllable with respect to the phase and /or the amplitude of the base-signal (11) by means of the at least one control signal (6), wherein the delay circuit (2) also comprises a second module (14) connected to the first module (10), which second module (14) comprises a signal-conductor (16) and at least one support conductor (18), wherein the signal conductor (16) and the at least one support conductor extend (18), at least over a part of the conductors, essentially parallel to one another in one another's vicinity, wherein, in use, the first module (10) supplies the base signal (11) to a first end of the signal conductor (16) for generating an output-signal (8) at a second end of the signal conductor (16), and wherein, in use, the first module (10) supplies the at least one support signal (12) to the at least one support conductor (18).
摘要翻译：本发明涉及用于延迟电输入信号（4）的可控延迟电路（2），其中可控延迟电路（2）被布置用于接收输入信号（4）和至少一个控制信号（6），其中，在使用中，延迟电路（2）延迟输入信号（4）以产生输出信号（8），其中延迟是至少一个控制信号（6）的函数，其中延迟电路 2）包括用于基于输入信号（4）和至少一个控制信号（6）产生基本信号（11）和至少一个支持信号（12）的第一模块（10），其中，在使用时，所述至少一个支持信号（12）的相位和/或振幅可通过所述至少一个控制信号（6）相对于所述基本信号（11）的相位和/或振幅来控制），其中所述延迟电路（2）还包括连接到所述第一模块（10）的第二模块（14），所述第二模块（14）包括信号导管（16）和至少一个支撑导体（18），其中所述信号导体（16）和所述至少一个支撑导体延伸（18）至少在所述导体的一部分上，彼此基本上彼此平行其中，在使用中，所述第一模块（10）将所述基本信号（11）提供给所述信号导体（16）的第一端，用于在所述信号导体（16）的第二端产生输出信号（8）），并且其中在使用中，所述第一模块（10）将所述至少一个支撑信号（12）提供给所述至少一个支撑导体（18）。

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