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1. 发明申请

WO2012139071A2 NON FOSTER CIRCUIT 审中-公开
标题翻译：非保险丝电路
公开(公告)号：WO2012139071A2
公开(公告)日：2012-10-11
申请号：PCT/US2012/032638
申请日：2012-04-06
申请人： HITKO, Donald A. , WHITE, Carson R. , YUNG, Michael W. , MATTHEWS, David S. , MORTON, Susan L. , MAY, Jason W. , COLBURN, Joseph
发明人： HITKO, Donald A. , WHITE, Carson R. , YUNG, Michael W. , MATTHEWS, David S. , MORTON, Susan L. , MAY, Jason W. , COLBURN, Joseph
IPC分类号： H03F3/45 , H03K19/003
CPC分类号： H03H11/10 , H03F1/56 , H03F2200/369 , H03H11/44 , H03H11/48 , H04B1/0458 , H04B1/18
摘要： A differential circuit topology that produces a tunable floating negative inductance, negative capacitance, negative resistance/conductance, or a combination of the three. These circuits are commonly referred to as "non-Foster circuits." The disclosed embodiments of the circuits comprises two differential pairs of transistors that are cross-coupled, a load immittance, multiple current sources, two Common-Mode FeedBack (CMFB) networks, at least one tunable (variable) resistance, and two terminals across which the desired immittance is present. The disclosed embodiments of the circuits may be configured as either a Negative Impedance Inverter (NII) or a Negative Impedance Converter (NIC) and as either Open-Circuit-Stable (OCS) and Short-Circuit-Stable (SCS).
摘要翻译：差分电路拓扑产生可调浮动负电感，负电容，负电阻/电导或三者的组合。这些电路通常被称为“非福斯特电路”。所公开的电路实施例包括交叉耦合的两个差分对晶体管，负载导纳，多个电流源，两个共模反馈（CMFB）网络，至少一个可调谐（可变）电阻和两个端子存在所需的导纳。公开的电路实施例可以被配置为负阻抗逆变器（NII）或负阻抗转换器（NIC）以及作为开路稳定（OCS）和短路稳定（SCS）。

2. 发明申请

WO2004100374A2 TIME DELAY APPARATUS AND METHOD OF USING SAME 审中-公开
标题翻译：时间延迟装置及其使用方法
公开(公告)号：WO2004100374A2
公开(公告)日：2004-11-18
申请号：PCT/US2003/030603
申请日：2003-09-25
申请人： HRL LABORATORIES, LLC , ELLIOTT, Ken , MORTON, Susan , RODWELL, Mark
发明人： ELLIOTT, Ken , MORTON, Susan , RODWELL, Mark
IPC分类号： H03K17/60
CPC分类号： H03K17/603 , H03K5/131 , H03K17/6264 , H03K2005/00065 , H03K2005/00176
摘要： Disclosed is a time delay generator 200 apparatus and method. The apparatus includes a time delay gate 212, a mixer 216 (a Gilbert cell circuit), and a current digital to analog converter 206. The mixer 216, comprised of first and second transistor differential pairs 218 and 220, receives an analog input signal 202 without a delay as well as a delayed input signal 210 produced by the time gate delay. The digital to analog converter regulates the relative current flow between a first control signal 232 and a second control signal 238, effectively altering the mixing of the undelayed input signal 208 and the delayed input signal 210 to generate a delayed output signal 214 with a time or phase delay substantially equal to the temporal delay represented by the digital signal input 204. The time delay generator exhibits reduced phase noise and a linear time delay response.
摘要翻译：公开了一种时间延迟发生器200的装置和方法。该装置包括时间延迟门212，混合器216（吉尔伯特单元电路）和当前数模转换器206.由第一和第二晶体管差分对218和220组成的混频器216接收模拟输入信号202 没有延迟，以及由时间门延迟产生的延迟输入信号210。数模转换器调节第一控制信号232和第二控制信号238之间的相对电流，有效地改变未延迟的输入信号208和延迟输入信号210的混合，以产生具有时间的延迟的输出信号214，或者相位延迟基本上等于由数字信号输入204表示的时间延迟。时间延迟发生器表现出降低的相位噪声和线性时间延迟响应。

3. 发明申请

WO2004100374A3 TIME DELAY APPARATUS AND METHOD OF USING SAME 审中-公开
标题翻译：时间延迟装置及其使用方法
公开(公告)号：WO2004100374A3
公开(公告)日：2005-05-19
申请号：PCT/US0330603
申请日：2003-09-25
申请人： HRL LAB LLC , ELLIOTT KEN , MORTON SUSAN , RODWELL MARK
发明人： ELLIOTT KEN , MORTON SUSAN , RODWELL MARK
IPC分类号： H03K5/00 , H03K5/13 , H03K17/60 , H03K17/62
CPC分类号： H03K17/603 , H03K5/131 , H03K17/6264 , H03K2005/00065 , H03K2005/00176
摘要： Disclosed is a time delay generator 200 apparatus and method. The apparatus includes a time delay gate 212, a mixer 216 (a Gilbert cell circuit), and a current digital to analog converter 206. The mixer 216, comprised of first and second transistor differential pairs 218 and 220, receives an analog input signal 202 without a delay as well as a delayed input signal 210 produced by the time gate delay. The digital to analog converter regulates the relative current flow between a first control signal 232 and a second control signal 238, effectively altering the mixing of the undelayed input signal 208 and the delayed input signal 210 to generate a delayed output signal 214 with a time or phase delay substantially equal to the temporal delay represented by the digital signal input 204. The time delay generator exhibits reduced phase noise and a linear time delay response.
摘要翻译：公开了一种时间延迟发生器200的装置和方法。该装置包括时间延迟门212，混合器216（吉尔伯特单元电路）和当前数模转换器206.由第一和第二晶体管差分对218和220组成的混频器216接收模拟输入信号202 没有延迟，以及由时间门延迟产生的延迟输入信号210。数模转换器调节第一控制信号232和第二控制信号238之间的相对电流，有效地改变未延迟的输入信号208和延迟输入信号210的混合，以产生具有时间的延迟的输出信号214，或者相位延迟基本上等于由数字信号输入204表示的时间延迟。时间延迟发生器表现出降低的相位噪声和线性时间延迟响应。

4. 发明申请

WO2012139071A4 NON FOSTER CIRCUIT 审中-公开
标题翻译：非保险丝电路
公开(公告)号：WO2012139071A4
公开(公告)日：2013-03-07
申请号：PCT/US2012032638
申请日：2012-04-06
申请人： HRL LAB LLC , HITKO DONALD A , WHITE CARSON R , YUNG MICHAEL W , MATTHEWS DAVID S , MORTON SUSAN L , MAY JASON W , COLBURN JOSEPH
发明人： HITKO DONALD A , WHITE CARSON R , YUNG MICHAEL W , MATTHEWS DAVID S , MORTON SUSAN L , MAY JASON W , COLBURN JOSEPH
IPC分类号： H03F3/45 , H03K19/003
CPC分类号： H03H11/10 , H03F1/56 , H03F2200/369 , H03H11/44 , H03H11/48 , H04B1/0458 , H04B1/18
摘要： A differential circuit topology that produces a tunable floating negative inductance, negative capacitance, negative resistance/conductance, or a combination of the three. These circuits are commonly referred to as "non-Foster circuits." The disclosed embodiments of the circuits comprises two differential pairs of transistors that are cross-coupled, a load immittance, multiple current sources, two Common-Mode FeedBack (CMFB) networks, at least one tunable (variable) resistance, and two terminals across which the desired immittance is present. The disclosed embodiments of the circuits may be configured as either a Negative Impedance Inverter (NII) or a Negative Impedance Converter (NIC) and as either Open-Circuit-Stable (OCS) and Short-Circuit-Stable (SCS).
摘要翻译：差分电路拓扑产生可调浮动负电感，负电容，负电阻/电导或三者的组合。这些电路通常被称为“非福斯特电路”。所公开的电路实施例包括交叉耦合的两个差分对晶体管，负载导纳，多个电流源，两个共模反馈（CMFB）网络，至少一个可调谐（可变）电阻和两个端子存在所需的导纳。公开的电路实施例可以被配置为负阻抗逆变器（NII）或负阻抗转换器（NIC）以及作为开路稳定（OCS）和短路稳定（SCS）。

5. 发明申请

WO2012139071A3 NON FOSTER CIRCUIT 审中-公开
标题翻译：非福斯特电路
公开(公告)号：WO2012139071A3
公开(公告)日：2013-01-10
申请号：PCT/US2012032638
申请日：2012-04-06
申请人： HITKO DONALD A , WHITE CARSON R , YUNG MICHAEL W , MATTHEWS DAVID S , MORTON SUSAN L , MAY JASON W , COLBURN JOSEPH
发明人： HITKO DONALD A , WHITE CARSON R , YUNG MICHAEL W , MATTHEWS DAVID S , MORTON SUSAN L , MAY JASON W , COLBURN JOSEPH
IPC分类号： H03F3/45 , H03K19/003
CPC分类号： H03H11/10 , H03F1/56 , H03F2200/369 , H03H11/44 , H03H11/48 , H04B1/0458 , H04B1/18
摘要： A differential circuit topology that produces a tunable floating negative inductance, negative capacitance, negative resistance/conductance, or a combination of the three. These circuits are commonly referred to as "non-Foster circuits." The disclosed embodiments of the circuits comprises two differential pairs of transistors that are cross-coupled, a load immittance, multiple current sources, two Common-Mode FeedBack (CMFB) networks, at least one tunable (variable) resistance, and two terminals across which the desired immittance is present. The disclosed embodiments of the circuits may be configured as either a Negative Impedance Inverter (NII) or a Negative Impedance Converter (NIC) and as either Open-Circuit-Stable (OCS) and Short-Circuit-Stable (SCS).
摘要翻译：一种差分电路拓扑，可产生可调浮动负电感，负电容，负电阻/电导或三者的组合。这些电路通常被称为“非福斯特电路”。所公开的电路的实施例包括交叉耦合的两个差分晶体管对，负载导抗，多个电流源，两个共模反馈（CMFB）网络，至少一个可调（可变）电阻以及两个跨过其的端子存在期望的抗体。所公开的电路实施例可以被配置为负阻抗反相器（NII）或负阻抗转换器（NIC）以及开路稳定（OCS）和短路稳定（SCS）。

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