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1. 发明申请

WO2009101568A1 AN INTEGRATED CIRCUIT WITH A MEMORY MATRIX WITH A DELAY MONITORING COLUMN 审中-公开
标题翻译：具有延迟监测列的存储器矩阵的集成电路
公开(公告)号：WO2009101568A1
公开(公告)日：2009-08-20
申请号：PCT/IB2009/050518
申请日：2009-02-09
申请人： NXP B.V. , VEENDRICK, Hendricus, J., M. , BENTEN, Harold, G., P. , BARGAGLI-STOFFI, Agnese, A., M. , VAN DE STEEG, Patrick
发明人： VEENDRICK, Hendricus, J., M. , BENTEN, Harold, G., P. , BARGAGLI-STOFFI, Agnese, A., M. , VAN DE STEEG, Patrick
IPC分类号： H01L27/02 , H01L27/105 , H01L27/11 , G11C11/412 , G11C11/413 , G11C11/417 , G11C29/50 , H01L21/8244
CPC分类号： H01L27/1104 , G11C11/41 , G11C11/413 , G11C29/50 , G11C29/50012 , H01L27/0207 , H01L27/105 , H01L27/11
摘要： An integrated circuit has a matrix of rows and columns of cells (10, 18, 19), each cell (10, 18, 19) comprising a first inverter (100) and a second inverter (102). First columns have a bit-line (12a,b), the first inverter inverter (100) and the second inverter (102) in each cell of the first columns being cross-coupled to each other and coupled to bit-line (12a,b) of the associated first column. A further column is provided in the matrix with bit line fragments (16) that are mutually disconnected. Delays are monitored by coupling at least the first inverters (100) of cells in respective pairs of rows in series via the bit-line fragments and measuring a delay during signal propagation through the series connection, for example by incorporating the series of inverters in a ring oscillator.
摘要翻译：集成电路具有单元行（10,18,19）的行和列的矩阵，每个单元（10,18,19）包括第一反相器（100）和第二反相器（102）。第一列具有位线（12a，b），第一列的每个单元中的第一反相器逆变器（100）和第二反相器（102）彼此交叉耦合并耦合到位线（12a， b）相关联的第一列。在矩阵中提供另一列，其中相互断开的位线片段（16）。通过经由比特线片段串联耦合至少对应的成对行中的单元的第一反相器（100）来监测延迟，并且例如通过将串联的反相器并入到串联片段中来测量在信号传播期间的延迟环形振荡器。

2. 发明申请

WO2004021100A2 CURRENT MODE SIGNALLING IN ELECTRONIC DATA PROCESSING CIRCUIT 审中-公开
标题翻译：电子数据处理电路中的电流模式信号
公开(公告)号：WO2004021100A2
公开(公告)日：2004-03-11
申请号：PCT/IB2003/003390
申请日：2003-07-31
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , KATOCH, Atul , SEEVINCK, Evert , VEENDRICK, Hendricus, J., M.
发明人： KATOCH, Atul , SEEVINCK, Evert , VEENDRICK, Hendricus, J., M.
IPC分类号： G06F
CPC分类号： H04L25/08 , H04L25/026 , H04L25/0272 , H04L25/0294
摘要： An electronic data processing circuit uses current mode signalling on a communication conductor, wherein a receiver supplies current to the communication conductor to try and keep a voltage on the conductor constant and measures the current that is needed to do so. A transition coding circuit is coupled between a data source circuit and the communication conductor, for driving the communication conductor in a first state in pulses in response to transitions in the logic signal and in a second state outside the pulses. The level that is used for indicating no change is selected so the current that needs to be supplied by the receiver is smaller when no change is signalled than when a change is signalled. Preferably only a nearly zero quiescent current is needed when there is no change.
摘要翻译：电子数据处理电路在通信导体上使用电流模式信号，其中接收器向通信导体提供电流以尝试并保持导体上的电压恒定并且测量所需的电流。转换编码电路耦合在数据源电路和通信导体之间，用于响应于逻辑信号中的转换和在脉冲之外的第二状态以脉冲方式驱动通信导体处于第一状态。选择用于指示没有变化的电平，所以当没有发出变化时，接收器需要提供的电流比发出变化时更小。当没有变化时，最好只需要几乎零静态电流。

3. 发明申请

WO2009122352A2 GLITCH MONITOR AND CIRCUIT 审中-公开
标题翻译：精灵监测和电路
公开(公告)号：WO2009122352A2
公开(公告)日：2009-10-08
申请号：PCT/IB2009/051337
申请日：2009-03-31
申请人： NXP B.V. , BARGAGLI-STOFFI, Agnese, A., M. , BENTEN, Harold, G., P., H. , VEENDRICK, Hendricus, J., M.
发明人： BARGAGLI-STOFFI, Agnese, A., M. , BENTEN, Harold, G., P., H. , VEENDRICK, Hendricus, J., M.
IPC分类号： H03K5/153 , G01R31/317 , G01R29/033
CPC分类号： G01R29/0273 , H03K5/1252
摘要： A glitch monitor 20 includes a first input 22 for connecting to a circuit node 12 of a device under test 10. The input signal is fed to a plurality of test paths 26,28,30 each with an amplifier 32,34,36 arranged to compare the voltage on the first input 22 with a reference voltage and a respective low-pass filter, wherein the low-pass filters of different test paths 26,28,30 have different frequencies. The low pass-filters may be implemented using capacitors 38,40,42. The number of glitches is determined using one or more counter 52,54 each having an up input 56 and a down input 58 connected to the outputs of different test paths 26,28,30.
摘要翻译：毛刺监测器20包括用于连接到被测器件10的电路节点12的第一输入22.输入信号被馈送到多个测试路径26,28,30，每个测试路径具有放大器32,34,36被布置为将第一输入端22上的电压与参考电压和相应的低通滤波器进行比较，其中不同测试路径26,28,30的低通滤波器具有不同的频率。低通滤波器可以使用电容器38,40,42来实现。使用一个或多个计数器52,54来确定毛刺的数量，每个计数器52,54具有连接到不同测试路径26,28,30的输出的向上输入56和向下输入58.

4. 发明申请

WO2009104130A2 POWER SUPPLY SWITCHING FOR REDUCING POWER CONSUMPTION OF INTEGRATED CIRCUITS 审中-公开
标题翻译：用于降低集成电路功耗的电源开关
公开(公告)号：WO2009104130A2
公开(公告)日：2009-08-27
申请号：PCT/IB2009/050638
申请日：2009-02-17
申请人： NXP B.V. , VEENDRICK, Hendricus, J., M. , PELGROM, Marcel , ZIEREN, Victor
发明人： VEENDRICK, Hendricus, J., M. , PELGROM, Marcel , ZIEREN, Victor
IPC分类号： H03K19/00
CPC分类号： H03K19/0016
摘要： Reduction of power consumption of integrated circuits due to reduced leakage is provided by driving an integrated circuit with a first drive potential (Vdd) and a second drive potential (Vsscore), switching the second drive potential to a ground potential in active mode using a power switch (30), and connecting a substrate potential of the integrated circuit to the ground potential.
摘要翻译：通过驱动具有第一驱动电位（Vdd）和第二驱动电位（Vsscore）的集成电路来提供由于减少泄漏而降低集成电路的功耗，使用功率将第二驱动电位切换到处于主动模式的接地电位开关（30），并将集成电路的衬底电位连接到地电位。

5. 发明申请

WO2006067733A1 ON SILICON INTERCONNECT CAPACITANCE EXTRACTION 审中-公开
标题翻译：硅互连电容提取
公开(公告)号：WO2006067733A1
公开(公告)日：2006-06-29
申请号：PCT/IB2005/054320
申请日：2005-12-19
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , THEENDAKARA, Praveen , PELGROM, Marcel , WIELING, Jean, G. , VEENDRICK, Hendricus, J., M.
发明人： THEENDAKARA, Praveen , PELGROM, Marcel , WIELING, Jean, G. , VEENDRICK, Hendricus, J., M.
IPC分类号： G01R27/26 , G01R31/30
CPC分类号： G01R31/2853 , G01R27/2605
摘要： The present invention relates to a on-chip circuit for on silicon interconnect capacitance (Cx) extraction that is self compensated for process variations in the integrated transistors. The circuit (10) comprises signal generation means (20) for generating a periodical pulse signal connected to first and to second signal delaying means (31, 32) for respective delaying said pulse signal, wherein said second signal delaying means (32) are configured to have a delay affected by said interconnect capacitance (Cx); a logical XOR gate (35) for connecting respective first and said second delay signals of said respective first and second delay means (31, 32), said logical XOR gate (35) being connected to signal integrating means (40); and said signal integrating means (40) being connected to analog to digital converting means (50). Whilst the error in conventional uncompensated systems, like delay line only, the error can be up to 30%, in the circuit according to the invention, the error due to process variations in the front-end is about 2%. Further, an output is provided in a digital format and thus, can be measured quickly with simple external hardware. Furthermore, the pulse signal frequency can be used as a monitor to measure process variations in the front-end. Moreover, since the circuit (10) is remarkably accurate and very easy to measure, it is the best choice as a process monitor for every chip fabricated in the future.
摘要翻译：本发明涉及用于硅互连电容（Cx）提取的片上电路，其被自身补偿以用于集成晶体管中的工艺变化。电路（10）包括信号产生装置（20），用于产生连接到第一和第二信号延迟装置（31,32）的周期性脉冲信号，用于各自延迟所述脉冲信号，其中所述第二信号延迟装置（32）被配置具有由所述互连电容（Cx）影响的延迟; 用于连接所述各个第一和第二延迟装置（31,32）的相应第一和第二延迟信号的逻辑异或门（35），所述逻辑异或门（35）连接到信号积分装置（40）; 并且所述信号积分装置（40）连接到模数转换装置（50）。虽然传统的无补偿系统中的误差，如延迟线，误差可高达30％，但在根据本发明的电路中，由于前端处理变化引起的误差约为2％。此外，以数字格式提供输出，因此可以用简单的外部硬件快速测量。此外，脉冲信号频率可以用作监视器来测量前端的过程变化。此外，由于电路（10）非常精确且非常容易测量，因此作为未来制造的每个芯片的过程监视器是最佳选择。

6. 发明申请

WO2003090355A3 INTEGRATED CIRCUIT WITH CLOCK SIGNAL DUTY CYCLE CONTROL 审中-公开
公开(公告)号：WO2003090355A3
公开(公告)日：2003-10-30
申请号：PCT/IB2003/001268
申请日：2003-04-01
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , RAO, Kiran, B., R. , GARG, Manish , VEENDRICK, Hendricus, J., M.
发明人： RAO, Kiran, B., R. , GARG, Manish , VEENDRICK, Hendricus, J., M.
IPC分类号： H03K5/156
摘要： An integrated circuit (100) has a clock signal distribution network (140) for distributing a parent clock pulse signal that is provided through a conductor (102). At the inputs, the clock distribution network (140) is coupled to a clock signal modifying circuit (120) and on the outputs the clock distribution network (140) is coupled to a reference generating circuit (160). The reference generating circuit (160) is arranged to provide the clock signal modifying circuit (120) with a direct current voltage that is proportional to the duty cycle of the clock pulse signal that is distributed through the clock distribution network (140). The clock signal modifying circuit (120) is arranged to alter the duty cycle of the incoming parent clock pulse signal responsive to the direct current voltage. The arrangement implements a feedback mechanism for reducing deviations from a 50% duty cycle of a clock pulse signal distributed through the clock distribution network (140).

7. 发明申请

WO2002099970A1 CONTROLLABLE DELAY CIRCUIT FOR DELAYING AN ELECTRIC SIGNAL 审中-公开
标题翻译：用于延迟电信号的可控延迟电路
公开(公告)号：WO2002099970A1
公开(公告)日：2002-12-12
申请号：PCT/IB2002/002039
申请日：2002-06-04
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VAN DIJK, Victor, E., S. , MEIJER, Rinze, I., M., P. , VEENDRICK, Hendricus, J., M.
发明人： VAN DIJK, Victor, E., S. , MEIJER, Rinze, I., M., P. , VEENDRICK, Hendricus, J., M.
IPC分类号： H03K5/13
CPC分类号： H03K5/131 , H03K5/15013
摘要： The invention relates to a controllable delay circuit (2) for delaying an electrical input signal (4) wherein the controllable delay circuit (2) is arranged for receiving an input signal (4) and at least one control signal (6), wherein, in use, the delay circuit (2) delays the input signal (4) by a delay for generating an output signal (8), wherein the delay is a function of the at least one control signal (6), wherein the delay circuit (2) comprises a first module (10) for generating a base signal (11) and at least one support signal (12) on the basis of the input signal (4) and the at least one control signal (6), wherein, in use, the phase and/or the amplitude of the at least one support signal (12) is controllable with respect to the phase and /or the amplitude of the base-signal (11) by means of the at least one control signal (6), wherein the delay circuit (2) also comprises a second module (14) connected to the first module (10), which second module (14) comprises a signal-conductor (16) and at least one support conductor (18), wherein the signal conductor (16) and the at least one support conductor extend (18), at least over a part of the conductors, essentially parallel to one another in one another's vicinity, wherein, in use, the first module (10) supplies the base signal (11) to a first end of the signal conductor (16) for generating an output-signal (8) at a second end of the signal conductor (16), and wherein, in use, the first module (10) supplies the at least one support signal (12) to the at least one support conductor (18).
摘要翻译：本发明涉及用于延迟电输入信号（4）的可控延迟电路（2），其中可控延迟电路（2）被布置用于接收输入信号（4）和至少一个控制信号（6），其中，在使用中，延迟电路（2）延迟输入信号（4）以产生输出信号（8），其中延迟是至少一个控制信号（6）的函数，其中延迟电路 2）包括用于基于输入信号（4）和至少一个控制信号（6）产生基本信号（11）和至少一个支持信号（12）的第一模块（10），其中，在使用时，所述至少一个支持信号（12）的相位和/或振幅可通过所述至少一个控制信号（6）相对于所述基本信号（11）的相位和/或振幅来控制），其中所述延迟电路（2）还包括连接到所述第一模块（10）的第二模块（14），所述第二模块（14）包括信号导管（16）和至少一个支撑导体（18），其中所述信号导体（16）和所述至少一个支撑导体延伸（18）至少在所述导体的一部分上，彼此基本上彼此平行其中，在使用中，所述第一模块（10）将所述基本信号（11）提供给所述信号导体（16）的第一端，用于在所述信号导体（16）的第二端产生输出信号（8）），并且其中在使用中，所述第一模块（10）将所述至少一个支撑信号（12）提供给所述至少一个支撑导体（18）。

8. 发明申请

WO2009122352A3 GLITCH MONITOR AND CIRCUIT 审中-公开
标题翻译：液晶显示器和电路
公开(公告)号：WO2009122352A3
公开(公告)日：2009-11-26
申请号：PCT/IB2009051337
申请日：2009-03-31
申请人： NXP BV , BARGAGLI-STOFFI AGNESE A M , BENTEN HAROLD G P H , VEENDRICK HENDRICUS J M
发明人： BARGAGLI-STOFFI AGNESE A M , BENTEN HAROLD G P H , VEENDRICK HENDRICUS J M
IPC分类号： H03K5/153 , G01R29/033 , G01R31/317
CPC分类号： G01R29/0273 , H03K5/1252
摘要： A glitch monitor 20 includes a first input 22 for connecting to a circuit node 12 of a device under test 10. The input signal is fed to a plurality of test paths 26,28,30 each with an amplifier 32,34,36 arranged to compare the voltage on the first input 22 with a reference voltage and a respective low-pass filter, wherein the low-pass filters of different test paths 26,28,30 have different frequencies. The low pass-filters may be implemented using capacitors 38,40,42. The number of glitches is determined using one or more counter 52,54 each having an up input 56 and a down input 58 connected to the outputs of different test paths 26,28,30.
摘要翻译：毛刺监视器20包括用于连接到被测器件10的电路节点12的第一输入端22.输入信号被馈送到多个测试路径26,28,30，每个测试路径26,28,30均布置有放大器32,34,36 将第一输入22上的电压与参考电压和相应的低通滤波器进行比较，其中不同测试路径26,28,30的低通滤波器具有不同的频率。低通滤波器可以使用电容器38,40,42来实现。使用一个或多个计数器52,54确定毛刺数量，每个计数器52,54具有连接到不同测试路径26,28,30的输出的上输入56和下输入58。

9. 发明申请

WO2006114727A1 SUPPLY VOLTAGE MONITORING 审中-公开
标题翻译：供电电压监测
公开(公告)号：WO2006114727A1
公开(公告)日：2006-11-02
申请号：PCT/IB2006/051214
申请日：2006-04-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , PELGROM, Marcel , PETRESCU, Violeta , VEENDRICK, Hendricus, J., M.
发明人： PELGROM, Marcel , PETRESCU, Violeta , VEENDRICK, Hendricus, J., M.
IPC分类号： G01R19/165 , G01R31/40
CPC分类号： G01R19/16552 , G01R19/28
摘要： An integrated circuit is provided with a distributed supply voltage monitoring system in which a single controller controls a plurality of voltage monitors located in respective modules of the integrated circuit. The controller and each circuit form a successive approximation analogue to digital converter. Such a system enables a small size monitoring circuit to be realised for every module of the integrated circuit.
摘要翻译：集成电路配备有分布式电源监控系统，其中单个控制器控制位于集成电路的相应模块中的多个电压监视器。控制器和每个电路形成逐次逼近的模数转换器。这样的系统能够为集成电路的每个模块实现小尺寸监视电路。

10. 发明申请

WO2006056898A1 MONITORING PHYSICAL OPERATING PARAMETERS OF AN INTEGRATED CIRCUIT 审中-公开
标题翻译：监测集成电路的物理操作参数
公开(公告)号：WO2006056898A1
公开(公告)日：2006-06-01
申请号：PCT/IB2005/053644
申请日：2005-11-07
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , VEENDRICK, Hendricus, J., M. , PELGROM, Marcel , PETRESCU, Violeta
发明人： VEENDRICK, Hendricus, J., M. , PELGROM, Marcel , PETRESCU, Violeta
IPC分类号： G01R31/317 , G01R31/28 , H03M1/46 , G01R31/26
CPC分类号： G01R31/31723 , G01R31/317
摘要： An integrated circuit comprises a plurality of sensing circuits (12), each for detecting whether a respective physical operating parameter is above or below a respective reference value. The integrated circuit contains a serial shift register (11) for shifting digital data signals that represent the respective reference values from a successive approximation update circuit (14) to the sensing circuits (12) and back to the successive approximation update circuit (14). Detection results of the sensing circuits (12) are shifted to the successive approximation update circuit (14) with the digital data signals. The successive approximation update circuit (14) is used to form the digital data so that the reference values form successive approximations of the physical operating parameter values during an analog to digital conversion process. In this way the successive approximation update circuit (14) is shared by a plurality of sensing circuits (12).
摘要翻译：集成电路包括多个检测电路（12），每个检测电路用于检测相应的物理操作参数是否高于或低于相应的参考值。集成电路包含用于将表示来自逐次逼近更新电路（14）的各个参考值的数字数据信号移位到感测电路（12）并返回到逐次逼近更新电路（14）的串行移位寄存器（11）。感测电路（12）的检测结果用数字数据信号转移到逐次逼近更新电路（14）。逐次逼近更新电路（14）用于形成数字数据，使得参考值在模数转换过程期间形成物理操作参数值的逐次逼近。以这种方式，逐次逼近更新电路（14）由多个感测电路（12）共享。

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