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1. 发明申请

WO2004090737A3 SENSE AMPLIFYING LATCH WITH LOW SWING FEEDBACK 审中-公开
标题翻译：感应放大灯具，低电压反馈
公开(公告)号：WO2004090737A3
公开(公告)日：2005-03-17
申请号：PCT/US2004010466
申请日：2004-04-02
申请人： SUN MICROSYSTEMS INC , SUTHERLAND IVAN E , BOSNYAK ROBERT J , DROST ROBERT J
发明人： SUTHERLAND IVAN E , BOSNYAK ROBERT J , DROST ROBERT J
IPC分类号： H01L23/48 , H01L25/065 , H03K3/037 , H03K5/003 , H03K17/689
CPC分类号： H03K5/003 , H01L23/48 , H01L25/0657 , H01L2225/06527 , H01L2924/00013 , H01L2924/0002 , H03K3/037 , H03K17/689 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： A system is presented for latching and amplifying a capacitively coupled inter-chip communication signal that operates by receiving an input signal on a capacitive receiver pad and feeding the input signal through an inverter to produce an output signal. The output signal is fed back through a weakened inverter to produce a feedback signal that is fed into an input of the inverter to form a latch for the input signal. The weakened inverter is biased to produce a feedback signal that swings between a high bias voltage, VH, and a low bias voltage, VL. VH is set slightly higher than the switching threshold of the inverter, and VL is set slightly lower than the switching threshold. This feedback signal causes the input signal to reside within a narrow voltage range near the switching threshold of the inverter, making the inverter sensitive to small transitions in the input signal.
摘要翻译：提出了一种用于锁存和放大电容耦合的芯片间通信信号的系统，其通过接收电容性接收器焊盘上的输入信号并通过反相器馈送输入信号以产生输出信号来操作。输出信号通过弱化逆变器反馈，产生反馈信号，该反馈信号馈送到反相器的输入端，形成输入信号的锁存器。弱化的逆变器被偏置以产生在高偏置电压VH和低偏置电压VL之间摆动的反馈信号。将VH设置为略高于逆变器的开关阈值，并将VL设置为略低于开关阈值。该反馈信号使得输入信号驻留在接近逆变器的开关阈值的窄电压范围内，使得反相器对输入信号中的小转变敏感。

2. 发明申请

WO0205076A3 POWERING IC CHIPS USING AC SIGNALS 审中-公开
标题翻译：使用交流信号供电IC芯片
公开(公告)号：WO0205076A3
公开(公告)日：2002-05-10
申请号：PCT/US0121435
申请日：2001-07-06
申请人： SUN MICROSYSTEMS INC
发明人： CRUZ JOSE M , BOSNYAK ROBERT J , VERMA SHWETABH
IPC分类号： G06F1/26 , H01F17/00 , H01F19/04 , H01F27/28 , H01L27/08 , H02M7/00 , H01L27/06
CPC分类号： H01L27/08 , G06F1/26 , H01F17/0006 , H01F19/04 , H01F27/2804 , H02M7/003
摘要： A power converter within an integrated circuit ("IC") for providing DC power to one or more function circuit, where the power converter has a transformer circuit for receiving an AC power signal and for supplying a transformed AC power signal. A converter circuit receives the transformed AC power signal and then converts the signal into a DC power signal supplied to one or more function circuit. The transformed AC power signal might either be stepped up or stepped down. The transformer circuit might comprise two coils, where a first coil is magnetically coupled to a second coil. The first coil is a first spiral and the second coil is a second spiral wherein an insulating material layer is disposed between the first spiral and the second spiral. The transformer circuit might include transformers connected in parallel or in series and may further be connected correspondingly to more than one converter circuit coupled in parallel. An IC comprising the power converter circuit can be integrated into a computer system.
摘要翻译：用于向一个或多个功能电路提供直流电力的集成电路（“IC”）内的功率转换器，其中功率转换器具有用于接收交流电力信号的变压器电路并用于提供经变换的交流电力信号。 A转换器电路接收经变换的AC电力信号，然后将该信号转换为提供给一个或多个功能电路的直流电力信号。变换后的交流电源信号可能会升高或降低。变压器电路可以包括两个线圈，其中第一线圈磁耦合到第二线圈。第一线圈是第一螺旋，第二线圈是第二螺旋形，其中绝缘材料层设置在第一螺旋和第二螺旋之间。变压器电路可以包括并联或串联连接的变压器，并且可以进一步相应地连接到并联耦合的多于一个的转换器电路。包括电源转换器电路的IC可以集成到计算机系统中。

3. 发明申请

WO2004097933A3 METHOD AND APPARATUS FOR OPTICALLY ALIGNING INTEGRATED CIRCUIT DEVICES 审中-公开
标题翻译：用于光学集成电路设备的方法和装置
公开(公告)号：WO2004097933A3
公开(公告)日：2005-03-03
申请号：PCT/US2004012443
申请日：2004-04-22
申请人： SUN MICROSYSTEMS INC , BOSNYAK ROBERT J , DROST ROBERT J
发明人： BOSNYAK ROBERT J , DROST ROBERT J
IPC分类号： H01L21/60 , H01L21/98 , H01L23/544 , G02B6/43
CPC分类号： H01L23/544 , H01L24/81 , H01L25/50 , H01L2223/54473 , H01L2223/5448 , H01L2224/16 , H01L2224/81121 , H01L2224/81801 , H01L2225/06527 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01075 , H01L2924/12035 , H01L2924/12036 , H01L2924/12041 , H01L2924/12042 , H01L2924/14 , H01L2924/00
摘要： A system that facilitates aligning a first semiconductor die with a second semiconductor die, wherein the first semiconductor die and the second semiconductor die are arranged active face to active face. The active face contains circuitry for communicating between semiconductor dies. The system starts by generating light on an active face of the first semiconductor die. The system then collimates the light within the active face of the first semiconductor die to form a first beam of light which is projected onto the second semiconductor die. Next, the system receives the first beam of light on an active face of the second semiconductor die and determines a position of the first beam of light on the active face of the second semiconductor die. The system determines an alignment of the second semiconductor die relative to the first semiconductor die based on the determined position of the first beam of light.
摘要翻译：一种有利于将第一半导体管芯与第二半导体管芯对准的系统，其中第一半导体管芯和第二半导体管芯被配置为主动面到主动面。主动面包括用于在半导体管芯之间通信的电路。该系统通过在第一半导体管芯的有源面上产生光来开始。然后，该系统使第一半导体管芯的有效面内的光准直，以形成投射到第二半导体管芯上的第一光束。接下来，系统在第二半导体管芯的有效面上接收第一光束，并确定第一光束在第二半导体管芯的有效面上的位置。该系统基于确定的第一光束的位置来确定第二半导体管芯相对于第一半导体管芯的对准。

4. 发明申请

WO02056474A3 CLOCK INTERPOLATION THROUGH CAPACITIVE WEIGHTING 审中-公开
标题翻译：通过电容加权的时钟插值
公开(公告)号：WO02056474A3
公开(公告)日：2003-04-24
申请号：PCT/US0200810
申请日：2002-01-11
申请人： SUN MICROSYSTEMS INC
发明人： DROST ROBERT J , BOSNYAK ROBERT J
IPC分类号： H03K5/08 , H03K5/13
CPC分类号： H03K5/13 , H03K5/08
摘要： A clock interpolation circuit for setting and controlling a phase of an output clock that is derived from an interpolation of multiple input clocks. Interpolation is performed by capacitively weighting the multiple clocks. A select and control circuit provides the ability to select different capacitance values to control the weighting. An optional buffer stage is also provided to sharpen the edge transitions of the interpolated clock.
摘要翻译：一种用于设置和控制从多个输入时钟的内插导出的输出时钟的相位的时钟插值电路。通过对多个时钟进行电容加权来执行插值。选择和控制电路提供选择不同电容值以控制加权的能力。还提供了可选的缓冲级，以锐化内插时钟的边沿转换。

5. 发明申请

WO02078206A3 BI-DIRECTIONAL COMMUNICATION SYSTEM WITH ECHO CANCELLATION 审中-公开
标题翻译：采用ECHO CANCELLATION的双向通信系统
公开(公告)号：WO02078206A3
公开(公告)日：2003-02-20
申请号：PCT/US0203902
申请日：2002-02-11
申请人： SUN MICROSYSTEMS INC
发明人： DROST ROBERT J , BOSNYAK ROBERT J
IPC分类号： H04L5/14 , H04L25/08 , H04L27/36 , H04L25/02 , H04B3/23 , H04L25/06
CPC分类号： H04L5/14 , H04L25/085 , H04L27/367
摘要： A bi-directional communication system and transceiver configuration are described, which employ a bi-directional reference to account for both common-mode and differential noise introduced at either end of a bi-directional communication channel. Some implementations exploit the techniques described in a bi-directional chip-to-chip communication scheme. In some implementations, the advantages of bi-directional reference techniques described herein are obtained while pre-distortion of transmitted signals is employed to compensate for intersymbol interference (ISI) in a communications channel.
摘要翻译：描述了双向通信系统和收发器配置，其采用双向参考来考虑在双向通信信道的任一端引入的共模和差分噪声。一些实现利用了双向芯片到芯片通信方案中描述的技术。在一些实施方案中，本文所述的双向参考技术的优点是获得的，同时采用发射信号的预失真来补偿通信信道中的符号间干扰（ISI）。

6. 发明申请

WO0230072A2 SWITCHED POSITIVE FEEDBACK FOR CONTROLLED RECEIVER IMPEDANCE 审中-公开
标题翻译：用于控制接收机阻抗的切换正向反馈
公开(公告)号：WO0230072A2
公开(公告)日：2002-04-11
申请号：PCT/US0131334
申请日：2001-10-05
申请人： SUN MICROSYSTEMS INC
发明人： BOSNYAK ROBERT J , CRUZ JOSE M , DROST ROBERT J
IPC分类号： H04L25/02
CPC分类号： H04L25/0292 , H04L25/0278
摘要： A receiver circuit includes a signal input, for receiving a signal input to a chip; a chip output, for supplying a buffered signal to circuitry on the chip; and a positive feedback circuit, coupled between the chip output and the signal input. The positive feedback circuit may comprise a first inverter, which has an input coupled to the signal input; a second inverter, which has an input coupled to an output of the first inverter; wherein an output of the second inverter provides the chip output.
摘要翻译：接收器电路包括用于接收输入到芯片的信号的信号输入; 芯片输出，用于向芯片上的电路提供缓冲信号; 和正反馈电路，耦合在芯片输出和信号输入之间。正反馈电路可以包括第一反相器，其具有耦合到信号输入的输入; 第二反相器，其具有耦合到所述第一反相器的输出的输入; 其中所述第二反相器的输出提供所述芯片输出。

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