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1. 发明申请

WO2006078544A3 LOW-NOISE SWITCHING VOLTAGE REGULATOR AND METHODS THEREFOR 审中-公开
标题翻译：低噪声开关电压调节器及其方法
公开(公告)号：WO2006078544A3
公开(公告)日：2008-01-24
申请号：PCT/US2006001146
申请日：2006-01-17
申请人： TIMELAB CORP , MACHESNEY BRIAN
发明人： MACHESNEY BRIAN
IPC分类号： G05F1/00 , G05F1/569 , H02J3/12
CPC分类号： H02M3/1584
摘要： Several techniques are provided to increase the efficiency and reduce the EMI of produced by a multiphase switching voltage regulator (fig.5). According to one technique, a multiphase switching voltage regulator is controlled by varying in time (fig. 9) the duration and/or position of each switching pulse for each of a plurality of channels 46(1-4) of the switching voltage regulator in response to one or more signals representing a state of each of a plurality of channels 46(1-4) of the voltage regulator. According to a second technique, a method is provided for controlling a multiphase switching 250(1 -4)voltage regulator comprising operating each channel 46(1-4) of the voltage regulator at a different frequency. The timing of the switching pulses to each channel 46(1-4) is scheduled to avoid time-overlap (fig. 9)of switching pulses for two or more channels 46(1-4).
摘要翻译：提供了几种技术来提高效率并降低由多相开关电压调节器产生的EMI（图5）。根据一种技术，多相开关电压调节器通过时间变化（图9）控制开关电压调节器的多个通道46（1-4）中的每个开关脉冲的持续时间和/或位置，响应于表示电压调节器的多个通道46（1-4）中的每一个的状态的一个或多个信号。根据第二技术，提供了一种用于控制多相开关250（1-4）电压调节器的方法，其包括以不同的频率操作电压调节器的每个通道46（1-4）。调度到每个通道46（1-4）的切换脉冲的定时被调度以避免两个或更多个通道46（1-4）的切换脉冲的时间重叠（图9）。

2. 发明申请

WO2006083555A3 DIGITALLY PROGRAMMABLE DELAY CIRCUIT WITH PROCESS POINT TRACKING 审中-公开
标题翻译：具有过程点跟踪的数字可编程延迟电路
公开(公告)号：WO2006083555A3
公开(公告)日：2006-11-23
申请号：PCT/US2006001727
申请日：2006-01-19
申请人： TIMELAB CORP , CARLEY ADAM L , ALLEN DANIEL J , MANDRY JAMES E
发明人： CARLEY ADAM L , ALLEN DANIEL J , MANDRY JAMES E
IPC分类号： H03K17/296
CPC分类号： H03K5/133 , H03K2005/00065 , H03K2005/00221
摘要： A digitally programmable delay circuit comprising a plurality of transistors connected in parallel with each other and to a line carrying a signal having an edge to be delayed.
摘要翻译：一种数字可编程延迟电路，包括彼此并联连接的多个晶体管以及承载具有待延迟边缘的信号的线。

3. 发明申请

WO2004077514A2 CLOCKTREE TUNING SHIMS AND SHIM TUNING METHOD 审中-公开
标题翻译： CLOCKTREE TUNING SHIMS和SHIM TUNING方法
公开(公告)号：WO2004077514A2
公开(公告)日：2004-09-10
申请号：PCT/US2004005375
申请日：2004-02-24
申请人： TIMELAB CORP , MANDRY JAMES E
发明人： MANDRY JAMES E
IPC分类号： G06F17/50 , H01L20060101 , H01L21/00 , H01L
CPC分类号： G06F17/5045
摘要： A digital storage medium storing electronic data for use with a clock tree design tool to design a clock distribution network within an integrated circuit, the electronic data implementing a library of shim cells, wherein each of the shim cells in the library represents a physical embodiment of a different clock driver cell of a plurality of clock driver cells and wherein all of the shim cells in the library are interchangeable in the clock distribution network design without requiring any change in placement or routing within the integrated circuit to maintain compliance with design requirements for the integrated circuit.
摘要翻译：一种存储与时钟树设计工具一起使用的电子数据的数字存储介质，用于设计集成电路内的时钟分配网络，该电子数据实现了一个垫片单元库，其中库中的每个垫片单元表示多个时钟驱动器单元中的不同时钟驱动器单元，并且其中库中的所有垫片单元在时钟分配网络设计中是可互换的，而不需要在集成电路内布置或布线的任何改变以维持符合设计要求集成电路。

4. 发明申请

WO2004015743A3 CLOCK DISTRIBUTOR CIRCUIT FOR MAINTAINING A PHASE RELATIONSHIP BETWEEN REMOTE OPERATING NODES AND A REFERENCE CLOCK ON A CHIP 审中-公开
标题翻译：用于维持远程操作数和芯片上的参考时钟之间的相位关系的时钟分配器电路
公开(公告)号：WO2004015743A3
公开(公告)日：2004-06-17
申请号：PCT/US0324315
申请日：2003-08-05
申请人： TIMELAB CORP
发明人： CARLEY ADAM L
IPC分类号： G06F1/10 , H03K5/13 , H03K5/15 , G06F17/50
CPC分类号： G06F1/10
摘要： A clock signal distributor circuit (12) for maintaining a phase relationship between one or more remote operating nodes (15, 17) and a reference clock on a chip, wherein there is a clock signal drive path and a clock signal sense path in a distribution limb (14, 16) for each remote node (15, 17). The clock signal distributor circuit (12) comprises a variable signal delay circuit in the clock signal drive path, a variable signal delay circuit in the clock signal sense path, and a feedback circuit that causes at least one variable signal delay circuit to change its signal delay based on phase of signal on the clock signal sense path.
摘要翻译：一种用于维持一个或多个远程操作节点（15,17）和芯片上的参考时钟之间的相位关系的时钟信号分配器电路（12），其中在分配中存在时钟信号驱动路径和时钟信号检测路径肢体（14,16），用于每个远程节点（15,17）。时钟信号分配器电路（12）包括时钟信号驱动路径中的可变信号延迟电路，时钟信号检测路径中的可变信号延迟电路和使至少一个可变信号延迟电路改变其信号的反馈电路基于时钟信号感测路径上的信号相位延迟。

5. 发明申请

WO2006119065A3 DENSE-TAP TRANSVERSAL FILTER WITH ELEMENTARY COEFFICIENTS 审中-公开
标题翻译：带有基本系数的DENSE-TAP TRANSVERSAL FILTER
公开(公告)号：WO2006119065A3
公开(公告)日：2008-01-10
申请号：PCT/US2006016348
申请日：2006-05-01
申请人： TIMELAB CORP , MACHESNEY BRIAN
发明人： MACHESNEY BRIAN
IPC分类号： H04B1/10 , H03D3/24
CPC分类号： H03H15/02 , H04L25/03038 , H04L25/03057
摘要： A signal processing method and device are provided to perform an arbitrary signal processing or filtering function on a continuous time signal. An input continuous time signal is successively delayed by a plurality of delay elements to produce a plurality of delayed signals.. A corresponding coefficient is applied to some or all of the plurality of delayed signals to produce a plurality of weighted signals. The plurality of weighted signals are combined to produce a processed output signal. The coefficients applied to some or all of the delayed signals are set to values so as to perform a desired signal filtering or processing function of the input continuous time signal in producing the processed output signal.
摘要翻译：提供信号处理方法和装置以对连续时间信号执行任意信号处理或滤波功能。输入连续时间信号被多个延迟元件连续延迟，以产生多个延迟信号。对应的系数被施加到多个延迟信号中的一些或全部以产生多个加权信号。多个加权信号被组合以产生经处理的输出信号。应用于一些或所有延迟信号的系数被设置为值，以便在产生经处理的输出信号时执行输入的连续时间信号的期望的信号滤波或处理功能。

6. 发明申请

WO2006083556A3 DELAY CIRCUIT FOR SYNCHRONIZING ARRIVAL OF A CLOCK SIGNAL AT DIFFERENT CIRCUIT BOARD POINTS 审中-公开
标题翻译：用于同步不同电路板时钟信号的延迟电路
公开(公告)号：WO2006083556A3
公开(公告)日：2007-01-04
申请号：PCT/US2006001728
申请日：2006-01-19
申请人： TIMELAB CORP , CARLEY ADAM L , ALLEN DANIEL J , MANDRY JAMES E
发明人： CARLEY ADAM L , ALLEN DANIEL J , MANDRY JAMES E
IPC分类号： G06F1/04
CPC分类号： H03H11/265
摘要： A clock signal generation system and method to distribute at least one clock signal to a plurality of points on a circuit board using a plurality of digitally programmable delay circuits (10) each of which delays the clock signal (Clockln) by a desired amount so as to synchronize arrival of the clock signal when distributed to each of the plurality of points on the circuit. Each digitally programmable delay circuits (10) comprises a plurality of circuit stages (100(l)-100(N)) connected in series with each other. Each circuit stage comprises a plurality of transistors of a first type (e.g., P-type) connected in parallel with each other, and a plurality of transistors of a second type (c.g., N-type) connected in parallel with each other in each circuit stage, one or more of the plurality of transistors of the first type are selected to delay a rising edge, and one or more of the plurality of transistors of a second type are selected to delay a falling edge.
摘要翻译：一种时钟信号产生系统和方法，用于使用多个数字可编程延迟电路（10）将至少一个时钟信号分配到电路板上的多个点，每个延迟电路将时钟信号（Clock1n）延迟期望的量，以便当分配给电路上的多个点中的每个点时，同步时钟信号的到达。每个数字可编程延迟电路（10）包括彼此串联连接的多个电路级（100（1）-100（N））。每个电路级包括彼此并联连接的多个第一类型的晶体管（例如，P型），以及在每个电路平台中彼此并联连接的第二类型（cg，N型）的多个晶体管选择第一类型的多个晶体管中的一个或多个以延迟上升沿，并且选择第二类型的多个晶体管中的一个或多个延迟下降沿。

7. 发明申请

WO2004079911A3 CLOCK AND DATA RECOVERY METHOD AND APPARATUS 审中-公开
标题翻译：时钟和数据恢复方法和设备
公开(公告)号：WO2004079911A3
公开(公告)日：2005-04-28
申请号：PCT/US2004006510
申请日：2004-03-04
申请人： TIMELAB CORP , ALLEN DANIEL J
发明人： ALLEN DANIEL J
IPC分类号： H03L7/00 , H03L7/087 , H03L7/091 , H03L7/093 , H04L7/00 , H04L7/033
CPC分类号： H03L7/00 , H03L7/087 , H03L7/091 , H03L7/093 , H03L2207/50 , H04L7/0008 , H04L7/0331 , H04L7/0337 , H04L7/0338
摘要： A method of processing a serial data stream carrying data at a rate established by an underlying clock signal, the method involving: time-stamping each of the transitions of a sequence of transitions within the serial data stream to thereby generate a sequence of time-stamps; and based at least in part on the sequence of timestamps, recovering the data from the serial data stream.
摘要翻译：一种以由底层时钟信号建立的速率处理携带数据的串行数据流的方法，所述方法包括：对串行数据流内的一系列转换的每个转换进行时间戳，从而产生一系列时间戳 ; 并且至少部分地基于时间戳的顺序，从串行数据流中恢复数据。

8. 发明申请

WO2005077034A2 HIGH SPEED SERIALIZER-DESERIALIZER 审中-公开
标题翻译：高速串联器 - DESERIALIZER
公开(公告)号：WO2005077034A2
公开(公告)日：2005-08-25
申请号：PCT/US2005003992
申请日：2005-02-09
申请人： TIMELAB CORP , CARLEY ADAM L
发明人： CARLEY ADAM L
IPC分类号： H03M5/08 , H03M7/00
CPC分类号： H03M5/08
摘要： A high speed serializer-deserializer (SerDes) that passes significantly more data through a channel for a given analog bandwidth and signal-to-noise ratio. This SerDes technique involves converting a plurality of bits to be transferred to positions of edges of a waveform that is transmitted over at least one transmission wire from a source to a destination. The plurality of bits are converted to edges in order to position edges such that more than k inter-edge spacings are possible over a range of spacings between T and kT, where k is a real number greater than 1 and T is the minimum spacing between consecutive edges. An edge position translation scheme that maps patterns in a stream of input bits to a corresponding spacing between a rising edge and a falling edge of the waveform, or between a falling edge and a rising edge of the waveform. The bits are recovered at the destination by detecting the edges in the received waveform at the destination and driving a stream of binary numbers representing time intervals between detected consecutive edges (inter-edge spacings). The stream of binary numbers is decoded according to the edge position translation scheme to recover corresponding bits.
摘要翻译：一种高速串行器 - 解串器（SerDes），通过通道显示更多的数据，以获得给定的模拟带宽和信噪比。该SerDes技术涉及将要传送的多个比特转换到通过至少一根传输线从源传输到目的地的波形边缘的位置。将多个位转换为边缘以便定位边缘，使得在T和kT之间的间隔范围内多于k个边缘间隔是可能的，其中k是大于1的实数，T是大于1的实数，并且T是连续边缘边缘位置转换方案，将输入比特流中的图形映射到波形的上升沿和下降沿之间的相应间隔，或波形的下降沿和上升沿之间。通过检测目的地的接收波形中的边缘，并且驱动表示检测到的连续边缘之间的时间间隔（边缘间隔）的二进制数据流，在目的地恢复比特。根据边缘位置转换方案对二进制数字流进行解码，以恢复相应的位。

9. 发明申请

WO2006044586A3 SPREAD SPECTRUM CLOCK SIGNAL GENERATION SYSTEM AND METHOD 审中-公开
标题翻译：传播频谱信号发生系统和方法
公开(公告)号：WO2006044586A3
公开(公告)日：2007-02-01
申请号：PCT/US2005036918
申请日：2005-10-12
申请人： TIMELAB CORP , CARLEY ADAM L , ALLEN DANIEL J
发明人： CARLEY ADAM L , ALLEN DANIEL J
IPC分类号： H04B1/69
CPC分类号： G06F1/08
摘要： A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spectrum modulation to the clock signal. A programmable modulator is provided that generates digital values representing edge positions for edges of a clock signal based on at least one of a time-varying period value and a time-varying duty-cycle value. The programmable modulator may comprise a first circuit, called a period modulation circuit, that generates a time-varying digital period value, and a second circuit, called a duty-cycle modulation circuit, that generates a time-varying digital duty-cycle value. The time-varying period values and time-varying duty cycle values are processed to produce a digital edge position value that specifies an edge position for a clock signal. The programmable modulator is coupled to an arbitrary waveform synthesizer that generates timing for edges of the clock signal based on the edge position values. A variety of modulations can be imposed on the clock signal using these techniques, including triangle wave modulation, near-triangle modulation, random and pseudo-random modulation.
摘要翻译：一种用于产生具有扩频调制的时钟信号的系统和方法。该方法涉及通过从针对每个边缘的定时的数字表示产生时钟信号的边缘的边缘位置来产生时钟信号，以将扩频调制传递给时钟信号。提供了一种可编程调制器，其基于时变周期值和时变占空比值中的至少一个，生成表示时钟信号的边沿的边缘位置的数字值。可编程调制器可以包括产生时变数字周期值的称为周期调制电路的第一电路和产生时变数字占空比值的称为占空比调制电路的第二电路。处理时变周期值和时变占空比值以产生指定时钟信号的边沿位置的数字边沿位置值。可编程调制器耦合到任意波形合成器，其基于边缘位置值产生时钟信号的边沿的定时。使用这些技术可以对时钟信号施加各种调制，包括三角波调制，近三角调制，随机和伪随机调制。

10. 发明申请

WO2006076206A2 POWER MANAGEMENT OF COMPONENTS HAVING CLOCK PROCESSING CIRCUITS 审中-公开
标题翻译：具有时钟处理电路的组件的电源管理
公开(公告)号：WO2006076206A2
公开(公告)日：2006-07-20
申请号：PCT/US2006000350
申请日：2006-01-09
申请人： TIMELAB CORP , ALLEN DANIEL J
发明人： ALLEN DANIEL J
IPC分类号： G06F1/26
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3243 , Y02D10/126 , Y02D10/152
摘要： A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied to the clock processing circuit is changed based on operating characteristics of a voltage regulator module (VRM) or power supply unit so as to maintain acceptable operating parameters of the power supply unit during a change in frequency of a cock signal. Data pertaining to operating characteristics of the VRM or power supply may be one or both of two forms. In one form, this data is determined a priori from simulations or experiments made on a particular VRM or power supply unit and used to generate and store parameters that are known to optimally (quickly and without degradation of VRM or power supply performance) change the frequency of the clock processing circuit. In another form, the operation conditions of the VRM or power supply unit are monitored in real-time as a frequency transition is occurring. In addition, control signals to a VRM or power supply may be monitored to control how changes are made to the frequency of a clock signal. Further still, the power available from a VRM or power supply is monitored and a clock signal frequency to one or more system components is controlled to balance the load to the power available from the VRM or power supply.
摘要翻译：一种用于管理使用时钟处理电路的组件的功耗的方法和系统，以从提供给时钟处理电路的时钟信号产生由该组件使用的处理时钟信号。提供给时钟处理电路的时钟信号的频率基于电压调节器模块（VRM）或电源单元的操作特性而改变，以便在公鸡的频率变化期间保持电源单元的可接受的操作参数信号。关于VRM或电源的操作特性的数据可以是两种形式之一或两者。在一种形式中，该数据先于在特定VRM或电源单元上进行的仿真或实验确定，并用于生成和存储已知最佳（快速且无劣化VRM或电源性能）的参数，以改变频率的时钟处理电路。在另一种形式中，当发生频率转换时，VRM或电源单元的操作条件被实时监控。此外，可以监控对VRM或电源的控制信号，以控制如何对时钟信号的频率进行改变。此外，还可以监控VRM或电源中提供的电源，并控制一个或多个系统组件的时钟信号频率，以平衡负载与VRM或电源可用的功率。

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