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1. 发明授权

US06836435B2 Compaction scheme in NVM 有权
公开(公告)号：US06836435B2
公开(公告)日：2004-12-28
申请号：US10319664
申请日：2002-12-13
申请人： Chi Nan Brian Li
发明人： Chi Nan Brian Li
IPC分类号： G11C1600
CPC分类号： G11C16/3468 , G11C16/14
摘要： A method of erasing a semiconductor nonvolatile memory (NVM) so as to compact the distribution of cell erased threshold voltages within a restricted range around a target erased threshold voltage. Erase pulses are applied to NVM cells until a determination is made by, for example, sensing total column source current that adequate erasure has been realized. An optional soft program signal may be applied subsequent to each erase pulse in order to impede over-erasure. Once erasure has been verified, the distribution of erased threshold voltages is compacted by sustaining, for a predetermined length of time, the simultaneous application of a gate voltage that is equal to the target erased threshold voltage and a highly positive drain voltage.

2. 发明授权

US06819593B2 Architecture to suppress bit-line leakage 有权
标题翻译：抑制位线泄漏的体系结构
公开(公告)号：US06819593B2
公开(公告)日：2004-11-16
申请号：US10318458
申请日：2002-12-13
申请人： Der-Shin Shyu , Hung-Cheng Sung , Li-Wen Chang , Han-Ping Chen , Chen-Ming Huang , Ya-Chen Kao
发明人： Der-Shin Shyu , Hung-Cheng Sung , Li-Wen Chang , Han-Ping Chen , Chen-Ming Huang , Ya-Chen Kao
IPC分类号： G11C1600
CPC分类号： G11C16/3418 , G11C16/0425
摘要： A method to suppress bit-line leakage in a nonvolatile memory cell is achieved. The method comprises providing an array of nonvolatile memory cells comprising source and bulk terminals. The array comprises a plurality of subarrays. The sources of all the nonvolatile cells in each subarray are coupled together to form a common subarray source. Bulks of all the nonvolatile cells in the array are coupled together to form a common array bulk. A first, non-zero voltage is forced between the common subarray source and the common array bulk for a first subarray that is selected for an access operation. A second, non-zero voltage is forced between the common subarray source and the common array bulk for a second subarray that is not selected for an access operation. The second, non-zero voltage inhibits bit line leakage in the second subarray.
摘要翻译：实现了在非易失性存储单元中抑制位线泄漏的方法。该方法包括提供包括源极和体积端子的非易失性存储器单元的阵列。阵列包括多个子阵列。每个子阵列中的所有非易失性单元的源耦合在一起以形成公共的子阵列源。阵列中所有非易失性单元的容量被耦合在一起以形成共同的阵列体。对于为访问操作选择的第一子阵列，第一个非零电压被强制在公共子阵列源和公共阵列块之间。第二个非零电压被强制在公共子阵列源和公共阵列块之间，用于未被选择用于访问操作的第二子阵列。第二个非零电压禁止第二个子阵列中的位线泄漏。

3. 发明授权

US06819590B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US06819590B2
公开(公告)日：2004-11-16
申请号：US10106358
申请日：2002-03-27
申请人： Akira Goda , Mitsuhiro Noguchi
发明人： Akira Goda , Mitsuhiro Noguchi
IPC分类号： G11C1600
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5671 , G11C16/0416 , G11C16/0483 , G11C16/0491 , G11C16/3418
摘要： Each of a plurality of memory elements of a semiconductor memory includes at least one control terminal which switches the ON state and OFF state of the current path between the current terminals, and an information storage portion interposed between the current path and the control terminal to provide a threshold voltage. This information storage portion selectively stores electrically erasable and programmable discrete N-valued (N is an integer of 2 or more) data. As the threshold voltage, the information storage portion provides first to Nth threshold voltages which are discrete in ascending order of voltage in correspondence with the N-valued data. All the first to Nth threshold voltages of the plurality of memory elements are higher than the lower one of voltages applied to the current terminals in data read.
摘要翻译：半导体存储器的多个存储元件中的每一个包括至少一个控制端子，其切换当前端子之间的电流路径的导通状态和截止状态，以及插入在电流路径和控制端子之间的信息存储部分，以提供阈值电压。该信息存储部选择性地存储电可擦除和可编程的离散N值（N为2以上的整数）数据。作为阈值电压，信息存储部分提供与N值数据对应的以电压升序离散的第一至第N阈值电压。多个存储元件的所有第一至第N阈值电压高于在数据读取中施加到当前端子的电压中的较低值。

4. 发明授权

US06791883B2 Program and erase in a thin film storage non-volatile memory 有权
标题翻译：在薄膜存储非易失性存储器中编程和擦除
公开(公告)号：US06791883B2
公开(公告)日：2004-09-14
申请号：US10178658
申请日：2002-06-24
申请人： Craig T. Swift , Jane A. Yater , Alexander B. Hoefler , Ko-Min Chang , Erwin J. Prinz , Bruce L. Morton
发明人： Craig T. Swift , Jane A. Yater , Alexander B. Hoefler , Ko-Min Chang , Erwin J. Prinz , Bruce L. Morton
IPC分类号： G11C1600
CPC分类号： G11C16/0466
摘要： A non-volatile memory having a thin film dielectric storage element is programmed by hot carrier injection (HCI) and erased by tunneling. The typical structure for the memory cells for this type of memory is silicon, oxide, nitride, oxide, and silicon (SONOS). The hot carrier injection provides relatively fast programming for SONOS, while the tunneling provides for erase that avoids the difficulties with the hot hole erase (HHE) type erase that generally accompanies hot carrier injection for programming. HHE is significantly more damaging to dielectrics leading to reliability issues. HHE also has a relatively narrow area of erasure that may not perfectly match the pattern for the HCI programming leaving an incomplete erasure. The tunnel erase effectively covers the entire area so there is no concern about incomplete erase. Although tunnel erase is slower than HHE, erase time is generally less critical in a system operation than is programming time.
摘要翻译：具有薄膜电介质存储元件的非易失性存储器通过热载流子注入（HCI）编程并通过隧道擦除。这种存储器的存储单元的典型结构是硅，氧化物，氮化物，氧化物和硅（SONOS）。热载波注入为SONOS提供相对快速的编程，而隧道提供擦除，避免了通常伴随热载流子注入进行编程的热孔擦除（HHE）类型擦除的困难。 HHE对电介质的破坏性更大，导致可靠性问题。 HHE还具有相对较窄的擦除区域，可能不完全匹配HCI编程的模式，从而导致不完整的擦除。隧道擦除有效地覆盖整个区域，所以不用担心不完全擦除。虽然隧道擦除比HHE慢，但擦除时间在系统操作中通常不如编程时间那么重要。

5. 发明授权

US06754103B2 Method and apparatus for programming and testing a non-volatile memory cell for storing multibit states 有权
标题翻译：用于编程和测试用于存储多位状态的非易失性存储单元的方法和装置
公开(公告)号：US06754103B2
公开(公告)日：2004-06-22
申请号：US10288361
申请日：2002-11-04
申请人： Jack E. Frayer
发明人： Jack E. Frayer
IPC分类号： G11C1600
CPC分类号： G11C29/50004 , G11C11/5628 , G11C16/04 , G11C16/12 , G11C16/30 , G11C16/3454 , G11C29/50
摘要： The present invention is a method and apparatus to program and/or to test a non-volatile memory cell to be programmed into a plurality of bit states (with each bit state having two states). More particularly, the method rapidly programs or tests such a cell by hard programming the cell when the cell is to be programmed into a state which permits the minimal amount of current t o flow in the channel. The charge pump integral with the memory device is capable of generating two types of pulses: a small incremental pulse, and a “hard” pulse, which is used only if the cell is to be programmed into the fully programmed state. For the states between fully programmed and fully erased, the incremental pulse is used to incrementally program the cell.
摘要翻译：本发明是一种编程和/或测试要编程为多个位状态（每个位状态具有两种状态）的非易失性存储单元的方法和装置。更具体地说，该方法通过对单元进行硬编程来快速编程或测试这样一个单元，当单元被编程到允许通道中最小量的电流流动的状态时。与存储器件集成的电荷泵能够产生两种类型的脉冲：小增量脉冲和“硬”脉冲，仅在将单元编程为完全编程状态时才使用。对于完全编程和完全擦除之间的状态，增量脉冲用于增量编程单元。

6. 发明授权

US06724659B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06724659B2
公开(公告)日：2004-04-20
申请号：US10338018
申请日：2003-01-08
申请人： Shunichi Saeki , Hideakii Kurata , Naoki Kobayashi
发明人： Shunichi Saeki , Hideakii Kurata , Naoki Kobayashi
IPC分类号： G11C1600
CPC分类号： G11C16/3459 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/28 , G11C16/3454 , G11C2211/5621
摘要： In a nonvolatile semiconductor memory device, in which programming operation of data is conducted by injecting hot electron generated between a source layer and a drain layer of a memory cell into a floating gate between the both layers on an upper potion of surface of a semiconductor, while verification of the data programmed is conducted by making discrimination on whether voltage applied to the drain is kept or not, depending upon a height of a threshold voltage of the memory cell.
摘要翻译：在非易失性半导体存储器件中，其中数据的编程操作是通过在半导体的上部表面上注入在存储单元的源极层和漏极层之间产生的热电子到两个层之间的浮动栅极来进行的，通过根据存储单元的阈值电压的高度判断是否保持施加到漏极的电压来进行对编程数据的验证。

7. 发明授权

US06646922B2 Nonvolatile memory and method of driving the same 有权
公开(公告)号：US06646922B2
公开(公告)日：2003-11-11
申请号：US10154556
申请日：2002-05-24
申请人： Kiyoshi Kato
发明人： Kiyoshi Kato
IPC分类号： G11C1600
CPC分类号： B82Y10/00 , G11C11/5642 , G11C16/0416 , G11C16/0466 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/28 , G11C16/3418 , G11C16/3431 , G11C2216/06
摘要： The nonvolatile memory according to the present invention can precisely read information included in a memory transistor subject to a shift phenomenon because electrical read is performed on the memory transistor by using a reference voltage generated from a refresh memory transistor. Further, according to the present invention, the period of time during which the refresh operation is performed can be longer than before, which improves the reliability of information stored in the memory transistor. Furthermore, the margin between distributions of threshold voltages can be reduced, which improves the scale of integration of the multilevel nonvolatile memory.

8. 发明授权

US06580645B1 Page buffer of a flash memory 失效
标题翻译： Flash存储器的页面缓冲区
公开(公告)号：US06580645B1
公开(公告)日：2003-06-17
申请号：US10065660
申请日：2002-11-07
申请人： Yen-Tai Lin , Chien-Hung Ho
发明人： Yen-Tai Lin , Chien-Hung Ho
IPC分类号： G11C1600
CPC分类号： G11C16/10 , G11C2216/14
摘要： A page buffer for a flash memory has a power supply, a latch circuit, and a plurality of switches. Initially the switches are controlled for resetting a first terminal and a second terminal of the latch circuit to a respective predetermined voltage. If a memory cell is not to be programmed, the voltage levels of the first terminal and the second terminal remain unchanged when the power supply outputs a programming voltage. If the memory cell is to be programmed, the voltage levels of the first terminal and the second terminal are changed when the power supply outputs the programming voltage. Each of the first terminal and the second terminal will regain the predetermined voltage after the memory cell is completely programmed to store a predetermined binary digit.
摘要翻译：闪存的页缓冲器具有电源，锁存电路和多个开关。最初，开关被控制用于将锁存电路的第一端子和第二端子复位到相应的预定电压。如果不编程存储单元，则当电源输出编程电压时，第一端子和第二端子的电压电平保持不变。如果要对存储器单元进行编程，则当电源输出编程电压时，第一端子和第二端子的电压电平发生变化。在存储器单元被完全编程以存储预定二进制数位之后，第一端子和第二端子中的每一个将重新获得预定电压。

9. 发明授权

US06549465B2 Nonvolatile semiconductor memory well voltage setting circuit without latchup and semiconductor memory device provided with the circuit 有权
公开(公告)号：US06549465B2
公开(公告)日：2003-04-15
申请号：US10083661
申请日：2002-02-27
申请人： Yasuaki Hirano , Shuichiro Kouchi , Yoshihisa Sekiguchi
发明人： Yasuaki Hirano , Shuichiro Kouchi , Yoshihisa Sekiguchi
IPC分类号： G11C1600
CPC分类号： G11C16/30 , G11C16/14
摘要： A well voltage setting circuit has a P-MOS transistor for applying erase pulse, a first N-MOS transistor for applying a reference voltage Vss to a P-well in a shutdown sequence after erase pulse application, and a second N-MOS transistor for forcing the P-well to the reference voltage Vss during write and read. The first N-MOS transistor has a driving capacity set to about {fraction (1/50)} of that of the second N-MOS transistor, so that a time for forcing the P-well to the reference voltage Vss is long enough to prevent occurrence of local latch-up during erase.

10. 发明授权

US06525968B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US06525968B2
公开(公告)日：2003-02-25
申请号：US10173305
申请日：2002-06-18
申请人： Shunichi Saeki , Hideakii Kurata , Naoki Kobayashi
发明人： Shunichi Saeki , Hideakii Kurata , Naoki Kobayashi
IPC分类号： G11C1600
CPC分类号： G11C16/3459 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/28 , G11C16/3454 , G11C2211/5621
摘要： In a nonvolatile semiconductor memory device, in which programming operation of data is conducted by injecting hot electron generated between a source layer and a drain layer of a memory cell into a floating gate between the both layers on an upper potion of surface of a semiconductor, while verification of the data programmed is conducted by making discrimination on whether voltage applied to the drain is kept or not, depending upon a height of a threshold voltage of the memory cell.

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