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1. 发明申请

US20150206594A1 FUSE CIRCUIT WITH TEST MODE 有权
标题翻译：带测试模式的保险丝电路
公开(公告)号：US20150206594A1
公开(公告)日：2015-07-23
申请号：US14161927
申请日：2014-01-23
申请人： ALEXANDER B. HOEFLER
发明人： ALEXANDER B. HOEFLER
IPC分类号： G11C17/16 , G11C29/00
CPC分类号： G11C17/16 , G11C17/18 , G11C29/00 , G11C29/027
摘要： During a program operation of a fuse cell of a fuse circuit, all of a group of select transistors of a fuse cell are made conductive to program the fuse cell. During a test operation of a fuse cell of the fuse circuit, less than all of the group of select transistors are made conductive so that current less than a programming current flows through the fuse cell.
摘要翻译：在保险丝电路的熔丝单元的编程操作期间，使熔丝单元的一组选择晶体管导通以对熔丝单元进行编程。在保险丝电路的熔丝单元的测试操作期间，小于全部选择晶体管的组导通，使得小于编程电流的电流流过熔丝单元。

2. 发明授权

US08254186B2 Circuit for verifying the write enable of a one time programmable memory 有权
标题翻译：用于验证一次可编程存储器的写使能的电路
公开(公告)号：US08254186B2
公开(公告)日：2012-08-28
申请号：US12771209
申请日：2010-04-30
申请人： Alexander B. Hoefler , Mohamed S. Moosa
发明人： Alexander B. Hoefler , Mohamed S. Moosa
IPC分类号： G11C7/22
CPC分类号： G11C17/16 , G11C17/18
摘要： A memory system including a one time programmable (OTP) memory is provided. The memory system further includes a write enable verification circuit including an asymmetric inverter stage and a symmetric inverter stage coupled at a node. The write enable verification circuit is configured to receive a write enable signal. When the write enable signal changes from a first voltage level to a second voltage level, a voltage at the node changes at a first rate and wherein when the write enable signal changes from the second voltage level to the first voltage level, the voltage at the node changes at a second rate higher than the first rate. The write enable verification circuit is further configured to generate a verified write enable signal for enabling programming of the OTP memory.
摘要翻译：提供了包括一次可编程（OTP）存储器的存储器系统。存储器系统还包括写使能验证电路，其包括耦合在节点处的非对称反相器级和对称反相器级。写使能验证电路被配置为接收写使能信号。当写使能信号从第一电压电平变为第二电压电平时，节点处的电压以第一速率变化，并且其中当写使能信号从第二电压电平变为第一电压电平时，节点以比第一速率高的第二速率改变。写使能验证电路还被配置为产生经验证的写使能信号，以使能对OTP存储器进行编程。

3. 发明申请

US20110267869A1 CIRCUIT FOR VERIFYING THE WRITE ENABLE OF A ONE TIME PROGRAMMABLE MEMORY 有权
标题翻译：用于验证一次性可编程存储器的写入电路的电路
公开(公告)号：US20110267869A1
公开(公告)日：2011-11-03
申请号：US12771209
申请日：2010-04-30
申请人： Alexander B. Hoefler , Mohamed S. Moosa
发明人： Alexander B. Hoefler , Mohamed S. Moosa
IPC分类号： G11C17/00 , G11C7/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A memory system including a one time programmable (OTP) memory is provided. The memory system further includes a write enable verification circuit including an asymmetric inverter stage and a symmetric inverter stage coupled at a node. The write enable verification circuit is configured to receive a write enable signal. When the write enable signal changes from a first voltage level to a second voltage level, a voltage at the node changes at a first rate and wherein when the write enable signal changes from the second voltage level to the first voltage level, the voltage at the node changes at a second rate higher than the first rate. The write enable verification circuit is further configured to generate a verified write enable signal for enabling programming of the OTP memory.
摘要翻译：提供包括一次可编程（OTP）存储器的存储器系统。存储器系统还包括写使能验证电路，其包括耦合在节点处的非对称反相器级和对称反相器级。写使能验证电路被配置为接收写使能信号。当写使能信号从第一电压电平变化到第二电压电平时，节点处的电压以第一速率变化，并且其中当写使能信号从第二电压电平变为第一电压电平时，节点以比第一速率高的第二速率改变。写使能验证电路还被配置为产生经验证的写使能信号，以使能对OTP存储器进行编程。

4. 发明授权

US07583554B2 Integrated circuit fuse array 有权
标题翻译：集成电路保险丝阵列
公开(公告)号：US07583554B2
公开(公告)日：2009-09-01
申请号：US11681421
申请日：2007-03-02
申请人： Alexander B. Hoefler
发明人： Alexander B. Hoefler
IPC分类号： G11C17/18
CPC分类号： G11C17/16 , G11C17/18
摘要： The fuse array described herein is very compact and uses little semiconductor area because of its crosspoint architecture. The disclosed crosspoint architecture reduces the number of conductors that must be run horizontally or vertically through each bit cell. As a result, the area required for each bit cell is significantly reduced. In one embodiment, a selected set of voltages on various wordlines and bitlines are used to program the fuses to produce programmed fuses having a tighter distribution of impedances. Similarly, a selected set of voltages on various wordlines and bitlines are used to read the fuses.
摘要翻译：这里描述的熔丝阵列是非常紧凑的，由于其交叉点架构而使用很少的半导体区域。所公开的交叉点架构减少了必须通过每个位单元水平或垂直运行的导体的数量。结果，每个位单元所需的面积显着减小。在一个实施例中，使用各种字线和位线上的所选择的一组电压来对保险丝编程以产生具有更紧密的阻抗分布的编程保险丝。类似地，使用各种字线和位线上的一组选定的电压来读取保险丝。

5. 发明申请

US20080265962A1 SCANNABLE FLIP-FLOP WITH NON-VOLATILE STORAGE ELEMENT AND METHOD 有权
标题翻译：具有非易失性存储元件和方法的扫描片
公开(公告)号：US20080265962A1
公开(公告)日：2008-10-30
申请号：US11741920
申请日：2007-04-30
申请人： Jeffrey W. Waldrip , Alexander B. Hoefler
发明人： Jeffrey W. Waldrip , Alexander B. Hoefler
IPC分类号： H03K3/289
CPC分类号： G01R31/318541
摘要： A circuit has a master latch having an input for receiving an input data signal, and an output. A slave latch has a first input coupled to the output of the master latch, and an output for providing an output data signal. A non-volatile storage element stores a predetermined value. The non-volatile storage element has an output coupled to the first input of the slave latch. The output data signal corresponds to one of either the input data signal or the predetermined value stored by the non-volatile storage element in response to a control signal.
摘要翻译：电路具有主锁存器，具有用于接收输入数据信号的输入端和输出端。从锁存器具有耦合到主锁存器的输出的第一输入端和用于提供输出数据信号的输出端。非易失性存储元件存储预定值。非易失性存储元件具有耦合到从锁存器的第一输入的输出。输出数据信号响应于控制信号对应于输入数据信号或由非易失性存储元件存储的预定值之一。

6. 发明授权

US07432547B2 Non-volatile memory device with improved data retention and method therefor 有权
标题翻译：具有改进的数据保留的非易失性存储器件及其方法
公开(公告)号：US07432547B2
公开(公告)日：2008-10-07
申请号：US10779004
申请日：2004-02-13
申请人： Gowrishankar L. Chindalore , Frank K. Baker, Jr. , Paul A. Ingersoll , Alexander B. Hoefler
发明人： Gowrishankar L. Chindalore , Frank K. Baker, Jr. , Paul A. Ingersoll , Alexander B. Hoefler
IPC分类号： H01L21/8238
CPC分类号： H01L21/28202 , H01L29/42324 , H01L29/511 , H01L29/518 , H01L29/792
摘要： A semiconductor device (30) comprises an underlying insulating layer (34), an overlying insulating layer (42) and a charge storage layer (36) between the insulating layers (34, 42). The charge storage layer (36) and the overlying insulating layer (42) form an interface, where at least a majority of charge in the charge storage layer (36) is stored. This can be accomplished by forming a charge storage layer (36) with different materials such as silicon and silicon germanium layers or n-type and p-type material layers, in one embodiment. In another embodiment, the charge storage layer (36) comprises a dopant that is graded. By storing at least a majority of the charge at the interface between the charge storage layer (36) and the overlying insulating layer (42), the leakage of charge through the underlying insulating layer is decreased allowing for a thinner underlying insulating layer (34) to be used.
摘要翻译：半导体器件（30）包括下层绝缘层（34），上覆绝缘层（42）和在绝缘层（34,42）之间的电荷存储层（36）。电荷存储层（36）和上覆绝缘层（42）形成存储电荷存储层（36）中至少大部分电荷的界面。这可以通过在一个实施例中通过形成具有不同材料的电荷存储层（36）来实现，例如硅和硅锗层或n型和p型材料层。在另一个实施例中，电荷存储层（36）包括分级的掺杂剂。通过在电荷存储层（36）和上覆绝缘层（42）之间的界面处存储至少大部分电荷，通过下面的绝缘层的电荷泄漏减小，允许更薄的下层绝缘层（34）要使用的。

7. 发明授权

US07312129B2 Method for producing two gates controlling the same channel 有权
标题翻译：用于产生控制相同通道的两个门的方法
公开(公告)号：US07312129B2
公开(公告)日：2007-12-25
申请号：US11339101
申请日：2006-01-25
申请人： Sinan Goktepeli , Alexander B. Hoefler , Marius K. Orlowski
发明人： Sinan Goktepeli , Alexander B. Hoefler , Marius K. Orlowski
IPC分类号： H01L21/336
CPC分类号： H01L21/28132 , H01L21/823437 , H01L21/823468 , H01L27/0705 , H01L29/66484 , H01L29/7831
摘要： A semiconductor process and apparatus use a predetermined sequence of patterning and etching steps to etch a gate stack (62) formed over a substrate (11) and a first spacer structure (42), thereby forming etched gate structures (72, 74) that are physically separated from one another but that control a substrate channel (71) subsequently defined in the substrate (11) by source/drain regions (82, 102, 84, 104) that are implanted around the etched gate structures (72, 74). Depending on how the first spacer structure (42) is positioned and configured, the channel (71) may be controlled to provide either a logical AND gate (100) or logical OR gate (200) functionality.
摘要翻译：半导体工艺和装置使用预定的图案化和蚀刻步骤序列来蚀刻在衬底（11）和第一间隔结构（42）上形成的栅极堆叠（62），从而形成蚀刻的栅极结构（72,74），其是在物理上彼此分离，但是通过植入在蚀刻的栅极结构（72,74）周围的源极/漏极区域（82,102,84,104）来控制随后在衬底（11）中限定的衬底沟道（71）。取决于第一间隔结构（42）如何定位和配置，通道（71）可被控制以提供逻辑与门（100）或逻辑或门（200）功能。

8. 发明授权

US07285832B2 Multiport single transistor bit cell 有权
标题翻译：多端口单晶体管位元
公开(公告)号：US07285832B2
公开(公告)日：2007-10-23
申请号：US11192956
申请日：2005-07-29
申请人： Alexander B. Hoefler , James D. Burnett
发明人： Alexander B. Hoefler , James D. Burnett
IPC分类号： H01L29/94
CPC分类号： G11C8/16 , H01L27/105 , H01L27/1052 , Y10S257/903
摘要： A multiport memory cell (200, 300, 600) includes a first word line (WL1) coupled to a gate electrode of a first transistor (201, 301, 601). A second word line (WL2) is coupled to a gate electrode of a second transistor (202, 302, 602). Importantly, the memory cell (200, 300, 600) includes a conductive path (215, 315) between an electrically floating body (426) of the first transistor (201) and an electrically floating body (426) of the second transistor (202). The first word line (WL1) may overlie a first portion of a common body (426) and the second word line (WL2) may overlie a second portion of the common body (426). The common body (426) may be positioned vertically between a buried oxide layer (427) and a gate dielectric layer (430) and laterally between first and second source/drain regions (401, 407) formed in a semiconductor layer (425). The cell (200, 300, 600) may include a third transistor (603) including a third word line (613) where the shared transistor body (610) is shared with the third transistor (603) and wherein the conductive path is connected to the third transistor (603).
摘要翻译：多端口存储单元（200,300,600）包括耦合到第一晶体管（201,301,601）的栅电极的第一字线（WL 1）。第二字线（WL 2）耦合到第二晶体管（202,302,602）的栅电极。重要的是，存储单元（200,300,600）包括在第一晶体管（201）的电浮动体（426）和第二晶体管（202）的电浮动体（426）之间的导电路径（215,315））。第一字线（WL1）可以覆盖共同体（426）的第一部分，并且第二字线（WL 2）可以覆盖在共同体（426）的第二部分上。公共体（426）可以垂直地定位在掩埋氧化物层（427）和栅极电介质层（430）之间，并且横向地位于形成在半导体层（425）中的第一和第二源极/漏极区域（401,407）之间。单元（200,300,600）可以包括第三晶体管（603），其包括共享晶体管本体（610）与第三晶体管（603）共享的第三字线（613），并且其中导电路径连接到第三晶体管（603）。

9. 发明授权

US06939767B2 Multi-bit non-volatile integrated circuit memory and method therefor 失效
标题翻译：多位非易失性集成电路存储器及其方法
公开(公告)号：US06939767B2
公开(公告)日：2005-09-06
申请号：US10716956
申请日：2003-11-19
申请人： Alexander B. Hoefler , Ko-Min Chang
发明人： Alexander B. Hoefler , Ko-Min Chang
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , B82Y10/00 , H01L27/115 , H01L29/42332 , H01L29/7887
摘要： A non-volatile memory (10) includes at least two buried bit lines (45, 47) formed within a semiconductor substrate (12), a charge storage layer (18) overlying the semiconductor substrate (12); a control gate (26) overlying the charge storage layer (18); an insulating liner (30) overlying the control gate; and first and second conductive sidewall spacer control gates (32, 34). Multiple programmable charge storage regions (42) and (41, 44) are created within the charge storage layer (18) beneath respective ones of the control gate (26) and the first and second sidewall spacer control gates (32, 34). Also, the non-volatile memory (10) is a virtual ground NOR type multi-bit flash EEPROM (electrically erasable programmable read only memory). By using conductive sidewall spacers as the control gates, a very dense multi-bit non-volatile memory can be manufactured.
摘要翻译：非易失性存储器（10）包括形成在半导体衬底（12）内的至少两个掩埋位线（45,47），覆盖半导体衬底（12）的电荷存储层（18）; 覆盖电荷存储层（18）的控制栅极（26）; 覆盖所述控制门的绝缘衬垫（30）; 以及第一和第二导电侧壁间隔物控制门（32,34）。在电荷存储层（18）内，在控制栅极（26）和第一和第二侧壁间隔物控制栅极（32,34）的相应一个之下产生多个可编程电荷存储区域（42）和（41,44）。此外，非易失性存储器（10）是虚拟NOR型多位闪存EEPROM（电可擦除可编程只读存储器）。通过使用导电侧壁间隔件作为控制栅极，可以制造非常密集的多位非易失性存储器。

10. 发明申请

US20120194222A1 MEMORY HAVING A LATCHING SENSE AMPLIFIER RESISTANT TO NEGATIVE BIAS TEMPERATURE INSTABILITY AND METHOD THEREFOR 有权
标题翻译：具有耐受偏差温度不稳定性的锁存感测放大器的存储器及其方法
公开(公告)号：US20120194222A1
公开(公告)日：2012-08-02
申请号：US13016353
申请日：2011-01-28
申请人： Alexander B. Hoefler , James D. Burnett , Scott I. Remington
发明人： Alexander B. Hoefler , James D. Burnett , Scott I. Remington
IPC分类号： H03F3/16 , H03K3/011
CPC分类号： H03K3/356182 , G11C7/04 , G11C7/065 , H03K3/011
摘要： An integrated circuit includes a memory cell and a sense amplifier coupled to the memory cell via a first bit line and a second bit line. The sense amplifier includes first and second inverters cross-coupled to provide a latch. The first inverter is responsive to a first data signal provided by the memory cell over the first bit line. The second inverter is responsive to a second data signal as provided by the memory cell over the second bit line. A first negative bias temperature instability (NBTI) compensation transistor includes a source electrode coupled to receive a reference voltage, a drain electrode coupled to a source electrode of the first inverter, and a gate electrode coupled to first logic responsive to the first data signal. A second NBTI compensation transistor includes a source electrode coupled to receive the reference voltage, a drain electrode coupled to a source electrode of the second inverter, and a gate electrode coupled to second logic responsive to the second data signal, wherein the second data signal is a logical complement of the first data signal.
摘要翻译：集成电路包括经由第一位线和第二位线耦合到存储器单元的存储单元和读出放大器。读出放大器包括交叉耦合以提供锁存器的第一和第二反相器。第一反相器响应于由第一位线上的存储器单元提供的第一数据信号。第二反相器响应于由第二位线由存储器单元提供的第二数据信号。第一负偏压温度不稳定性（NBTI）补偿晶体管包括耦合以接收参考电压的源电极，耦合到第一反相器的源电极的漏极和响应于第一数据信号耦合到第一逻辑的栅电极。第二NBTI补偿晶体管包括耦合以接收参考电压的源电极，耦合到第二反相器的源电极的漏电极和响应于第二数据信号耦合到第二逻辑的栅电极，其中第二数据信号是第一数据信号的逻辑补码。

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