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1. 发明授权

US08809179B2 Method for reducing topography of non-volatile memory and resulting memory cells 有权
标题翻译：减少非易失性存储器和结果存储单元的形貌的方法
公开(公告)号：US08809179B2
公开(公告)日：2014-08-19
申请号：US11716164
申请日：2007-03-09
申请人： Shih Wei Wang , Derek Lin , Chen-Ming Huang , Chang-Jen Hsieh , Chi-Hsin Lo , Chung-Yi Yu , Feng-Jia Shiu , Yeur-Luen Tu , Yi-Shin Chu , Jen-Sheng Yang
发明人： Shih Wei Wang , Derek Lin , Chen-Ming Huang , Chang-Jen Hsieh , Chi-Hsin Lo , Chung-Yi Yu , Feng-Jia Shiu , Yeur-Luen Tu , Yi-Shin Chu , Jen-Sheng Yang
IPC分类号： H01L21/44 , H01L27/115 , H01L27/105
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11521 , H01L27/11526 , H01L27/11573
摘要： A method for forming a semiconductor structure includes providing a substrate; forming a gate stack of a flash memory cell, wherein a top portion of the gate stack comprises a capping layer; forming a gate having at least a portion over the capping layer; and reducing a thickness of the portion of the gate over the capping layer. The topography height difference between the flash memory cell and MOS devices on the same chip is reduced.
摘要翻译：一种形成半导体结构的方法包括：提供衬底; 形成闪存单元的栅极堆叠，其中所述栅极堆叠的顶部部分包括覆盖层; 形成具有覆盖层上方的至少一部分的栅极; 并且在所述封盖层上减小所述栅极的所述部分的厚度。闪存单元和同一芯片上的MOS器件之间的地形高差减小。

2. 发明授权

US08796105B2 Method and apparatus for preparing polysilazane on a semiconductor wafer 有权
标题翻译：在半导体晶片上制备聚硅氮烷的方法和装置
公开(公告)号：US08796105B2
公开(公告)日：2014-08-05
申请号：US13558284
申请日：2012-07-25
申请人： You-Hua Chou , Chih-Tsung Lee , Min-Hao Hong , Ming-Huei Lien , Chih-Jen Wu , Chen-Ming Huang
发明人： You-Hua Chou , Chih-Tsung Lee , Min-Hao Hong , Ming-Huei Lien , Chih-Jen Wu , Chen-Ming Huang
IPC分类号： H01L21/76
CPC分类号： H01L21/02164 , H01L21/02222 , H01L21/02282 , H01L21/02323 , H01L21/02337 , H01L21/76227
摘要： A method for depositing a polysilazane on a semiconductor wafer is provided. The method includes steps of disposing a silazane onto the semiconductor wafer, and heating the silazane to form the polysilazane on the semiconductor wafer. An apparatus for preparing a polysilazane on a semiconductor wafer is also provided.
摘要翻译：提供了一种在半导体晶片上沉积聚硅氮烷的方法。该方法包括将硅氮烷置于半导体晶片上，并加热硅氮烷以在半导体晶片上形成聚硅氮烷的步骤。还提供了一种在半导体晶片上制备聚硅氮烷的设备。

3. 发明申请

US20140030866A1 METHOD AND APPARATUS FOR PREPARING POLYSILAZANE ON A SEMICONDUCTOR WAFER 有权
标题翻译：在半导体波长处制备聚硅氧烷的方法和装置
公开(公告)号：US20140030866A1
公开(公告)日：2014-01-30
申请号：US13558284
申请日：2012-07-25
申请人： You-Hua Chou , Chih-Tsung Lee , Min-Hao Hong , Ming-Huei Lien , Chih-Jen Wu , Chen-Ming Huang
发明人： You-Hua Chou , Chih-Tsung Lee , Min-Hao Hong , Ming-Huei Lien , Chih-Jen Wu , Chen-Ming Huang
IPC分类号： H01L21/762 , H01L21/314
CPC分类号： H01L21/02164 , H01L21/02222 , H01L21/02282 , H01L21/02323 , H01L21/02337 , H01L21/76227
摘要： A method for depositing a polysilazane on a semiconductor wafer is provided. The method includes steps of disposing a silazane onto the semiconductor wafer, and heating the silazane to form the polysilazane on the semiconductor wafer. An apparatus for preparing a polysilazane on a semiconductor wafer is also provided.
摘要翻译：提供了一种在半导体晶片上沉积聚硅氮烷的方法。该方法包括将硅氮烷置于半导体晶片上，并加热硅氮烷以在半导体晶片上形成聚硅氮烷的步骤。还提供了一种在半导体晶片上制备聚硅氮烷的设备。

4. 发明授权

US07176083B2 High write and erase efficiency embedded flash cell 有权
公开(公告)号：US07176083B2
公开(公告)日：2007-02-13
申请号：US10870774
申请日：2004-06-17
申请人： Der-Shin Shyu , Hung-Cheng Sung , Chen-Ming Huang
发明人： Der-Shin Shyu , Hung-Cheng Sung , Chen-Ming Huang
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/7885
摘要： An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.

5. 发明申请

US20050282337A1 High write and erase efficiency embedded flash cell 有权
标题翻译：高写入和擦除效率嵌入式闪存单元
公开(公告)号：US20050282337A1
公开(公告)日：2005-12-22
申请号：US10870774
申请日：2004-06-17
申请人： Der-Shin Shyu , Hung-Cheng Sung , Chen-Ming Huang
发明人： Der-Shin Shyu , Hung-Cheng Sung , Chen-Ming Huang
IPC分类号： H01L21/336 , H01L21/4763 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , H01L29/7885
摘要： An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.
摘要翻译：一种嵌入式闪存单元结构，其包括结构，第一浮动栅极，其具有在所述结构上方的暴露侧壁，第二浮动栅极，具有在所述结构上并与所述第一浮动栅极间隔开的暴露的侧壁; 相应的第一浮动栅极和第二浮动栅极，至少在第一和第二浮动栅极的相应暴露的侧壁上方的第二对间隔物，在第二对间隔物之间的结构中的源极区域，源极植入物并且设置在第一对间隔件外侧的第一和第二控制门，并且暴露在结构的暴露的外侧部分中的结构的外侧部分和相应的漏极区域。还提供了一种形成嵌入式闪存单元结构的方法。

6. 发明授权

US06855648B2 Method of reducing stress migration in integrated circuits 有权
标题翻译：减少集成电路应力迁移的方法
公开(公告)号：US06855648B2
公开(公告)日：2005-02-15
申请号：US10601163
申请日：2003-06-20
申请人： Chen-Ming Huang , Sen-Shan Yang
发明人： Chen-Ming Huang , Sen-Shan Yang
IPC分类号： H01L21/768 , H01L23/532 , H01L21/324
CPC分类号： H01L21/76877 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： A method for reducing stress migration in the copper interconnect line is set forth. In accordance with the method, two anneal steps take place: The first step is at low temperature and of relatively short duration (e.g., about 25-300° C., and about 10 seconds-10 hours). After the first anneal, the wafer is cooled to room temperature. The second step is performed after the cooling step; a higher anneal temperature and longer time duration is needed to enhance performance.
摘要翻译：阐述了一种减少铜互连线中的应力迁移的方法。根据该方法，发生两个退火步骤：第一步是在低温和相对短的持续时间（例如约25-300℃，约10秒-10小时）。第一次退火后，将晶片冷却至室温。第二步在冷却步骤之后进行; 需要更高的退火温度和更长的持续时间来增强性能。

7. 发明授权

US06819593B2 Architecture to suppress bit-line leakage 有权
标题翻译：抑制位线泄漏的体系结构
公开(公告)号：US06819593B2
公开(公告)日：2004-11-16
申请号：US10318458
申请日：2002-12-13
申请人： Der-Shin Shyu , Hung-Cheng Sung , Li-Wen Chang , Han-Ping Chen , Chen-Ming Huang , Ya-Chen Kao
发明人： Der-Shin Shyu , Hung-Cheng Sung , Li-Wen Chang , Han-Ping Chen , Chen-Ming Huang , Ya-Chen Kao
IPC分类号： G11C1600
CPC分类号： G11C16/3418 , G11C16/0425
摘要： A method to suppress bit-line leakage in a nonvolatile memory cell is achieved. The method comprises providing an array of nonvolatile memory cells comprising source and bulk terminals. The array comprises a plurality of subarrays. The sources of all the nonvolatile cells in each subarray are coupled together to form a common subarray source. Bulks of all the nonvolatile cells in the array are coupled together to form a common array bulk. A first, non-zero voltage is forced between the common subarray source and the common array bulk for a first subarray that is selected for an access operation. A second, non-zero voltage is forced between the common subarray source and the common array bulk for a second subarray that is not selected for an access operation. The second, non-zero voltage inhibits bit line leakage in the second subarray.
摘要翻译：实现了在非易失性存储单元中抑制位线泄漏的方法。该方法包括提供包括源极和体积端子的非易失性存储器单元的阵列。阵列包括多个子阵列。每个子阵列中的所有非易失性单元的源耦合在一起以形成公共的子阵列源。阵列中所有非易失性单元的容量被耦合在一起以形成共同的阵列体。对于为访问操作选择的第一子阵列，第一个非零电压被强制在公共子阵列源和公共阵列块之间。第二个非零电压被强制在公共子阵列源和公共阵列块之间，用于未被选择用于访问操作的第二子阵列。第二个非零电压禁止第二个子阵列中的位线泄漏。

8. 发明授权

US08704224B2 Semiconductor test structures 有权
标题翻译：半导体测试结构
公开(公告)号：US08704224B2
公开(公告)日：2014-04-22
申请号：US13241634
申请日：2011-09-23
申请人： An-Chun Tu , Chen-Ming Huang , Chih-Jen Wu , Chin-Hsiang Lin
发明人： An-Chun Tu , Chen-Ming Huang , Chih-Jen Wu , Chin-Hsiang Lin
IPC分类号： H01L23/10
CPC分类号： G01R31/2644 , G01R31/2884 , H01L22/14 , H01L22/32 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A resistive test structure that includes a semiconductor substrate with an active region, a gate stack formed over the active region, a first electrical contact in communication with the active region on opposing sides of the gate stack, the first electrical contact providing an electrical short across a first dimension of the gate stack, and a second electrical contact in communication with the active region on the opposing sides of the gate stack, the second electrical contact providing an electrical short across the first dimension of the gate stack, the first and second electrical contacts spaced along a second dimension of the gate stack perpendicular to the first dimension.
摘要翻译：一种电阻测试结构，其包括具有有源区的半导体衬底，形成在有源区上的栅极叠层，与栅极堆叠的相对侧上的有源区连通的第一电触点，第一电触点提供跨越栅极堆叠的第一尺寸和与栅极堆叠的相对侧上的有源区域连通的第二电触点，第二电触点跨过栅极堆叠的第一维度提供电短路，第一和第二电极接触件沿垂直于第一尺寸的栅极堆叠的第二尺寸间隔开。

9. 发明授权

US08674469B2 Isolation structure for backside illuminated image sensor 有权
标题翻译：背面照明图像传感器的隔离结构
公开(公告)号：US08674469B2
公开(公告)日：2014-03-18
申请号：US12766130
申请日：2010-04-23
申请人： Kuan-Chieh Huang , Chih-Jen Wu , Chen-Ming Huang , Dun-Nian Yaung , An-Chun Tu
发明人： Kuan-Chieh Huang , Chih-Jen Wu , Chen-Ming Huang , Dun-Nian Yaung , An-Chun Tu
IPC分类号： H01L31/00
CPC分类号： H01L21/76237 , H01L21/76224 , H01L27/14621 , H01L27/14625 , H01L27/14627 , H01L27/1463 , H01L27/14636 , H01L27/1464 , H01L27/14685 , H01L27/14687 , H01L27/14689 , H01L31/18
摘要： A backside illuminated image sensor includes an isolation structure passing through a substrate, a sensor element formed overlying the front surface of the substrate, and a color filter formed overlying the back surface of the substrate.
摘要翻译：背面照明图像传感器包括通过基板的隔离结构，覆盖在基板的前表面上的传感器元件和形成在基板的后表面上的滤色器。

10. 发明授权

US08614131B2 Self-aligned static random access memory (SRAM) on metal gate 有权
标题翻译：金属门上的自对准静态随机存取存储器（SRAM）
公开(公告)号：US08614131B2
公开(公告)日：2013-12-24
申请号：US12364701
申请日：2009-02-03
申请人： An-Chun Tu , Chen-Ming Huang
发明人： An-Chun Tu , Chen-Ming Huang
IPC分类号： H01L21/336
CPC分类号： H01L21/823475 , H01L21/76895 , H01L21/76897 , H01L21/823437 , H01L21/823456 , H01L27/11 , H01L27/1104 , H01L29/6653 , H01L29/66545
摘要： A method for fabricating an integrated circuit providing an enlarged contact process window while reducing device size is disclosed. The method comprises providing a substrate including a first region and a second region, the first and second regions having one or more gate structures including a dummy gate layer; removing the dummy gate layer from at least one of the one or more gate structures in the first and second regions to form one or more trenches in the first and second regions; filling the one or more trenches in the first and second regions with a conductive layer; selectively etching back the conductive layer of the one or more gate structures in the second region of the substrate; forming a protective layer over the etched back conductive layer of the one or more gate structures in the second region; and forming one or more contact openings in the first and second regions.
摘要翻译：公开了一种制造集成电路的方法，该集成电路在减小装置尺寸的同时提供放大的接触处理窗口。该方法包括提供包括第一区域和第二区域的衬底，所述第一和第二区域具有包括虚拟栅极层的一个或多个栅极结构; 从第一和第二区域中的一个或多个栅极结构中的至少一个去除伪栅极层，以在第一和第二区域中形成一个或多个沟槽; 用导电层填充第一和第二区域中的一个或多个沟槽; 选择性地蚀刻衬底的第二区域中的一个或多个栅极结构的导电层; 在所述第二区域中的所述一个或多个栅极结构的蚀刻背面导电层上形成保护层; 以及在所述第一和第二区域中形成一个或多个接触开口。

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