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1. 发明授权

US06819620B2 Power supply device with reduced power consumption 有权
标题翻译：电源设备功耗降低
公开(公告)号：US06819620B2
公开(公告)日：2004-11-16
申请号：US10248495
申请日：2003-01-23
申请人： Yen-Tai Lin , Ching-Yuan Lin , Chien-Hung Ho
发明人： Yen-Tai Lin , Ching-Yuan Lin , Chien-Hung Ho
IPC分类号： G11C1134
CPC分类号： G11C16/30
摘要： A power supply used for providing a flash memory with an operating voltage has a plurality of memory blocks and a plurality of decoders corresponding to the memory blocks. Each memory block has a plurality of memory cells for storing binary data. Each decoder is used for selecting memory cells in the corresponding memory block. The power supply has at least three power sources for generating different voltages, and controls the power sources for making a voltage difference between a high voltage level and a low voltage level of the unselected decoder less than a voltage difference between a high voltage level and a low voltage level of the selected decoder.
摘要翻译：用于提供具有工作电压的闪速存储器的电源具有多个存储块和对应于存储块的多个解码器。每个存储块具有用于存储二进制数据的多个存储单元。每个解码器用于选择相应存储块中的存储单元。电源具有用于产生不同电压的至少三个电源，并且控制电源以使未选择的解码器的高电压电平和低电压电平之间的电压差小于高电压电平和高电压电平之间的电压差所选解码器的低电压电平。

2. 发明授权

US06580658B1 Method using a word line driver for driving a word line 失效
标题翻译：使用字线驱动程序来驱动字线的方法
公开(公告)号：US06580658B1
公开(公告)日：2003-06-17
申请号：US10065661
申请日：2002-11-07
申请人： Yu-Ming Hsu , Yen-Tai Lin , Chien-Hung Ho
发明人： Yu-Ming Hsu , Yen-Tai Lin , Chien-Hung Ho
IPC分类号： G11C800
CPC分类号： G11C8/08 , G11C16/08
摘要： A word line driver includes an address decoder having a first circuit and a second circuit for selecting the word line, and a control end disposed between the first circuit and the second circuit. In addition, the word line driver has a level shift circuit for shifting a voltage level of the word line, and the level shift circuit has an input end connected to the second circuit of the address decoder. A method of driving a word line includes shifting a voltage level of the control end while turning on the second circuit so as to shift a voltage level of the input end of the level shift circuit, and shifting a voltage level of at least one of the first and second power supplies and using the second circuit to isolate the voltage level of the control end from the voltage level of the word line.
摘要翻译：字线驱动器包括具有第一电路的地址解码器和用于选择字线的第二电路，以及设置在第一电路和第二电路之间的控制端。此外，字线驱动器具有用于移位字线的电压电平的电平移位电路，并且电平移位电路具有连接到地址解码器的第二电路的输入端。一种驱动字线的方法包括：在接通第二电路的同时移动控制端的电压电平，以便移位电平移位电路的输入端的电压电平，并移位至少一个第一和第二电源，并使用第二电路将控制端的电压电平与字线的电压电平隔离开。

3. 发明授权

US06580645B1 Page buffer of a flash memory 失效
标题翻译： Flash存储器的页面缓冲区
公开(公告)号：US06580645B1
公开(公告)日：2003-06-17
申请号：US10065660
申请日：2002-11-07
申请人： Yen-Tai Lin , Chien-Hung Ho
发明人： Yen-Tai Lin , Chien-Hung Ho
IPC分类号： G11C1600
CPC分类号： G11C16/10 , G11C2216/14
摘要： A page buffer for a flash memory has a power supply, a latch circuit, and a plurality of switches. Initially the switches are controlled for resetting a first terminal and a second terminal of the latch circuit to a respective predetermined voltage. If a memory cell is not to be programmed, the voltage levels of the first terminal and the second terminal remain unchanged when the power supply outputs a programming voltage. If the memory cell is to be programmed, the voltage levels of the first terminal and the second terminal are changed when the power supply outputs the programming voltage. Each of the first terminal and the second terminal will regain the predetermined voltage after the memory cell is completely programmed to store a predetermined binary digit.
摘要翻译：闪存的页缓冲器具有电源，锁存电路和多个开关。最初，开关被控制用于将锁存电路的第一端子和第二端子复位到相应的预定电压。如果不编程存储单元，则当电源输出编程电压时，第一端子和第二端子的电压电平保持不变。如果要对存储器单元进行编程，则当电源输出编程电压时，第一端子和第二端子的电压电平发生变化。在存储器单元被完全编程以存储预定二进制数位之后，第一端子和第二端子中的每一个将重新获得预定电压。

4. 发明申请

US20130064027A1 Memory and Method of Adjusting Operating Voltage thereof 审中-公开
标题翻译：记忆和调整其工作电压的方法
公开(公告)号：US20130064027A1
公开(公告)日：2013-03-14
申请号：US13231980
申请日：2011-09-14
申请人： Meng-Yi Wu , Wein-Town Sun , Yen-Tai Lin , Cheng-Jye Liu , Chiun-Chi Shen
发明人： Meng-Yi Wu , Wein-Town Sun , Yen-Tai Lin , Cheng-Jye Liu , Chiun-Chi Shen
IPC分类号： G11C29/00
CPC分类号： G11C29/021 , G11C11/40 , G11C29/028 , G11C29/50016 , G11C2029/5002
摘要： By adjusting an operating voltage of a memory cell in a memory according to a measured capacitance result indicating capacitance of an under-test capacitor of the memory cell, an appropriate operating voltage for the memory cell can always be determined according to the measured capacitance result. The measured capacitance result indicates whether the capacitance of the under-test capacitor indicating the characteristic of the gate dielectric of the memory cell is higher or lower than a reference capacitor, and is generated by amplifying a difference between two voltages indicating capacitance of the reference capacitor and the capacitance of the under-test capacitor.
摘要翻译：通过根据指示存储单元的未测试电容器的电容的测量电容结果来调节存储器中的存储单元的工作电压，可以总是根据所测量的电容结果确定存储单元的适当工作电压。测量的电容结果表示指示存储单元的栅极电介质的特性的未测试电容器的电容是否高于或低于参考电容器，并且通过放大表示参考电容器的电容的两个电压之间的差来产生和被测电容器的电容。

5. 发明申请

US20070159883A1 Method and Related Apparatus Capable of Improving Endurance of Memory 审中-公开
标题翻译：能够提高记忆力的方法和相关装置
公开(公告)号：US20070159883A1
公开(公告)日：2007-07-12
申请号：US11531278
申请日：2006-09-13
申请人： Ching-Yuan Lin , Yen-Tai Lin
发明人： Ching-Yuan Lin , Yen-Tai Lin
IPC分类号： G11C11/34 , G11C16/06 , G11C16/04
CPC分类号： G11C16/349 , G11C16/102 , G11C16/3495
摘要： A method capable of improving endurance of memory includes detecting whether a record cell is the last non-programmed record cell of a set of record cells that includes the record cell. The method includes erasing the corresponding set of multi-time programmable memory blocks and erasing the set of record cells, if the record cell is the last non-programmed record cell of the set of record cells that includes the record cell. The method further includes programming the record cell corresponding to a first non-programmed record cell in the set of record cells if the non-programmed record cell is not the last non-programmed record cell of the set of record cells.
摘要翻译：能够提高存储器耐久性的方法包括检测记录单元是否是包括记录单元的一组记录单元的最后一个非编程记录单元。如果记录单元是包括记录单元的记录单元组的最后一个未编程的记录单元，则该方法包括擦除相应的多次可编程存储器块组并擦除记录单元组。该方法还包括如果非编程记录单元不是该组记录单元的最后一个非编程记录单元，则编程对应于记录单元组中的第一非编程记录单元的记录单元。

6. 发明授权

US08373485B2 Voltage level shifting apparatus 有权
标题翻译：电压电平转换装置
公开(公告)号：US08373485B2
公开(公告)日：2013-02-12
申请号：US13090283
申请日：2011-04-20
申请人： Chen-Hao Po , Yen-Tai Lin , Way-Chen Wu , Ching-Shan Chien
发明人： Chen-Hao Po , Yen-Tai Lin , Way-Chen Wu , Ching-Shan Chien
IPC分类号： H03L5/00
CPC分类号： H03K3/356182
摘要： A voltage level shifting apparatus is disclosed. The voltage level shifting apparatus has a cross-coupled transistor pair, a plurality of transistor pairs, a first diode string, a second diode string and an input transistor pair. One of the transistor pairs is coupled to the cross-coupled transistor pair, and the transistor pairs are controlled by a plurality of reference voltages. The first and the second diode strings are coupled between two of the transistor pairs. Each of the first and the second diode strings has at least one diode. The input transistor pair receives a first and a second input voltage, and the first and second input voltages are complementary signals. The cross-coupled transistor pair generates and outputs a first output voltage and a second output voltage by shifting the voltage level of the first and the second input voltage.
摘要翻译：公开了一种电压电平转换装置。电压电平移位装置具有交叉耦合晶体管对，多个晶体管对，第一二极管串，第二二极管串和输入晶体管对。晶体管对中的一个耦合到交叉耦合晶体管对，并且晶体管对由多个参考电压控制。第一和第二二极管串耦合在两个晶体管对之间。第一和第二二极管串中的每一个具有至少一个二极管。输入晶体管对接收第一和第二输入电压，第一和第二输入电压是互补信号。交叉耦合晶体管对通过移位第一和第二输入电压的电压电平来产生并输出第一输出电压和第二输出电压。

7. 发明申请

US20080165587A1 OPERATING METHOD OF P-CHANNEL NON-VOLATILE MEMORY 失效
标题翻译： P-CHANNEL非易失性存储器的操作方法
公开(公告)号：US20080165587A1
公开(公告)日：2008-07-10
申请号：US12046477
申请日：2008-03-12
申请人： Yen-Tai Lin
发明人： Yen-Tai Lin
IPC分类号： G11C11/34
CPC分类号： H01L27/115
摘要： A P-channel non-volatile memory is described. The P-channel non-volatile memory includes a substrate, a first memory cell, and second memory cell. An N-well is disposed over the substrate, and the first cell and the second cell are disposed over the N-well. The first memory cell includes a first gate, a first charge storage structure, a first doped region and a second doped region. The first doped region and the second doped region are disposed in the substrate on the respective sides of the first gate. The second cell includes a second gate, a second charge storage structure, a third doped region, and the second doped region. The third doped region and the second doped region are disposed in the substrate on the respective sides of the second gate. The second cell and the first cell share the second doped region.
摘要翻译：描述P沟道非易失性存储器。 P沟道非易失性存储器包括衬底，第一存储单元和第二存储单元。在衬底上设置N阱，并且将第一电池和第二电池设置在N阱上。第一存储单元包括第一栅极，第一电荷存储结构，第一掺杂区和第二掺杂区。第一掺杂区域和第二掺杂区域设置在第一栅极的相应侧面上的衬底中。第二单元包括第二栅极，第二电荷存储结构，第三掺杂区和第二掺杂区。第三掺杂区域和第二掺杂区域设置在第二栅极的相应侧上的衬底中。第二单元和第一单元共享第二掺杂区。

8. 发明申请

US20080159008A1 OPERATING METHOD OF P-CHANNEL NON-VOLATILE MEMORY 审中-公开
公开(公告)号：US20080159008A1
公开(公告)日：2008-07-03
申请号：US12045030
申请日：2008-03-10
申请人： Yen-Tai Lin
发明人： Yen-Tai Lin
IPC分类号： G11C11/34
CPC分类号： H01L27/115
摘要： A P-channel non-volatile memory is described. The P-channel non-volatile memory includes a substrate, a first memory cell, and second memory cell. An N-well is disposed over the substrate, and the first cell and the second cell are disposed over the N-well. The first memory cell includes a first gate, a first charge storage structure, a first doped region and a second doped region. The first doped region and the second doped region are disposed in the substrate on the respective sides of the first gate. The second cell includes a second gate, a second charge storage structure, a third doped region, and the second doped region. The third doped region and the second doped region are disposed in the substrate on the respective sides of the second gate. The second cell and the first cell share the second doped region.

9. 发明申请

US20060262626A1 METHOD FOR ACCESSING MEMORY 有权
标题翻译：访问存储器的方法
公开(公告)号：US20060262626A1
公开(公告)日：2006-11-23
申请号：US11163431
申请日：2005-10-19
申请人： Ching-Yuan Lin , Hong-Yi Liao , Yen-Tai Lin , Shih-Yun Lin , Chun-Hung Lu
发明人： Ching-Yuan Lin , Hong-Yi Liao , Yen-Tai Lin , Shih-Yun Lin , Chun-Hung Lu
IPC分类号： G11C17/18
CPC分类号： G11C16/105 , G11C16/3495 , G11C17/146 , G11C17/18 , G11C2216/26
摘要： The present invention provides a method for accessing a memory. The memory contains M one-time programmable memory blocks, and each has a first memory sector and a second memory sector. The method includes: selecting a first target memory block and reading the first target memory block. The step of selecting a first target memory block is performed by comparing the second memory sectors of N one-time programmable memory blocks from M one-time programmable memory blocks by following a search rule to select the first target memory block.
摘要翻译：本发明提供一种访问存储器的方法。存储器包含M个一次性可编程存储器块，并且每个具有第一存储器扇区和第二存储器扇区。该方法包括：选择第一目标存储块并读取第一目标存储块。通过按照搜索规则比较来自M个一次可编程存储器块的N个一次可编程存储器块的第二存储器扇区来选择第一目标存储器块来选择第一目标存储器块的步骤来选择第一目标存储器块。

10. 发明授权

US6153463A Triple plate capacitor and method for manufacturing 有权
标题翻译：三板式电容器及其制造方法
公开(公告)号：US6153463A
公开(公告)日：2000-11-28
申请号：US350478
申请日：1999-07-09
申请人： Hon-Sco Wei , Yen-Tai Lin
发明人： Hon-Sco Wei , Yen-Tai Lin
IPC分类号： H01L21/02 , H01L29/94 , H01L21/8242
CPC分类号： H01L28/40 , H01L29/94
摘要： A novel capacitor design and construction method that uses a stacked structure which is sometimes otherwise used for a so-called floating gate transistor. A first electrical contact is electrically coupled with a conductive region formed in the substrate and with a control gate layer. A second electrical contact is electrically coupled with a floating gate layer, forming a plate between the substrate and control gate layers. The footprint of this capacitor is reduced by using both sides of the floating gate layer as capacitive plate. Parasitic capacitance is relatively reduced. One or more dielectric layers can be formed for both capacitors and for floating gate transistors on the substrate in the same process step or steps.
摘要翻译：一种新颖的电容器设计和施工方法，其使用有时另外用于所谓的浮栅晶体管的堆叠结构。第一电触头与形成在基板中的导电区域和控制栅极层电耦合。第二电接触件与浮栅层电耦合，在衬底和控制栅极层之间形成一个板。通过使用浮动栅极层的两侧作为电容板来减小该电容器的占位面积。寄生电容相对减小。可以在相同的工艺步骤中为两个电容器和衬底上的浮栅晶体管形成一个或多个电介质层。

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