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1. 发明授权

US06903975B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US06903975B2
公开(公告)日：2005-06-07
申请号：US10786025
申请日：2004-02-26
申请人： Shunichi Saeki , Hideakii Kurata , Naoki Kobayashi
发明人： Shunichi Saeki , Hideakii Kurata , Naoki Kobayashi
IPC分类号： G11C16/02 , G11C11/56 , G11C16/28 , G11C16/34 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C16/00
CPC分类号： G11C16/3459 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/28 , G11C16/3454 , G11C2211/5621
摘要： A nonvolatile semiconductor memory device includes a memory cell, formed in a well in a substrate and having a source, a drain, a first gate and a second gate. A word line control circuit drives a word line connected to the second gate, a program data holding circuit holds program data, a programming voltage generator circuit applies a programming voltage onto a bit line connected to the drain, and a discrimination circuit verifies the program data. Programming is conducted by applying positive voltages to the second gate and drain, while injecting hot electrons generated in a channel portion in a vicinity of the drain when 0V is applied to the well and source to increase a threshold voltage. Verification is conducted by applying a verify voltage to the second gate, while applying a positive voltage to the drain and 0V to the well and source, thereby verifying whether the positive voltage applied is maintained or comes down to 0V, depending upon the threshold voltage, by means of the discrimination circuit.
摘要翻译：非易失性半导体存储器件包括形成在衬底中的阱中并具有源极，漏极，第一栅极和第二栅极的存储单元。字线控制电路驱动连接到第二门的字线，程序数据保持电路保存程序数据，编程电压发生器电路将编程电压施加到与漏极连接的位线上，鉴别电路验证程序数据。通过向第二栅极和漏极施加正电压，同时在向阱和源施加0V以增加阈值电压时注入在漏极附近的通道部分中产生的热电子来进行编程。通过向第二栅极施加验证电压，同时向漏极施加正电压，向阱和源施加0V，从而根据阈值电压验证施加的正电压是否维持或降至0V，通过鉴别电路。

2. 发明授权

US06414877B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US06414877B2
公开(公告)日：2002-07-02
申请号：US09769358
申请日：2001-01-26
申请人： Shunichi Saeki , Hideakii Kurata , Naoki Kobayashi
发明人： Shunichi Saeki , Hideakii Kurata , Naoki Kobayashi
IPC分类号： G11C1600
CPC分类号： G11C16/3459 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/28 , G11C16/3454 , G11C2211/5621
摘要： In a nonvolatile semiconductor memory device, in which programming operation of data is conducted by injecting hot electron generated between a source layer and a drain layer of a memory cell into a floating gate between the both layers on an upper potion of surface of a semiconductor, while verification of the data programmed is conducted by making discrimination on whether voltage applied to the drain is kept or not, depending upon a height of a threshold voltage of the memory cell.

3. 发明授权

US06724659B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US06724659B2
公开(公告)日：2004-04-20
申请号：US10338018
申请日：2003-01-08
申请人： Shunichi Saeki , Hideakii Kurata , Naoki Kobayashi
发明人： Shunichi Saeki , Hideakii Kurata , Naoki Kobayashi
IPC分类号： G11C1600
CPC分类号： G11C16/3459 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/28 , G11C16/3454 , G11C2211/5621
摘要： In a nonvolatile semiconductor memory device, in which programming operation of data is conducted by injecting hot electron generated between a source layer and a drain layer of a memory cell into a floating gate between the both layers on an upper potion of surface of a semiconductor, while verification of the data programmed is conducted by making discrimination on whether voltage applied to the drain is kept or not, depending upon a height of a threshold voltage of the memory cell.
摘要翻译：在非易失性半导体存储器件中，其中数据的编程操作是通过在半导体的上部表面上注入在存储单元的源极层和漏极层之间产生的热电子到两个层之间的浮动栅极来进行的，通过根据存储单元的阈值电压的高度判断是否保持施加到漏极的电压来进行对编程数据的验证。

4. 发明授权

US06525968B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US06525968B2
公开(公告)日：2003-02-25
申请号：US10173305
申请日：2002-06-18
申请人： Shunichi Saeki , Hideakii Kurata , Naoki Kobayashi
发明人： Shunichi Saeki , Hideakii Kurata , Naoki Kobayashi
IPC分类号： G11C1600
CPC分类号： G11C16/3459 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C16/28 , G11C16/3454 , G11C2211/5621
摘要： In a nonvolatile semiconductor memory device, in which programming operation of data is conducted by injecting hot electron generated between a source layer and a drain layer of a memory cell into a floating gate between the both layers on an upper potion of surface of a semiconductor, while verification of the data programmed is conducted by making discrimination on whether voltage applied to the drain is kept or not, depending upon a height of a threshold voltage of the memory cell.

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