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1. 发明授权

US06791883B2 Program and erase in a thin film storage non-volatile memory 有权
标题翻译：在薄膜存储非易失性存储器中编程和擦除
公开(公告)号：US06791883B2
公开(公告)日：2004-09-14
申请号：US10178658
申请日：2002-06-24
申请人： Craig T. Swift , Jane A. Yater , Alexander B. Hoefler , Ko-Min Chang , Erwin J. Prinz , Bruce L. Morton
发明人： Craig T. Swift , Jane A. Yater , Alexander B. Hoefler , Ko-Min Chang , Erwin J. Prinz , Bruce L. Morton
IPC分类号： G11C1600
CPC分类号： G11C16/0466
摘要： A non-volatile memory having a thin film dielectric storage element is programmed by hot carrier injection (HCI) and erased by tunneling. The typical structure for the memory cells for this type of memory is silicon, oxide, nitride, oxide, and silicon (SONOS). The hot carrier injection provides relatively fast programming for SONOS, while the tunneling provides for erase that avoids the difficulties with the hot hole erase (HHE) type erase that generally accompanies hot carrier injection for programming. HHE is significantly more damaging to dielectrics leading to reliability issues. HHE also has a relatively narrow area of erasure that may not perfectly match the pattern for the HCI programming leaving an incomplete erasure. The tunnel erase effectively covers the entire area so there is no concern about incomplete erase. Although tunnel erase is slower than HHE, erase time is generally less critical in a system operation than is programming time.
摘要翻译：具有薄膜电介质存储元件的非易失性存储器通过热载流子注入（HCI）编程并通过隧道擦除。这种存储器的存储单元的典型结构是硅，氧化物，氮化物，氧化物和硅（SONOS）。热载波注入为SONOS提供相对快速的编程，而隧道提供擦除，避免了通常伴随热载流子注入进行编程的热孔擦除（HHE）类型擦除的困难。 HHE对电介质的破坏性更大，导致可靠性问题。 HHE还具有相对较窄的擦除区域，可能不完全匹配HCI编程的模式，从而导致不完整的擦除。隧道擦除有效地覆盖整个区域，所以不用担心不完全擦除。虽然隧道擦除比HHE慢，但擦除时间在系统操作中通常不如编程时间那么重要。

2. 发明授权

US06887758B2 Non-volatile memory device and method for forming 有权
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US06887758B2
公开(公告)日：2005-05-03
申请号：US10267153
申请日：2002-10-09
申请人： Gowrishankar L. Chindalore , Paul A. Ingersoll , Craig T. Swift , Alexander B. Hoefler
发明人： Gowrishankar L. Chindalore , Paul A. Ingersoll , Craig T. Swift , Alexander B. Hoefler
IPC分类号： H01L21/336 , H01L29/792 , H01L29/788
CPC分类号： H01L29/66825 , H01L29/66833 , H01L29/792
摘要： A semiconductor device (10) has a highly doped layer (26) having a first conductivity type uniformly implanted into the semiconductor substrate (20). An oxide-nitride-oxide structure (36, 38, 40) is formed over the semiconductor substrate (20). A halo region (46) having the first conductivity type is implanted at an angle in only a drain side of the oxide-nitride-oxide structure and extends under the oxide-nitride-oxide structure a predetermined distance from an edge of the oxide-nitride-oxide structure. A source (52) and drain (54) having a second conductivity type are implanted into the substrate (20). The resulting non-volatile memory cell provides a low natural threshold voltage to minimize threshold voltage drift during a read cycle. In addition, the use of the halo region (46) on the drain side allows a higher programming speed, and the highly doped layer (26) allows the use of a short channel device.
摘要翻译：半导体器件（10）具有均匀地注入到半导体衬底（20）中的具有第一导电类型的高掺杂层（26）。氧化物 - 氧化物 - 氧化物结构（36,38,40）形成在半导体衬底（20）上。具有第一导电类型的卤素区域（46）以仅在氧化物 - 氧化物 - 氧化物结构的漏极侧的角度被注入，并且在氧化物 - 氮化物 - 氧化物结构之下延伸到氧化氮化物 - 氮化物的边缘的预定距离氧化物结构。具有第二导电类型的源极（52）和漏极（54）被注入衬底（20）中。所得的非易失性存储单元提供低的自然阈值电压，以在读周期期间最小化阈值电压漂移。此外，在漏极侧使用卤素区域（46）允许更高的编程速度，并且高掺杂层（26）允许使用短通道器件。

3. 发明授权

US06713812B1 Non-volatile memory device having an anti-punch through (APT) region 有权
标题翻译：具有抗冲穿（APT）区域的非易失性存储器件
公开(公告)号：US06713812B1
公开(公告)日：2004-03-30
申请号：US10267199
申请日：2002-10-09
申请人： Alexander B. Hoefler , Gowrishankar L. Chindalore , Paul A. Ingersoll , Craig T. Swift
发明人： Alexander B. Hoefler , Gowrishankar L. Chindalore , Paul A. Ingersoll , Craig T. Swift
IPC分类号： H01L29788
CPC分类号： H01L29/66825 , H01L27/11521 , H01L29/105 , H01L29/66833 , H01L29/792
摘要： A memory device (70) that uses a non-volatile storage element (38), such as nitride, has reduced read disturb, which is the problem of tending to increase the threshold voltage of a memory device (70) during a read. To reduce this effect, the memory device (70) uses a counterdoped channel (86) to lower the natural threshold voltage of the device (70). This counterdoping can even be of sufficient dosage to reverse the conductivity type of the channel (86) and causing a negative natural threshold voltage. This allows for a lower gate voltage during read to reduce the adverse effect of performing a read. An anti-punch through (ATP) region (74) below the channel (86) allows for the lightly doped or reversed conductivity type channel (86) to avoid short channel leakage. A halo implant (46) on the drain side (54, 53) assists in hot carrier injection (HCI) so that the HCI is effective even though the channel (86) is lightly doped or of reversed conductivity type.
摘要翻译：使用诸如氮化物的非易失性存储元件（38）的存储器件（70）具有减少的读取干扰，这是读取期间倾向于增加存储器件（70）的阈值电压的问题。为了减少这种影响，存储装置（70）使用反向通道（86）来降低装置（70）的自然阈值电压。这种反渗透甚至可以具有足够的剂量来反转通道（86）的导电类型并导致负的自然阈值电压。这在读取期间允许较低的栅极电压以减少执行读取的不利影响。在沟道（86）下方的抗穿透（ATP）区域（74）允许轻掺杂或反向导电型通道（86）避免短沟道泄漏。漏极侧（54,53）上的卤素注入（46）有助于热载流子注入（HCI），使得尽管通道（86）被轻掺杂或反向导电类型，HCI也是有效的。

4. 发明授权

US06939767B2 Multi-bit non-volatile integrated circuit memory and method therefor 失效
标题翻译：多位非易失性集成电路存储器及其方法
公开(公告)号：US06939767B2
公开(公告)日：2005-09-06
申请号：US10716956
申请日：2003-11-19
申请人： Alexander B. Hoefler , Ko-Min Chang
发明人： Alexander B. Hoefler , Ko-Min Chang
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , B82Y10/00 , H01L27/115 , H01L29/42332 , H01L29/7887
摘要： A non-volatile memory (10) includes at least two buried bit lines (45, 47) formed within a semiconductor substrate (12), a charge storage layer (18) overlying the semiconductor substrate (12); a control gate (26) overlying the charge storage layer (18); an insulating liner (30) overlying the control gate; and first and second conductive sidewall spacer control gates (32, 34). Multiple programmable charge storage regions (42) and (41, 44) are created within the charge storage layer (18) beneath respective ones of the control gate (26) and the first and second sidewall spacer control gates (32, 34). Also, the non-volatile memory (10) is a virtual ground NOR type multi-bit flash EEPROM (electrically erasable programmable read only memory). By using conductive sidewall spacers as the control gates, a very dense multi-bit non-volatile memory can be manufactured.
摘要翻译：非易失性存储器（10）包括形成在半导体衬底（12）内的至少两个掩埋位线（45,47），覆盖半导体衬底（12）的电荷存储层（18）; 覆盖电荷存储层（18）的控制栅极（26）; 覆盖所述控制门的绝缘衬垫（30）; 以及第一和第二导电侧壁间隔物控制门（32,34）。在电荷存储层（18）内，在控制栅极（26）和第一和第二侧壁间隔物控制栅极（32,34）的相应一个之下产生多个可编程电荷存储区域（42）和（41,44）。此外，非易失性存储器（10）是虚拟NOR型多位闪存EEPROM（电可擦除可编程只读存储器）。通过使用导电侧壁间隔件作为控制栅极，可以制造非常密集的多位非易失性存储器。

5. 发明申请

US20120194222A1 MEMORY HAVING A LATCHING SENSE AMPLIFIER RESISTANT TO NEGATIVE BIAS TEMPERATURE INSTABILITY AND METHOD THEREFOR 有权
标题翻译：具有耐受偏差温度不稳定性的锁存感测放大器的存储器及其方法
公开(公告)号：US20120194222A1
公开(公告)日：2012-08-02
申请号：US13016353
申请日：2011-01-28
申请人： Alexander B. Hoefler , James D. Burnett , Scott I. Remington
发明人： Alexander B. Hoefler , James D. Burnett , Scott I. Remington
IPC分类号： H03F3/16 , H03K3/011
CPC分类号： H03K3/356182 , G11C7/04 , G11C7/065 , H03K3/011
摘要： An integrated circuit includes a memory cell and a sense amplifier coupled to the memory cell via a first bit line and a second bit line. The sense amplifier includes first and second inverters cross-coupled to provide a latch. The first inverter is responsive to a first data signal provided by the memory cell over the first bit line. The second inverter is responsive to a second data signal as provided by the memory cell over the second bit line. A first negative bias temperature instability (NBTI) compensation transistor includes a source electrode coupled to receive a reference voltage, a drain electrode coupled to a source electrode of the first inverter, and a gate electrode coupled to first logic responsive to the first data signal. A second NBTI compensation transistor includes a source electrode coupled to receive the reference voltage, a drain electrode coupled to a source electrode of the second inverter, and a gate electrode coupled to second logic responsive to the second data signal, wherein the second data signal is a logical complement of the first data signal.
摘要翻译：集成电路包括经由第一位线和第二位线耦合到存储器单元的存储单元和读出放大器。读出放大器包括交叉耦合以提供锁存器的第一和第二反相器。第一反相器响应于由第一位线上的存储器单元提供的第一数据信号。第二反相器响应于由第二位线由存储器单元提供的第二数据信号。第一负偏压温度不稳定性（NBTI）补偿晶体管包括耦合以接收参考电压的源电极，耦合到第一反相器的源电极的漏极和响应于第一数据信号耦合到第一逻辑的栅电极。第二NBTI补偿晶体管包括耦合以接收参考电压的源电极，耦合到第二反相器的源电极的漏电极和响应于第二数据信号耦合到第二逻辑的栅电极，其中第二数据信号是第一数据信号的逻辑补码。

6. 发明授权

US07733711B2 Circuit and method for optimizing memory sense amplifier timing 有权
标题翻译：用于优化存储器读出放大器时序的电路和方法
公开(公告)号：US07733711B2
公开(公告)日：2010-06-08
申请号：US12206332
申请日：2008-09-08
申请人： James D. Burnett , Alexander B. Hoefler
发明人： James D. Burnett , Alexander B. Hoefler
IPC分类号： G11C16/04
CPC分类号： G11C29/02 , G11C7/04 , G11C7/08 , G11C7/14 , G11C7/22 , G11C11/41 , G11C29/023 , G11C29/026 , G11C29/028
摘要： A memory has an array of memory cells, a word line driver, a sense amplifier, and a sense enable circuit. Each memory cell has a coupling transistor for coupling a storage portion to a bit line. The coupling transistors have an average threshold voltage and a maximum threshold voltage. The word line driver is coupled to the array and is for enabling a selected row of memory cells in the array. The sense amplifier detects a state of a memory cell in the selected row in response to a sense enable signal. The sense enable circuit provides the sense enable signal at a time based on the maximum threshold voltage. This timing enables the sense amplifier sufficiently late for low temperature operation while providing for faster operation at high temperature than would normally be achieved using just the average threshold voltage in providing timing of the sense enable signal.
摘要翻译：存储器具有存储器单元阵列，字线驱动器，读出放大器和感测使能电路。每个存储单元具有用于将存储部分耦合到位线的耦合晶体管。耦合晶体管具有平均阈值电压和最大阈值电压。字线驱动器耦合到阵列，并且用于启用阵列中所选行的存储器单元。感测放大器响应于感测使能信号来检测所选行中的存储器单元的状态。感测使能电路基于最大阈值电压一次提供感测使能信号。该定时使得感测放大器足够迟到低温操作，同时在高温下提供比通常仅通过提供感测使能信号的定时的平均阈值电压实现的更快的操作。

7. 发明申请

US20080212387A1 INTEGRATED CIRCUIT FUSE ARRAY 有权
公开(公告)号：US20080212387A1
公开(公告)日：2008-09-04
申请号：US11681421
申请日：2007-03-02
申请人： Alexander B. Hoefler
发明人： Alexander B. Hoefler
IPC分类号： G11C17/18
CPC分类号： G11C17/16 , G11C17/18
摘要： The fuse array described herein is very compact and uses little semiconductor area because of its crosspoint architecture. The disclosed crosspoint architecture reduces the number of conductors that must be run horizontally or vertically through each bit cell. As a result, the area required for each bit cell is significantly reduced. In one embodiment, a selected set of voltages on various wordlines and bitlines are used to program the fuses to produce programmed fuses having a tighter distribution of impedances. Similarly, a selected set of voltages on various wordlines and bitlines are used to read the fuses.

8. 发明申请

US20080085574A1 ANTIFUSE ONE TIME PROGRAMMABLE MEMORY ARRAY AND METHOD OF MANUFACTURE 有权
标题翻译：防止一次可编程存储器阵列和制造方法
公开(公告)号：US20080085574A1
公开(公告)日：2008-04-10
申请号：US11538862
申请日：2006-10-05
申请人： Alexander B. Hoefler
发明人： Alexander B. Hoefler
IPC分类号： H01L21/82
CPC分类号： H01L27/101
摘要： A method for making a one time programmable (OTP) memory array includes providing a wafer comprising a buried insulator layer and a semiconductor layer over the buried insulator layer and forming a plurality of bit lines in the semiconductor layer. Each of the plurality of bit lines comprise a portion of the semiconductor layer and the plurality of bit lines are separated from each other by isolation regions formed in the semiconductor layer. The method further includes forming an anti-fuse dielectric layer over and in physical contact with the plurality of bit lines and the isolation regions, and forming a plurality of word lines over and in physical contact with the anti-fuse dielectric layer.
摘要翻译：一种用于制造一次性可编程（OTP）存储器阵列的方法包括在所述掩埋绝缘体层上提供包括掩埋绝缘体层和半导体层的晶片，并在所述半导体层中形成多个位线。多个位线中的每一个都包括半导体层的一部分，并且多个位线通过形成在半导体层中的隔离区彼此分离。该方法还包括在多个位线和隔离区域之间形成物理接触的反熔丝电介质层，并且与反熔丝电介质层物理接触地形成多个字线。

9. 发明授权

US06911360B2 Fuse and method for forming 失效
标题翻译：保险丝和成型方法
公开(公告)号：US06911360B2
公开(公告)日：2005-06-28
申请号：US10425275
申请日：2003-04-29
申请人： Chi Nan Brian Li , Alexander B. Hoefler , Der-Gao Lin
发明人： Chi Nan Brian Li , Alexander B. Hoefler , Der-Gao Lin
IPC分类号： H01L23/525 , H01L21/479
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An active fuse includes an active fuse geometry (120) that is used to form both a variable resistor (106) and a select transistor (110). In one embodiment, the active fuse geometry is formed in a portion of an active region (160) of a semiconductor substrate (140), and a select gate (124) is disposed over an end portion (123) of the active fuse geometry to form an integral select transistor (110) for use in programming the active fuse. The use of a shared active fuse geometry within the active region allows for reduced area requirements and improved sensing margins.
摘要翻译：有源保险丝包括用于形成可变电阻器（106）和选择晶体管（110）的有源熔丝几何形状（120）。在一个实施例中，有源熔丝几何形状形成在半导体衬底（140）的有源区（160）的一部分中，并且选择栅极（124）设置在有源熔丝几何的端部（123）上方，形成用于编程有源保险丝的整体选择晶体管（110）。在有源区域内使用共享的有源保险丝几何形状允许减少面积要求和改进的感测裕度。

10. 发明授权

US08254186B2 Circuit for verifying the write enable of a one time programmable memory 有权
标题翻译：用于验证一次可编程存储器的写使能的电路
公开(公告)号：US08254186B2
公开(公告)日：2012-08-28
申请号：US12771209
申请日：2010-04-30
申请人： Alexander B. Hoefler , Mohamed S. Moosa
发明人： Alexander B. Hoefler , Mohamed S. Moosa
IPC分类号： G11C7/22
CPC分类号： G11C17/16 , G11C17/18
摘要： A memory system including a one time programmable (OTP) memory is provided. The memory system further includes a write enable verification circuit including an asymmetric inverter stage and a symmetric inverter stage coupled at a node. The write enable verification circuit is configured to receive a write enable signal. When the write enable signal changes from a first voltage level to a second voltage level, a voltage at the node changes at a first rate and wherein when the write enable signal changes from the second voltage level to the first voltage level, the voltage at the node changes at a second rate higher than the first rate. The write enable verification circuit is further configured to generate a verified write enable signal for enabling programming of the OTP memory.
摘要翻译：提供了包括一次可编程（OTP）存储器的存储器系统。存储器系统还包括写使能验证电路，其包括耦合在节点处的非对称反相器级和对称反相器级。写使能验证电路被配置为接收写使能信号。当写使能信号从第一电压电平变为第二电压电平时，节点处的电压以第一速率变化，并且其中当写使能信号从第二电压电平变为第一电压电平时，节点以比第一速率高的第二速率改变。写使能验证电路还被配置为产生经验证的写使能信号，以使能对OTP存储器进行编程。

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