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    • 1. 发明申请
    • SERIALIZER/DESERIALIZER CIRCUIT FOR JITTER SENSITIVITY CHARACTERIZATION
    • 串行器/ DESERIALIZER电路,用于智能感应特性
    • US20040243899A1
    • 2004-12-02
    • US10707961
    • 2004-01-28
    • INTERNATIONAL BUSINESS MACHINES CORPORATIONINTERNATIONAL BUSINESS MACHINES CORPORATION
    • Dominique P. BonneauPhilippe HauvillerVincent Vallet
    • G11B005/00G06K005/04G01R031/28G11B020/20
    • G01R31/31709G01R31/31715G01R31/31725H03M9/00H04J2203/0062H04J2203/0089H04L1/205H04L1/243H04L1/244
    • Disclosed herein is an improved serializer/deserializer (SERDES) circuit (102) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (108). To that end, a delay perturbation is added to the serial data stream at the serializer (120) output, typically using a variable delay (DEL) line (116). Then, the perturbed serial data stream is looped back to the CDR circuit. A dedicated circuit in the control logic (112) coupled to the DEL line and the deserializer circuit (110) analyzes the recovered data to characterize the sensitivity of the CDR circuit to the jitter frequency. By continuously modifying the output delay of said serial data stream, i.e. the amplitude and the frequency of the perturbation, one can generate a perturbed serial data stream, very close to the real jittered data. Moreover, the perturbed data stream can be transmitted to any distant SERDES circuit (104) before it is looped back to the CDR circuit. By comparing the jitter sensitivity with and without using the transmission link (106), one can easily characterize the amount of jitter added by said link. A method of testing the jitter sensitivity of the CDR circuit is also disclosed.
    • 本文公开了一种改进的串行器/解串器(SERDES)电路(102),其具有被配置为执行时钟和数据恢复(CDR)电路(108)的原位抖动灵敏度表征的内置自检能力。 为此,通常使用可变延迟(DEL)线(116),在串行器(120)输出端口向串行数据流添加延迟扰动。 然后,干扰的串行数据流被环回到CDR电路。 耦合到DEL线的控制逻辑(112)中的专用电路和解串行器电路(110)分析恢复的数据以表征CDR电路对抖动频率的灵敏度。 通过连续地修改所述串行数据流的输出延迟,即扰动的振幅和频率,可以产生非常接近实际抖动数据的干扰的串行数据流。 此外,扰动的数据流可以在被环回到CDR电路之前被发送到任何远端的SERDES电路(104)。 通过比较具有和不使用传输链路(106)的抖动灵敏度,可以容易地表征所述链路所添加的抖动量。 还公开了测试CDR电路的抖动灵敏度的方法。