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1. 发明申请

US20040243899A1 SERIALIZER/DESERIALIZER CIRCUIT FOR JITTER SENSITIVITY CHARACTERIZATION 有权
标题翻译：串行器/ DESERIALIZER电路，用于智能感应特性
公开(公告)号：US20040243899A1
公开(公告)日：2004-12-02
申请号：US10707961
申请日：2004-01-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION , INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Dominique P. Bonneau , Philippe Hauviller , Vincent Vallet
IPC分类号： G11B005/00 , G06K005/04 , G01R031/28 , G11B020/20
CPC分类号： G01R31/31709 , G01R31/31715 , G01R31/31725 , H03M9/00 , H04J2203/0062 , H04J2203/0089 , H04L1/205 , H04L1/243 , H04L1/244
摘要： Disclosed herein is an improved serializer/deserializer (SERDES) circuit (102) having built-in self-test capabilities that is configured to perform an in-situ jitter sensitivity characterization of the clock and data recovery (CDR) circuit (108). To that end, a delay perturbation is added to the serial data stream at the serializer (120) output, typically using a variable delay (DEL) line (116). Then, the perturbed serial data stream is looped back to the CDR circuit. A dedicated circuit in the control logic (112) coupled to the DEL line and the deserializer circuit (110) analyzes the recovered data to characterize the sensitivity of the CDR circuit to the jitter frequency. By continuously modifying the output delay of said serial data stream, i.e. the amplitude and the frequency of the perturbation, one can generate a perturbed serial data stream, very close to the real jittered data. Moreover, the perturbed data stream can be transmitted to any distant SERDES circuit (104) before it is looped back to the CDR circuit. By comparing the jitter sensitivity with and without using the transmission link (106), one can easily characterize the amount of jitter added by said link. A method of testing the jitter sensitivity of the CDR circuit is also disclosed.
摘要翻译：本文公开了一种改进的串行器/解串器（SERDES）电路（102），其具有被配置为执行时钟和数据恢复（CDR）电路（108）的原位抖动灵敏度表征的内置自检能力。为此，通常使用可变延迟（DEL）线（116），在串行器（120）输出端口向串行数据流添加延迟扰动。然后，干扰的串行数据流被环回到CDR电路。耦合到DEL线的控制逻辑（112）中的专用电路和解串行器电路（110）分析恢复的数据以表征CDR电路对抖动频率的灵敏度。通过连续地修改所述串行数据流的输出延迟，即扰动的振幅和频率，可以产生非常接近实际抖动数据的干扰的串行数据流。此外，扰动的数据流可以在被环回到CDR电路之前被发送到任何远端的SERDES电路（104）。通过比较具有和不使用传输链路（106）的抖动灵敏度，可以容易地表征所述链路所添加的抖动量。还公开了测试CDR电路的抖动灵敏度的方法。

2. 发明申请

US20230140791A1 PROGRAMMING TASK SUPPORTING MATERIAL GENERATION 有权
公开(公告)号：US20230140791A1
公开(公告)日：2023-05-04
申请号：US17514009
申请日：2021-10-29
申请人： International Business Machines Corporation
发明人： Ana Paula Brambila , Thiago Bianchi , Marco Aurelio Stelmar Netto , Thiago Roberto Fontes Iunes
IPC分类号： G06F9/50 , G06F16/93
摘要： The present specification describes a computer-implemented method. According to the method, a programming task to be executed is received. A completed task that is similar to the programming task to be executed is identified from a database of completed tasks. Supporting documentation associated with the completed task is extracted and supporting material associated with the completed task is generated and transmitted to a computing device which is to execute the programming task.

3. 发明申请

US20230139805A1 CONTROL UNIT FOR QUBITS 有权
公开(公告)号：US20230139805A1
公开(公告)日：2023-05-04
申请号：US17453499
申请日：2021-11-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Thomas Morf , Cezar Bogdan Zota , Peter Mueller , Pier Andrea Francese , Marcel A. Kossel , Matthias Braendli , Mridula Prathapan
IPC分类号： G06F15/82 , G06N10/40
摘要： The invention relates to a control unit for controlling a data transfer between a classical processor and a quantum processor with a plurality of qubits. The control unit comprises a plurality of control and read-out circuits configured for controlling and reading out the plurality of qubits. Each of the control and read-out circuits is assigned to one or more of the qubits. A controlling of the quantum processor by the control unit comprises selectively powering on a subset of the control and read-out circuits during an instruction cycle, while ensuring that the remaining control and read-out circuits are powered off during the instruction cycle. The powered-on subset of control and read-out circuits is used to control a subset of the qubits and to read out data from the subset of qubits.

4. 发明申请

US20230139759A1 DATA SWAP PREVENTION IN DISTRIBUTED COMPUTING ENVIRONMENTS 有权
公开(公告)号：US20230139759A1
公开(公告)日：2023-05-04
申请号：US17518932
申请日：2021-11-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Abhay Kumar Patra , Rakesh Shinde , Harish Bharti , Vijay Ekambaram
IPC分类号： G06F9/46 , G06F9/30 , G06F9/50
摘要： Inadvertent data swaps can be prevented by measuring volume of transactions in distributed computing environment to determine locations for potential data swaps; and managing a correlation between a thread identification (ID) and transaction header (ID) for transactions in the distributed computing environment. In some embodiments, the prevention of data swaps can further include performing a data transmission interruption to avoid data swaps at the locations for potential data swaps. When the thread identification (ID) and transaction header (ID) do not match the potential for data swaps can be high.

5. 发明申请

US20230139437A1 CLASSIFIER PROCESSING USING MULTIPLE BINARY CLASSIFIER STAGES 有权
公开(公告)号：US20230139437A1
公开(公告)日：2023-05-04
申请号：US17516870
申请日：2021-11-02
申请人： International Business Machines Corporation
发明人： Igor Henrique Nicacio Braga
IPC分类号： G06N3/08 , G06K9/62
摘要： An embodiment generates a training batch of data points from training data for a plurality of classes and builds a multi-class classifier having a series of binary classifiers arranged in a first order. Each of the binary classifiers is associated with a respective class. The embodiment trains the multi-class classifier with the binary classifiers arranged in a first order and, at each binary classifier, the embodiment identifies data points as belonging to the class associated with the respective classifier and updates the training batch to exclude the classified data points. The embodiment then modifies the multi-class classifier by changing the order of classifiers and repeats the training of the multi-class classifier with the series of binary classifiers arranged in a second order. The embodiment then selects a final configuration of the multi-class classifier based at least in part on a comparison of first training results to the second training results.

6. 发明申请

US20230139329A1 DYNAMIC VIRTUAL PRIVATE NETWORK PROTOCOL CONFIGURATION 有权
公开(公告)号：US20230139329A1
公开(公告)日：2023-05-04
申请号：US17453090
申请日：2021-11-01
申请人： International Business Machines Corporation
发明人： Hemant Kumar Sivaswamy , Venkata Vara Prasad Karri , Sarbajit K. Rakshit , Seema Nagar
IPC分类号： H04L29/06 , G06N20/00
摘要： Provided is a computer-implemented method, system, and computer program product for dynamically configuring a virtual private network (VPN) protocol of a VPN tunnel. A processor may analyze data activity associated with a first device, where the first device is connected to a second device using a VPN tunnel. The processor may compare the analyzed data activity to a set of policies for determining a VPN protocol to apply to the VPN tunnel. The processor may identify, based on the comparing, a first VPN protocol from a plurality of VPN protocols. The processor may apply the first VPN protocol to the VPN tunnel.

7. 发明申请

US20230138988A1 DUAL DAMASCENE FULLY-ALIGNED VIA INTERCONNECTS WITH DUAL ETCH LAYERS 有权
公开(公告)号：US20230138988A1
公开(公告)日：2023-05-04
申请号：US17514036
申请日：2021-10-29
申请人： International Business Machines Corporation
发明人： Koichi Motoyama , Kenneth Chun Kuen Cheng , Chanro Park , Chih-Chao Yang
IPC分类号： H01L21/768 , H01L23/522
摘要： A fully-aligned via interconnect structure is provided in which a first etch stop layer is formed on a first interconnect dielectric material layer containing an electrically conductive line structure to protect the interconnect dielectric material from eroding during metallization used in providing a combined vialline electrically conductive structure in a second interconnect dielectric material layer that is formed above the first interconnect dielectric material layer. The interconnect structure has low resistance due to the maximized contact between the via portion of combined vialline electrically conductive structure and the underlying electrically conductive line structure. Moreover, no bowing or metal fangs are formed, and no metal residue is introduced into the first interconnect dielectric material layer during metallization.

8. 发明申请

US20230138987A1 EFFICIENT MACHINE LEARNING MODEL INFERENCE 有权
公开(公告)号：US20230138987A1
公开(公告)日：2023-05-04
申请号：US17453565
申请日：2021-11-04
申请人： International Business Machines Corporation
发明人： Song Bo , Dong Hai Yu , Jun Wang , Jiang Bo Kang , Yao Dong Liu
IPC分类号： G06N3/08 , G06N20/20
摘要： One or more computer processors calculate a cache prediction for a received inference request within an inference cache structured as a self-learning tree, wherein the inference request comprises a set of input values. The one or more computer processors responsive to the retrieved cache prediction exceeding a cache prediction threshold, transmit the cache prediction. The one or more computer processors parallel compute a model prediction for the received inference request utilizing a trained model. The one or more computer processors responsive to the retrieved model prediction exceeding a model prediction threshold, convert the trained model into a tree structure. The one or more computer processors update the inference cache with the converted train model. The one or more computer processors transmit the model prediction.

9. 发明申请

US20230138367A1 GENERATION OF GRAPHICAL USER INTERFACE PROTOTYPES 有权
公开(公告)号：US20230138367A1
公开(公告)日：2023-05-04
申请号：US17515917
申请日：2021-11-01
申请人： International Business Machines Corporation
发明人： Yuan Jie Song , Xiao Feng Ji , Dan Zhang , Jun Qian Zhou , Meng Chai
IPC分类号： G06F8/38 , G06N20/00
摘要： A method of generating a prototype of a graphical user interface (GUI). The method includes acquiring a draft wireframe representing a GUI design, the draft wireframe including one or more wireframe components, and decomposing the draft wireframe into one or more component slices, each component slice including a respective wireframe component of the one or more wireframe components. The method also includes generating a component slice sequence including the one or more component slices and at least one additional component slice selected based on the draft wireframe, constructing a wireframe based on the component slice sequence, and generating a prototype of the GUI design based on the constructed wireframe.

10. 发明申请

US20230137421A1 MRAM BOTTOM ELECTRODE SHROUD 有权
公开(公告)号：US20230137421A1
公开(公告)日：2023-05-04
申请号：US17452807
申请日：2021-10-29
申请人： International Business Machines Corporation
发明人： Oscar van der Straten , Koichi Motoyama , Kenneth Chun Kuen Cheng , Joseph F. Maniscalco , Chih-Chao Yang
IPC分类号： H01L43/02 , H01L43/12 , H01L27/22
摘要： A memory device includes a bottom electrode having an uppermost surface, a first sidewall, and a second sidewall. The memory device further includes a dielectric layer covering the uppermost surface and the first and second sidewalls of the bottom electrode such that an uppermost surface of the dielectric layer is arranged higher than the uppermost surface of the bottom electrode. The memory device further includes a metal body in direct contact with the uppermost surface of the bottom electrode and extending through the dielectric layer to the uppermost surface of the dielectric layer. The memory device further includes a memory component arranged in direct contact with the metal body and with the uppermost surface of the dielectric layer.

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