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1. 发明授权

US06380047B1 Shallow trench isolation formation with two source/drain masks and simplified planarization mask 有权
标题翻译：浅沟槽隔离形成，具有两个源/漏屏蔽和简化的平面化掩模
公开(公告)号：US06380047B1
公开(公告)日：2002-04-30
申请号：US09634990
申请日：2000-08-08
申请人： Basab Bandyopadhyay , Nick Kepler , Olov Karlsson , Larry Wang , Effiong Ibok , Christopher F. Lyons
发明人： Basab Bandyopadhyay , Nick Kepler , Olov Karlsson , Larry Wang , Effiong Ibok , Christopher F. Lyons
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate with improved planarity using a simplified reverse source/drain planarization mask. Embodiments include forming large trenches and refilling them with an insulating material which also covers the substrate surface, masking the areas above the large trenches, etching to remove substantially all of the insulating material on the substrate surface and polishing to planarize the insulating material above the large trenches. Small trenches and peripheral trenches surrounding the large trenches are then formed, refilled with insulating material, and planarized. Since the large trenches are formed prior to and separately from the small trenches, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches. The use of a planarization mask with relatively few features having a relatively large geometry avoids the need to create and implement a complex and critical mask, thereby reducing manufacturing costs and increasing production throughput. Furthermore, because the large and small trenches are not polished at the same time, overpolishing is avoided, thereby improving planarity and, hence, the accuracy of subsequent photolithographic processing.
摘要翻译：使用简化的反向源极/漏极平面化掩模，在具有改善的平面度的半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构。实施例包括形成大沟槽并用也覆盖衬底表面的绝缘材料再填充它们，掩蔽大沟槽上方的区域，蚀刻以基本上除去衬底表面上的所有绝缘材料，并抛光以平坦化绝缘材料沟渠然后形成围绕大沟槽的小沟槽和外围沟槽，用绝缘材料重新填充并平坦化。由于在小沟槽之前和分开形成大沟槽，所以可以在仅在大沟槽上而不是小沟槽形成相对简单的平坦化掩模之后进行蚀刻。使用具有相对较大几何特征的平面化掩模的使用避免了创建和实现复杂和关键掩模的需要，从而降低制造成本并提高生产量。此外，因为大的和小的沟槽不同时被抛光，所以避免了过度抛光，从而提高平面度，从而提高随后的光刻处理的精度。

2. 发明授权

US6165906A Semiconductor topography employing a shallow trench isolation structure with an improved trench edge 有权
标题翻译：半导体拓扑采用具有改进的沟槽边缘的浅沟槽隔离结构
公开(公告)号：US6165906A
公开(公告)日：2000-12-26
申请号：US237412
申请日：1999-01-26
申请人： Basab Bandyopadhyay , Douglas J. Bonser , Michael J. McBride
发明人： Basab Bandyopadhyay , Douglas J. Bonser , Michael J. McBride
IPC分类号： H01L21/3065 , H01L21/311 , H01L21/316 , H01L21/32 , H01L21/762
CPC分类号： H01L21/76235 , H01L21/3065 , H01L21/31116 , H01L21/31662 , H01L21/32
摘要： A method of forming an improved isolation trench between active regions within the semiconductor substrate involves oxidizing unmasked portions of a semiconductor substrate prior to etching an isolation trench into the semiconductor substrate. By oxidizing the unmasked portions of the semiconductor prior to etching, an isolation trench with rounded corners may be formed.
摘要翻译：在半导体衬底内的有源区域之间形成改进的隔离沟槽的方法包括在将隔离沟槽蚀刻到半导体衬底之前氧化半导体衬底的未屏蔽部分。通过在蚀刻之前氧化半导体的未屏蔽部分，可以形成具有圆角的隔离沟槽。

3. 发明授权

US6124183A Shallow trench isolation formation with simplified reverse planarization mask 失效
标题翻译：浅沟槽隔离形成，具有简化的反向平面化掩模
公开(公告)号：US6124183A
公开(公告)日：2000-09-26
申请号：US992490
申请日：1997-12-18
申请人： Olov Karlsson , Christopher F. Lyons , Basab Bandyopadhyay , Nick Kepler , Larry Wang , Effiong Ibok
发明人： Olov Karlsson , Christopher F. Lyons , Basab Bandyopadhyay , Nick Kepler , Larry Wang , Effiong Ibok
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate using a simplified reverse source/drain planarization mask. Embodiments include forming trenches and refilling them with an insulating material which also covers a main surface of the substrate, polishing to remove an upper portion of the insulating material and to planarize the insulating material above the small trenches, furnace annealing to densify and strengthen the remaining insulating material, masking the insulating material above the large trenches, isotropically etching the insulating material, and polishing to planarize the insulating material. Since the insulating material is partially planarized and strengthened prior to etching, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches. Because the features of the planarization mask are relatively few and have a relatively large geometry, the present invention avoids the need to create and implement a critical mask, enabling production costs to be reduced and manufacturing throughput to be increased.
摘要翻译：使用简化的反向源极/漏极平面化掩模在半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构。实施例包括形成沟槽并用绝缘材料再填充它们，该绝缘材料也覆盖衬底的主表面，抛光以除去绝缘材料的上部并平面化小沟槽上方的绝缘材料，炉退火致密化并加强其余部分绝缘材料，掩蔽大沟槽上方的绝缘材料，各向同性地蚀刻绝缘材料，并抛光以使绝缘材料平坦化。由于在蚀刻之前绝缘材料被部分平坦化和加强，因此可以在仅在大的沟槽上而不是小沟槽形成相对简单的平坦化掩模之后进行蚀刻。由于平面化掩模的特征相对较少并且具有相对较大的几何形状，因此本发明避免了创建和实施关键掩模的需要，从而能够降低生产成本并提高生产量。

4. 发明授权

US6090712A Shallow trench isolation formation with no polish stop 失效
标题翻译：浅沟隔离形成，无抛光停止
公开(公告)号：US6090712A
公开(公告)日：2000-07-18
申请号：US992489
申请日：1997-12-18
申请人： Christopher F. Lyons , Basab Bandyopadhyay , Nick Kepler , Olov Karlsson , Larry Wang , Effiong Obok
发明人： Christopher F. Lyons , Basab Bandyopadhyay , Nick Kepler , Olov Karlsson , Larry Wang , Effiong Obok
IPC分类号： H01L21/762 , H01L21/461
CPC分类号： H01L21/76224
摘要： An insulated trench isolation structure is formed in a semiconductor substrate omitting a barrier nitride polish stop layer while avoiding substrate damage, thereby simplifying trench formation and improving planarity. After trench fill, polishing is conducted to effect substantial planarization without exposing the substrate surface, thereby avoiding substrate damage. Etching is then conducted to expose the substrate surface. The omission of the barrier nitride polish stop avoids generation of a topographical step at the substrate/trench fill interface, thereby enhancing the accuracy of subsequent photolithographic techniques in forming features with minimal dimensions.
摘要翻译：在半导体衬底中形成绝缘沟槽隔离结构，省略了阻挡氮化物抛光停止层，同时避免了衬底损坏，从而简化了沟槽形成并提高了平面度。在沟槽填充之后，进行抛光以实现基本平坦化而不暴露衬底表面，从而避免衬底损坏。然后进行蚀刻以暴露衬底表面。阻挡氮化物抛光停止的省略避免了在衬底/沟槽填充界面处产生形貌步骤，从而在最小尺寸形成特征的同时提高随后的光刻技术的精度。

5. 发明授权

US5894168A Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization 失效
标题翻译：用于制造具有最佳多晶硅互连布局的集成电路的掩模生成技术，用于实现全局平坦化
公开(公告)号：US5894168A
公开(公告)日：1999-04-13
申请号：US947521
申请日：1997-10-02
申请人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
IPC分类号： H01L21/3105 , H01L21/768 , H01L23/528 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76819 , H01L21/31053 , H01L23/528 , H01L2924/0002
摘要： A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.
摘要翻译：提供了一种光刻掩模衍生方法，用于改善沉积在由衍生的光刻掩模形成的导体上的层间电介质的整体平面性。衍生出光刻掩模，使得非操作导体彼此间隔开最小距离和与操作导体间隔开的规则间隔排列的导体，其上可使用例如化学机械的电介质层沉积并容易地平坦化抛光技术。所得的层间电介质上表面在整个半导体形貌上被全局平坦化到均匀的高度。操作导体与非操作导体不相似，因为操作导体连接在可操作的集成电路的电路中。非操作导体不在集成电路路径内连接，并且通常浮动或连接到电源。因此，非操作导体对集成电路功能没有贡献，而不是为覆盖的层间电介质提供结构平面性。掩模推导方法适用于金属互连光刻掩模或多晶硅互连光刻掩模。

6. 发明授权

US5850105A Substantially planar semiconductor topography using dielectrics and chemical mechanical polish 失效
标题翻译：使用电介质和化学机械抛光的基本平面的半导体形貌
公开(公告)号：US5850105A
公开(公告)日：1998-12-15
申请号：US822120
申请日：1997-03-21
申请人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
发明人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L23/532 , H01L23/58
CPC分类号： H01L23/5329 , H01L2924/0002
摘要： A method for forming a multilevel interconnect structure having a globally planarized upper surface. Dielectrics are deposited upon a semiconductor to minimize pre-existing disparities in topographical height and to create an upper surface topography having a polish rate greater than that of lower regions. Subsequent chemical mechanical polishing produces a substantially planar surface.
摘要翻译：一种用于形成具有全局平坦化的上表面的多层互连结构的方法。电介质沉积在半导体上以最小化形貌高度上的先前存在的差异并产生具有比下部区域更高的抛光速率的上表面形貌。随后的化学机械抛光产生基本平坦的表面。

7. 发明授权

US5759913A Method of formation of an air gap within a semiconductor dielectric by solvent desorption 失效
标题翻译：通过溶剂解吸形成半导体电介质内气隙的方法
公开(公告)号：US5759913A
公开(公告)日：1998-06-02
申请号：US658547
申请日：1996-06-05
申请人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
发明人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/768 , H01L21/283
CPC分类号： H01L21/7682 , H01L21/76828
摘要： A dielectric material is provided having air gaps which form during dielectric deposition between interconnects. The dielectric is deposited in interconnect-spaced geometries which have certain aspect ratios and which are exposed at the bottom of the geometries to a hygroscopic dielectric. During deposition, the dielectric is forced along the sidewall of the spaced interconnects as a result of moisture ougasing from the hygroscopic dielectric. Over a period of time, a keyhole occurs with pile up accumulation (or cusping) at the corners of the spaced interconnects. By decreasing the deposition temperature in a subsequent step, outgasing is minimized, and deposition over the keyhole and upon the hygroscopic dielectric takes place. Keyhole coverage results in an air gap which is surrounded on all sides by the fill dielectric. Air gap between interconnects helps reduce permittivity of the overall dielectric structure, resulting in a lessening of the interconnect line-to-line capacitance.
摘要翻译：提供介电材料，其具有在互连之间的介电沉积期间形成的气隙。电介质沉积在具有特定纵横比的互连隔开的几何形状中，并且在几何形状的底部暴露于吸湿电介质。在沉积期间，电介质由于从吸湿介质的湿气渗出而沿着间隔开的互连件的侧壁被迫。在一段时间内，在间隔互连的角落处堆积积聚（或缩小）时，会产生锁孔。通过在随后的步骤中降低沉积温度，最大限度地减少了沉积，并且在钥匙孔和吸湿介质上沉积。钥匙孔覆盖导致气隙由填充电介质所包围。互连之间的空气间隙有助于降低整个电介质结构的介电常数，导致互连线对线电容的减小。

8. 发明授权

US06376330B1 Dielectric having an air gap formed between closely spaced interconnect lines 失效
标题翻译：电介质具有形成在紧密间隔的互连线之间的气隙
公开(公告)号：US06376330B1
公开(公告)日：2002-04-23
申请号：US08655242
申请日：1996-06-05
申请人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
发明人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
IPC分类号： H01L2176
CPC分类号： H01L21/7682
摘要： A dielectric material is provided having air gaps purposely formed within the dielectric. The dielectric is deposited, and air gaps formed, between respective interconnect lines. The geometries between interconnect lines is purposely controlled to achieve a large aspect ratio necessary to produce air gaps during CVD of the dielectric. Air gaps exist between interconnects to reduce the line-to-line capacitance, and thereby reduce the propagation delay associated with closely spaced interconnects.
摘要翻译：提供一种电介质材料，其具有在电介质中有目的地形成的气隙。电介质被沉积，并且在相应的互连线之间形成气隙。有意地控制互连线之间的几何形状以实现在电介质CVD期间产生气隙所需的大的纵横比。互连之间存在空隙，以减少线间电容，从而减少与紧密间隔的互连相关的传播延迟。

9. 发明授权

US6127719A Subfield conductive layer and method of manufacture 失效
标题翻译：子场导电层及其制造方法
公开(公告)号：US6127719A
公开(公告)日：2000-10-03
申请号：US038464
申请日：1998-03-11
申请人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
发明人： H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/74 , H01L29/00 , H01L31/119
CPC分类号： H01L21/74
摘要： A subfield conductive layer is provided, wherein a conductive layer is implanted beneath and laterally adjacent a field dielectric. The subfield conductive layer is placed within the silicon substrate after the field dielectric is formed. The conductive layer represents a buried interconnect which resides between isolated devices. The buried interconnect, however, is formed using high energy ion implant through a field dielectric formed either by LOCOS or shallow trench isolation techniques. The buried interconnect, or conductive layer, resides and electrically connects source and drain regions of two isolated devices.
摘要翻译：提供了一个子场导电层，其中将导电层注入到场电介质的下面和横向附近。在形成场电介质之后，将子场导电层置于硅衬底内。导电层表示驻留在隔离器件之间的掩埋互连。然而，埋入式互连通过使用由LOCOS或浅沟槽隔离技术形成的场电介质的高能离子注入形成。埋置的互连或导电层驻留并电连接两个隔离器件的源极和漏极区域。

10. 发明授权

US06074927A Shallow trench isolation formation with trench wall spacer 失效
标题翻译：浅沟槽隔离形成与沟槽壁间隔
公开(公告)号：US06074927A
公开(公告)日：2000-06-13
申请号：US87662
申请日：1998-06-01
申请人： Nick Kepler , Basab Bandyopadhyay , Olov Karlsson , Larry Wang , Effiong Ibok , Christopher F. Lyons
发明人： Nick Kepler , Basab Bandyopadhyay , Olov Karlsson , Larry Wang , Effiong Ibok , Christopher F. Lyons
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76232
摘要： A shallow trench isolation structure is formed which enables the growth of a high quality gate oxide at the trench edges and protects the field oxide from gouging during post-gate processing, such as during the local interconnect etch, thereby allowing the formation of high-quality implanted junctions. Embodiments include forming a photoresist mask directly on a pad oxide layer which, in turn, is formed on a main surface of a semiconductor substrate or an epitaxial layer on a semiconductor substrate. After masking, the substrate is etched to form a trench, an oxide liner is grown in the trench surface, and a polish stop layer is deposited in the trench on the oxide liner and on the pad oxide layer. The polish stop layer is then masked to the trench edges, and the polish stop in the trench is anisotropically etched, to remove the polish stop at the bottom of the trenches leaving a portion overlying the side surfaces and edges of the trench on the oxide liner. The trench is then filled with an insulating material, the insulating material is planarized, and the polish stop over the pad oxide layer is removed by anisotropic etching. Thus, the oxide liner is allowed to grow on the trench edges without the restraint of a polish stop, resulting in a thick, rounded oxide on the trench edges. The portion of the polish stop remaining in the trench and on the oxide liner at the trench edges serves as a protective spacer, protecting the field oxide from erosion during subsequent processing steps.
摘要翻译：形成浅沟槽隔离结构，其使得能够在沟槽边缘处生长高质量的栅极氧化物，并且保护场氧化物在后栅极处理（例如在局部互连蚀刻期间）中的气蚀，从而允许形成高质量植入路口。实施例包括直接在衬垫氧化物层上形成光致抗蚀剂掩模，衬垫氧化物层又形成在半导体衬底的主表面或半导体衬底上的外延层上。在掩模之后，蚀刻衬底以形成沟槽，在沟槽表面中生长氧化物衬垫，并且抛光停止层沉积在氧化物衬垫和衬垫氧化物层上的沟槽中。然后将抛光停止层掩蔽到沟槽边缘，并且沟槽中的抛光停止点被各向异性地蚀刻，以去除沟槽底部的抛光停止部，留下覆盖氧化物衬垫上的沟槽的侧表面和边缘的部分。然后用绝缘材料填充沟槽，使绝缘材料平坦化，并通过各向异性蚀刻去除衬垫氧化物层上的抛光剂停止。因此，允许氧化物衬垫在沟槽边缘上生长而不受抛光停止的限制，导致沟槽边缘上的厚的圆形氧化物。保留在沟槽中的抛光停止部分和在沟槽边缘处的氧化物衬垫上的部分用作保护间隔物，在随后的处理步骤期间保护场氧化物免受侵蚀。

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