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1. 发明授权

US06171962B2 Shallow trench isolation formation without planarization mask 失效
标题翻译：浅沟槽隔离形成无平面化掩模
公开(公告)号：US06171962B2
公开(公告)日：2001-01-09
申请号：US08993889
申请日：1997-12-18
申请人： Olov Karlsson , Christopher F. Lyons , Basab Bandyopadhyay , Nick Kepler , Larry Wang , Effiong Ibok
发明人： Olov Karlsson , Christopher F. Lyons , Basab Bandyopadhyay , Nick Kepler , Larry Wang , Effiong Ibok
IPC分类号： H01L21302
CPC分类号： H01L21/76229 , H01L21/31053
摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate without a planarization mask or etch. Embodiments include forming trenches and refilling them with an insulating material which also covers the substrate surface, followed by polishing to remove an upper portion of the insulating material and to planarize the insulating material above the small trenches. A second layer of insulating material is then deposited to fill seams in the insulating material above the small trenches and to fill steps in the insulating material above the large trenches. The insulating material is then planarized. Since the insulating material is partially planarized by the first polish and the seams and steps are filled by the second deposition, the resulting topography of the upper surface of the second layer of insulating material is small enough to enable a direct final polish without the need to create and implement a planarization mask and to perform an etch and mask removal, thereby reducing manufacturing costs and increasing production throughput.
摘要翻译：在半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构，而不需要平坦化掩模或蚀刻。实施例包括用绝缘材料形成沟槽并再填充它们，该绝缘材料也覆盖衬底表面，接着进行抛光以除去绝缘材料的上部并使小沟槽上方的绝缘材料平坦化。然后沉积第二层绝缘材料以填充小沟槽上方的绝缘材料中的接缝，并填充大沟槽上方的绝缘材料的步骤。然后将绝缘材料平坦化。由于绝缘材料被第一抛光部分地平坦化并且接缝和步骤通过第二次沉积来填充，所以第二层绝缘材料的上表面的所得形貌足够小以使得能够进行直接的最终抛光，而不需要创建并实现平面化掩模并执行蚀刻和掩模去除，从而降低制造成本并提高生产量。

2. 发明授权

US6130467A Shallow trench isolation with spacers for improved gate oxide quality 失效
标题翻译：浅沟槽隔离带隔板，提高栅极氧化物质量
公开(公告)号：US6130467A
公开(公告)日：2000-10-10
申请号：US993857
申请日：1997-12-18
申请人： Basab Bandyopadhyay , Nick Kepler , Olov Karlsson , Larry Wang , Effiong Ibok , Christopher F. Lyons
发明人： Basab Bandyopadhyay , Nick Kepler , Olov Karlsson , Larry Wang , Effiong Ibok , Christopher F. Lyons
IPC分类号： H01L21/762 , H01L29/00
CPC分类号： H01L21/76224
摘要： An insulated trench isolation structure is formed in a semiconductor substrate with an oxide or nitride spacer overlying and protecting a portion of a pad oxide layer at the trench edge such that the pad oxide layer acts as part of the gate oxide layer. Embodiments include providing a step between the trench fill and the pad oxide layer and forming the protective spacer thereon. The protective spacer protects the underlying portion of the pad oxide layer at the trench edge during pad oxide removal prior to forming a gate oxide. Therefore, it is only necessary to grow the gate oxide on the main surface of the substrate, not at the trench edges. The gate oxide can then be formed uniformly thin, while the remaining pad oxide at the trench edges is relatively thick.
摘要翻译：在具有氧化物或氮化物间隔物的半导体衬底中形成绝缘沟槽隔离结构，覆盖并保护沟槽边缘处的焊盘氧化物层的一部分，使得焊盘氧化物层用作栅极氧化物层的一部分。实施例包括在沟槽填充物和衬垫氧化物层之间提供步骤，并在其上形成保护隔离物。在形成栅极氧化物之前，保护间隔物在衬垫氧化物去除期间保护焊盘氧化物层的沟槽边缘的下面部分。因此，仅需要在衬底的主表面上而不是在沟槽边缘处生长栅极氧化物。然后可以将栅极氧化物均匀地形成，而沟槽边缘处的剩余焊盘氧化物相对较厚。

3. 发明授权

US6090713A Shallow trench isolation formation with simplified reverse planarization mask 失效
标题翻译：浅沟槽隔离形成，具有简化的反向平面化掩模
公开(公告)号：US6090713A
公开(公告)日：2000-07-18
申请号：US992491
申请日：1997-12-18
申请人： Olov Karlsson , Christopher F. Lyons , Basab Bandyophadhyay , Nick Kepler , Larry Wang , Effiong Ibok
发明人： Olov Karlsson , Christopher F. Lyons , Basab Bandyophadhyay , Nick Kepler , Larry Wang , Effiong Ibok
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/316
CPC分类号： H01L21/76229 , H01L21/31053 , H01L21/31055
摘要： An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate using a simplified reverse source/drain planarization mask. Embodiments include forming trenches and refilling them with an insulating material which also covers the substrate surface, polishing to remove an upper portion of the insulating material and to planarize the insulating material above the small trenches, depositing a second, thin layer of insulating material filling seams in the insulating material above the small trenches, masking the insulating material above the large trenches, isotropically etching, and polishing to planarize the insulating material. Since the insulating material is partially planarized and the seams over the small trenches are filled, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches. The use of a planarization mask having relatively few features with relatively large geometry avoids the necessity of creating and implementing a complex, critical mask, thereby reducing manufacturing costs and increasing production throughput.
摘要翻译：使用简化的反向源极/漏极平面化掩模在半导体衬底中形成具有不同宽度的大的和小的沟槽的绝缘沟槽隔离结构。实施例包括形成沟槽并用也覆盖衬底表面的绝缘材料再填充它们，抛光以去除绝缘材料的上部并平面化小沟槽上方的绝缘材料，沉积第二薄层的绝缘材料填充接缝在小沟槽上方的绝缘材料中，掩蔽大沟槽上方的绝缘材料，各向同性蚀刻和抛光以使绝缘材料平坦化。由于绝缘材料被部分平坦化并且填充了小沟槽上的接缝，所以可以在仅在大沟槽而不是小沟槽上形成相对简单的平坦化掩模之后进行蚀刻。使用具有相对较小几何特征的平面化掩模具有相对大的几何形状避免了创建和实施复杂的关键掩模的必要性，从而降低制造成本并提高生产量。

4. 发明授权

US5930645A Shallow trench isolation formation with reduced polish stop thickness 失效
标题翻译：浅沟隔离结构，减少抛光停止厚度
公开(公告)号：US5930645A
公开(公告)日：1999-07-27
申请号：US993881
申请日：1997-12-18
申请人： Christopher F. Lyons , Basab Bandyopadhyay , Nick Kepler , Olov Karlsson , Larry Wang , Effiong Ibok
发明人： Christopher F. Lyons , Basab Bandyopadhyay , Nick Kepler , Olov Karlsson , Larry Wang , Effiong Ibok
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76232
摘要： An insulated trench isolation structure is formed in a semiconductor substrate using a thin amorphous silicon or polysilicon polish stop layer by adding a reflectance compensation layer on the polish stop layer. As a result, the topological step between the main surface of the substrate and the uppermost surface of the trench fill is reduced, thereby facilitating the application and enhancing the accuracy of photolithographic techniques in forming features with minimal dimensions.
摘要翻译：通过在抛光停止层上添加反射率补偿层，在半导体衬底中使用薄的非晶硅或多晶硅抛光停止层形成绝缘沟槽隔离结构。结果，衬底的主表面和沟槽填充物的最上表面之间的拓扑步骤减少，从而有助于在最小尺寸形成特征时光刻技术的应用和提高精度。

5. 发明授权

US5795820A Method for simplifying the manufacture of an interlayer dielectric stack 失效
标题翻译：用于简化层间电介质堆叠的制造的方法
公开(公告)号：US5795820A
公开(公告)日：1998-08-18
申请号：US673005
申请日：1996-07-01
申请人： Nick Kepler
发明人： Nick Kepler
IPC分类号： H01L21/768 , H01L21/441
CPC分类号： H01L21/76801 , H01L21/76834 , H01L21/76895
摘要： A method and apparatus is provided for simplifying the manufacture of an interlayer dielectric where local interconnects are utilized. The invention utilizes a separate LI stack and first contact stack deposition and etch. In the first step, a layer of oxide etch stop and a layer of TEOS oxide are deposited to form a first LI stack. This stack is then contact etched, filled, and polished. A first contact stack is then formed by deposition of a doped silane oxide layer that is contact etched, filled, and polished. The method produces an ILD with a first layer of oxide etch stop, a second layer of undoped TEOS oxide, and a final layer of doped silane oxide.
摘要翻译：提供了一种用于简化使用局部互连的层间电介质的制造的方法和装置。本发明利用单独的LI堆叠和第一接触堆叠沉积和蚀刻。在第一步骤中，沉积一层氧化物蚀刻停止层和一层TEOS氧化物以形成第一个LI堆叠。然后将该叠层接触刻蚀，填充和抛光。然后通过沉积接触蚀刻，填充和抛光的掺杂硅烷氧化物层形成第一接触堆叠。该方法产生具有第一层氧化物蚀刻停止层的第一层，未掺杂的TEOS氧化物层的第二层和掺杂的硅烷氧化物的最终层。

6. 发明授权

US06514844B1 Sidewall treatment for low dielectric constant (low K) materials by ion implantation 失效
标题翻译：通过离子注入对低介电常数（低K）材料进行侧壁处理
公开(公告)号：US06514844B1
公开(公告)日：2003-02-04
申请号：US09840598
申请日：2001-04-23
申请人： Jeremy I. Martin , Eric M. Apelgren , Christian Zistl , Paul R. Besser , Srikantewara Dakshina-Murthy , Jonathan B. Smith , Nick Kepler , Fred Cheung
发明人： Jeremy I. Martin , Eric M. Apelgren , Christian Zistl , Paul R. Besser , Srikantewara Dakshina-Murthy , Jonathan B. Smith , Nick Kepler , Fred Cheung
IPC分类号： H01L2144
CPC分类号： H01L21/76825 , H01L21/31155 , H01L21/76801 , H01L21/76807 , H01L21/7681 , H01L21/76877
摘要： A method is provided, the method comprising forming a first conductive structure, and forming a first dielectric layer above the first conductive structure. The method also comprises densifying a portion of the first dielectric layer above at least a portion of the first conductive structure, and forming a first opening in the densified portion of the first dielectric layer.
摘要翻译：提供了一种方法，该方法包括形成第一导电结构，以及在第一导电结构之上形成第一电介质层。该方法还包括在第一导电结构的至少一部分上方致密化第一电介质层的一部分，以及在第一介电层的致密部分中形成第一开口。

7. 发明授权

US06274511B1 Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of refractory metal layer 有权
$Method of forming junction-leakage free metal silicide in a semiconductor wafer by amorphization of refractory metal layer$
标题翻译：通过难熔金属层的非晶化在半导体晶片中形成结漏电的金属硅化物的方法
公开(公告)号：US06274511B1
公开(公告)日：2001-08-14
申请号：US09256781
申请日：1999-02-24
申请人： Karsten Wieczorek , Nick Kepler , Paul R. Besser
发明人： Karsten Wieczorek , Nick Kepler , Paul R. Besser
IPC分类号： H01L2131
CPC分类号： H01L21/28518
摘要： A method for forming ultra shallow junctions in a semiconductor wafer with reduced junction leakage arising from a silicidation process due to grain boundary induced stress induced junction spiking amorphizes the metal layer prior to annealing during silicidation. After the gate and source/drain junctions are formed in a semiconductor device, dopant or non-dopant material is implanted into the anamorphous metal layer that has been previously deposited over the gate and source/drain junctions. The ion implantation is performed at an energy level sufficient to amorphize the metal (e.g. cobalt), and substantially eliminate grain boundaries in the metal and release grain boundary induced stress. This prevents grain boundary stress induced diffusion of the metal during the first phase of the silicidation process, where the metal is the diffusing species. The silicide regions that are formed during subsequent annealing steps therefore do not exhibit junction spikes.
摘要翻译：在半导体晶片中形成超浅结的方法，其中由于晶界诱发的应力诱导的接合尖峰而导致的由硅化工艺引起的结的漏点在硅化过程中退火之前对金属层进行了非晶化。在半导体器件中形成栅极和源极/漏极结之后，将掺杂剂或非掺杂剂材料注入到先前沉积在栅极和源极/漏极结上的无定形金属层中。离子注入在足以使金属（例如钴）非晶化的能级下进行，并且基本上消除金属中的晶界并释放晶界诱发的应力。这防止在硅化过程的第一阶段期间金属是扩散物质的晶界应力引起的金属扩散。因此，在随后的退火步骤期间形成的硅化物区域不会显示结尖峰。

8. 发明授权

US06238986B1 Formation of junctions by diffusion from a doped film at silicidation 有权
标题翻译：通过硅化物从掺杂膜扩散形成结
公开(公告)号：US06238986B1
公开(公告)日：2001-05-29
申请号：US09187427
申请日：1998-11-06
申请人： Nick Kepler , Karsten Wieczorek , Larry Wang , Paul Raymond Besser
发明人： Nick Kepler , Karsten Wieczorek , Larry Wang , Paul Raymond Besser
IPC分类号： H01L2128
CPC分类号： H01L29/66575 , H01L21/2257 , H01L21/823814 , H01L21/823835 , H01L29/665
摘要： High integrity shallow source/drain junctions are formed employing cobalt silicide contacts. A layer of cobalt and a cap layer of titanium or titanium nitride are deposited on a substrate above intended source/drain regions, followed by silicidation. Embodiments include low-temperature rapid thermal annealing to form a high-resistivity phase cobalt silicide, removing the cap layer, depositing a doped film on the first phase cobalt silicide, and heating, as by high-temperature rapid thermal annealing, to form a low-resistance cobalt silicide during which impurities from the doped film diffuse through the cobalt silicide into the substrate to form source/drain regions having junctions extending into the substrate a constant depth below the cobalt silicide/silicon substrate interface. In another embodiment, impurities are diffused from the doped film to form source/drain regions and self-aligned junctions following formation of the low-resistance phase cobalt silicide. The formation of source/drain junctions self-aligned to the cobalt silicide/silicon substrate interface prevents junction leakage while allowing the formation of cobalt silicide contacts at optimum thickness to avoid parasitic series resistances, thereby facilitating reliable device scaling.
摘要翻译：使用硅化钴接触形成高度完整的浅源极/漏极结。一层钴和钛或氮化钛的覆盖层沉积在预期的源极/漏极区域上的衬底上，随后进行硅化。实施例包括低温快速热退火以形成高电阻率相硅化钴，去除覆盖层，在第一相钴硅化物上沉积掺杂膜，并且通过高温快速热退火加热以形成低电阻的硅化钴，其中来自掺杂膜的杂质通过硅化钴扩散到衬底中以形成具有在硅化钴/硅衬底界面下方延伸到衬底中的连续恒定深度的接合的源/漏区。在另一个实施例中，在形成低电阻相钴硅化物之后，杂质从掺杂膜扩散以形成源/漏区和自对准结。与硅化钴/硅衬底界面自对准的源极/漏极结的形成可防止结合泄漏，同时允许以最佳厚度形成硅化钴触点，以避免寄生串联电阻，从而便于可靠的器件缩放。

9. 发明授权

US06169005A Formation of junctions by diffusion from a doped amorphous silicon film during silicidation 有权
标题翻译：在硅化过程中由掺杂的非晶硅膜扩散形成接合点
公开(公告)号：US06169005A
公开(公告)日：2001-01-02
申请号：US09318824
申请日：1999-05-26
申请人： Nick Kepler , Karsten Wieczorek , Larry Wang , Paul Raymond Besser
发明人： Nick Kepler , Karsten Wieczorek , Larry Wang , Paul Raymond Besser
IPC分类号： H01L21386
CPC分类号： H01L21/28518 , H01L21/2257 , H01L21/76895 , H01L29/665
摘要： High integrity ultra-shallow source/drain junctions are formed employing cobalt silicide contacts. These are formed by depositing a layer of cobalt on a substrate above intended source/drain regions, and depositing a doped amorphous silicon film on the cobalt. Silicidation, as by rapid thermal annealing, is performed to form a low-resistance cobalt suicide while consuming the amorphous silicon film and diffusing impurities from the doped amorphous silicon film through the cobalt silicide into the substrate. The diffusion of the impurities forms shallow junctions extending into the substrate a substantially constant depth below the cobalt silicide/silicon substrate interface. The consumption of the amorphous silicon film during silicidation, which results in less consumption of substrate silicon, and formation of source/drain junctions self-aligned to the cobalt silicide/silicon substrate interface, enables the formation of ultra-shallow source/drain junctions without junction leakage while allowing the formation of cobalt silicide contacts at optimum thickness, thereby facilitating reliable device scaling.
摘要翻译：使用硅化钴接触形成高完整性超浅源极/漏极结。这些是通过在目标源极/漏极区域上的衬底上沉积钴层而在钴上沉积掺杂的非晶硅膜形成的。通过快速热退火进行硅化，以形成低电阻的硅化钴，同时消耗非晶硅膜并将杂质从掺杂的非晶硅膜通过硅化钴扩散到衬底中。杂质的扩散形成延伸到衬底中的浅结，在硅化钴/硅衬底界面下方基本上恒定的深度。在硅化期间，非晶硅膜的消耗导致较少的衬底硅消耗，以及与硅化钴/硅衬底界面自对准的源极/漏极结的形成使得能够形成超浅源极/漏极结而不形成结点泄漏，同时允许以最佳厚度形成钴硅化物触点，从而便于可靠的器件缩放。

10. 发明授权

US6162699A Method for generating limited isolation trench width structures and a device having a narrow isolation trench surrounding its periphery 有权
标题翻译：用于产生有限隔离沟槽宽度结构的方法和具有围绕其周边的窄隔离沟槽的器件
公开(公告)号：US6162699A
公开(公告)日：2000-12-19
申请号：US181561
申请日：1998-10-29
申请人： Larry Wang , Nick Kepler , Olov Karlsson , Basab Bandyopadhyay , Effiong Ibok , Christopher F. Lyons
发明人： Larry Wang , Nick Kepler , Olov Karlsson , Basab Bandyopadhyay , Effiong Ibok , Christopher F. Lyons
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224 , Y10S438/942 , Y10S438/945
摘要： A method for effectively generating limited trench width isolation structures without incurring the susceptibility to dishing problems to produce high quality ICs employs a computer to generate data representing a trench isolation mask capable of being used to etch a limited trench width isolation structure about the perimeter of active region layers, polygate layers, and Local Interconnect (LI) layers. Once the various layers are defined using data on the computer and configured such that chip real estate is maximized, then the boundaries are combined using, for example, logical OR operators to produce data representing an overall composite layer. Once the data representing the composite layer is determined, the data is expanded evenly outward in all horizontal directions by a predetermined amount, .lambda., to produce data representing a preliminary expanded region. Any narrow regions are then merged together with the preliminary expanded region to produce data representing a final expanded region, which is used to produce a mask employed to produce an even width trench about the perimeter of the composite layer. The computer then generates the mask according to the results achieved and the isolation trenches are etched. The resulting isolation trenches prevent short-circuits from occurring between the various electrical devices on the semiconductor device.
摘要翻译：用于有效地产生有限的沟槽宽度隔离结构而不会产生对凹陷问题的敏感性以产生高质量IC的方法使用计算机产生表示沟槽隔离掩模的数据，所述沟槽隔离掩模能够用于围绕有源的周边刻蚀有限的沟槽宽度隔离结构区域层，多晶硅层和局部互连（LI）层。一旦使用计算机上的数据来定义各个层，并且配置为使得芯片空间最大化，则使用例如逻辑OR运算符来组合边界以产生表示整个复合层的数据。一旦确定了表示复合层的数据，则数据在所有水平方向上均匀地向外扩展预定量的λ，以产生表示初步扩展区域的数据。然后将任何窄区域与预扩展区域合并以产生表示最终扩展区域的数据，其用于产生用于围绕复合层的周边产生均匀宽度沟槽的掩模。然后，计算机根据实现的结果生成掩模，并且蚀刻隔离沟槽。所产生的隔离沟槽防止在半导体器件上的各种电器件之间发生短路。

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