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1. 发明申请

US20140079169A1 RESONANT CLOCK AMPLIFIER WITH A DIGITALLY TUNABLE DELAY 有权
标题翻译：具有数字可调延时功能的谐振时钟放大器
公开(公告)号：US20140079169A1
公开(公告)日：2014-03-20
申请号：US14080733
申请日：2013-11-14
申请人： Broadcom Corporation
发明人： Bharath RAGHAVAN , Jun CAO , Afshin MOMTAZ
IPC分类号： H03K5/07 , H04L7/02
CPC分类号： H03K5/07 , H03K2005/00071 , H03K2005/00208 , H03M9/00 , H04L7/0079 , H04L7/02 , H04L7/027 , H04L7/033
摘要： A programmable frequency receiver includes a slicer for receiving data at a first frequency, a de-multiplexer for de-multiplexing the data at a second frequency, a programmable clock generator for generating a clock at the first frequency, and first and second resonant clock amplifiers for amplifying clock signals at the first and second frequencies. The resonant clock amplifiers include an inductor having a low Q value, allowing them to amplify clock signals over the programmable frequency range of the receiver. The second resonant clock amplifier includes digitally tunable delay elements to delay and center the amplified clock signal of the second frequency in the data window at the interface between the slicer and the de-multiplexer. The delay elements can be capacitors. A calibration circuit adjusts capacitive elements within a master clock generator to generate a master clock at the first frequency.
摘要翻译：可编程频率接收机包括用于以第一频率接收数据的分片器，用于以第二频率解复用数据的解复用器，用于产生第一频率的时钟的可编程时钟发生器，以及第一和第二谐振时钟放大器用于在第一和第二频率处放大时钟信号。谐振时钟放大器包括具有低Q值的电感器，允许它们在接收器的可编程频率范围上放大时钟信号。第二谐振时钟放大器包括数字可调谐延迟元件，以在限幅器和解复用器之间的接口处在数据窗口中延迟和居中放大的第二频率的时钟信号。延迟元件可以是电容器。校准电路调整主时钟发生器内的电容元件，以产生第一个频率的主时钟。

2. 发明申请

US20130285727A1 OCTAL CLOCK PHASE INTERPOLATOR ARCHITECTURE 审中-公开
标题翻译：十字钟相位插件架构
公开(公告)号：US20130285727A1
公开(公告)日：2013-10-31
申请号：US13755782
申请日：2013-01-31
申请人： Texas Instruments Incorporated
发明人： Andrew Pickering , Vipul Raithatha , Peter Hunt
IPC分类号： H03K5/15
CPC分类号： H03K5/15 , H03K5/135 , H03K2005/00052 , H03K2005/00208
摘要： The present invention provides an apparatus and method of generating a set of 8 clock signals nominally spaced at equal 45° intervals by phase interpolation from a set of 4 quadrature reference clocks. The scheme is useful for clock generation for data capture in an oversampled clock/data recovery (CDR) system where the frequency of data sampling is twice that of the frequency of reference clock edges.
摘要翻译：本发明提供了一种通过从一组4个正交参考时钟的相位插值产生一组8个时钟信号的装置和方法，该组信号通过相位插值等距45°间隔。该方案对于过采样时钟/数据恢复（CDR）系统中的数据采集的时钟生成是有用的，其中数据采样的频率是参考时钟边沿频率的两倍。

3. 发明申请

US20110204943A1 DELAY CELL AND PHASE LOCKED LOOP USING THE SAME 有权
标题翻译：延迟细胞和相位锁定环使用它
公开(公告)号：US20110204943A1
公开(公告)日：2011-08-25
申请号：US13102938
申请日：2011-05-06
申请人： Taek-Sang SONG , Kyung-Hoon KIM , Dae-Han KWON
发明人： Taek-Sang SONG , Kyung-Hoon KIM , Dae-Han KWON
IPC分类号： H03L7/08
CPC分类号： H03L7/0995 , H03K3/0322 , H03K5/133 , H03K2005/00208 , H03K2005/00234 , H03L2207/06
摘要： A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.
摘要翻译：通过根据PVT的条件控制延迟单元的延迟时间来产生内部时钟的锁相环，从而提高内部时钟的抖动特性。延迟单元包括响应于控制电压控制第一和第二电流的第一电流控制器，以及响应频率范围选择信号控制第一和第二电流的第二电流控制器。锁相环包括用于将参考时钟与反馈时钟进行比较的相位比较器，用于产生对应于相位比较器的输出的控制电压的控制电压发生器和用于产生具有频率的内部时钟的压控振荡器响应于控制电压和一个或多个频率范围控制信号，其中使用内部时钟产生反馈时钟。

4. 发明授权

US07961026B2 Delay cell and phase locked loop using the same 有权
标题翻译：延迟单元和锁相环使用相同
公开(公告)号：US07961026B2
公开(公告)日：2011-06-14
申请号：US12003676
申请日：2007-12-31
申请人： Taek-Sang Song , Kyung-Hoon Kim , Dae-Han Kwon
发明人： Taek-Sang Song , Kyung-Hoon Kim , Dae-Han Kwon
IPC分类号： H03H11/26
CPC分类号： H03L7/0995 , H03K3/0322 , H03K5/133 , H03K2005/00208 , H03K2005/00234 , H03L2207/06
摘要： A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.
摘要翻译：通过根据PVT的条件控制延迟单元的延迟时间来产生内部时钟的锁相环，从而提高内部时钟的抖动特性。延迟单元包括响应于控制电压控制第一和第二电流的第一电流控制器，以及响应频率范围选择信号控制第一和第二电流的第二电流控制器。锁相环包括用于将参考时钟与反馈时钟进行比较的相位比较器，用于产生对应于相位比较器的输出的控制电压的控制电压发生器和用于产生具有频率的内部时钟的压控振荡器响应于控制电压和一个或多个频率范围控制信号，其中使用内部时钟产生反馈时钟。

5. 发明授权

US07865087B2 Bandpass filter circuit, band-elimination filter circuit, infrared signal processing circuit 有权
标题翻译：带通滤波电路，消除滤波电路，红外信号处理电路
公开(公告)号：US07865087B2
公开(公告)日：2011-01-04
申请号：US11929805
申请日：2007-10-30
申请人： Takahiro Inoue
发明人： Takahiro Inoue
IPC分类号： H04B10/06 , H03B1/00
CPC分类号： H03H11/0455 , H03F3/087 , H03F3/45183 , H03F3/45475 , H03F3/45636 , H03F3/45932 , H03F2203/45101 , H03F2203/45138 , H03H11/0433 , H03H11/0472 , H03K3/0231 , H03K3/0322 , H03K2005/00071 , H03K2005/00208
摘要： A bandpass filter circuit 10 of the present invention includes: transconductance amplifier circuits 1 to 3; a common-mode feedback circuit 4 which outputs a first control signal to the transconductance amplifier circuit 1 so that a D.C. voltage level of a differential output of the transconductance amplifier circuit 1 is at a predetermined level; a common-mode feedback circuit 5 which outputs a second control signal to the transconductance amplifier circuit 2 so that a D.C. voltage level of a differential output of the transconductance amplifier circuit 2 is at a predetermined level; and capacitors C1 to C3. Each of the members are connected as shown in FIG. 1. With the configuration, a bandpass filter circuit capable of adjusting constants such as a Q-value is realized.
摘要翻译：本发明的带通滤波器电路10包括：跨导放大器电路1至3; 共模反馈电路4，其向跨导放大器电路1输出第一控制信号，使得跨导放大器电路1的差分输出的直流电压电平处于预定电平; 输出第二控制信号到跨导放大器电路2的共模反馈电路5，使得跨导放大器电路2的差分输出的直流电压电平处于预定电平; 和电容器C1〜C3。每个构件如图1所示连接。通过该结构，实现了能够调整诸如Q值的常数的带通滤波器电路。

6. 发明授权

US07821317B2 Clock generating apparatus 失效
标题翻译：时钟发生装置
公开(公告)号：US07821317B2
公开(公告)日：2010-10-26
申请号：US12137595
申请日：2008-06-12
申请人： Young-chan Jang
发明人： Young-chan Jang
IPC分类号： H03K3/00
CPC分类号： H03K5/133 , G06F1/08 , H03K5/15026 , H03K2005/00052 , H03K2005/00208 , H03L7/0812
摘要： A clock generating apparatus includes a clock generator and a controllable delay line. The clock generator receives an external clock signal and generates multiple clock signals having different phases by delaying the external clock signal. The controllable delay line receives one of the multiple clock signals as a first clock signal and delays the first clock signal by a first interval in response to an externally applied control signal. The delayed first clock signal is input to the clock generator.
摘要翻译：时钟发生装置包括时钟发生器和可控延时线。时钟发生器通过延迟外部时钟信号来接收外部时钟信号并产生具有不同相位的多个时钟信号。可控延迟线接收多个时钟信号中的一个作为第一时钟信号，并且响应于外部施加的控制信号而延迟第一时钟信号第一间隔。延迟的第一时钟信号被输入到时钟发生器。

7. 发明授权

US07705649B1 Duty cycle correction circuit with small duty error and wide frequency range 有权
标题翻译：占空比校正电路，占空比小，频率范围宽
公开(公告)号：US07705649B1
公开(公告)日：2010-04-27
申请号：US12062426
申请日：2008-04-03
申请人： Hao Yu , Sing W. Chin , Bill C. Wong
发明人： Hao Yu , Sing W. Chin , Bill C. Wong
IPC分类号： H03K3/017
CPC分类号： H03K5/1565 , H03K2005/00097 , H03K2005/00208 , H03L7/0812 , H03L7/0891 , H03L7/093
摘要： A duty cycle correction circuit (10) for receiving an input clock signal (11) and generating an output clock signal (13) having a predetermined duty cycle includes a clock trigger circuit (12) generating the output clock signal (13) having a first clock edge triggered from the input clock signal and a second clock edge triggered from a delayed clock signal (22); a charge pump circuit (14) receiving the output clock signal and generating charging and discharging currents for a capacitor (C1) where a control voltage develops on the capacitor indicative of the duty cycle error of the output clock signal; a self-track bias circuit (18) receiving the control voltage and generating first and second bias voltages (23, 24) in response to the control voltage; and a delay-locked loop circuit (20) receiving the output clock signal and the first and second bias voltages and generating the delayed clock signal.
摘要翻译：一种用于接收输入时钟信号（11）并产生具有预定占空比的输出时钟信号（13）的占空比校正电路（10）包括：时钟触发电路（12），产生具有第一从所述输入时钟信号触发时钟沿和从延迟的时钟信号（22）触发的第二时钟沿; 电荷泵电路（14），接收所述输出时钟信号，并且产生电容器（C1）的充电和放电电流，其中在所述电容器上产生控制电压，其指示所述输出时钟信号的占空比误差; 接收所述控制电压并且响应于所述控制电压产生第一和第二偏置电压（23,24）的自磁道偏置电路（18）; 以及延迟锁定环路（20），接收所述输出时钟信号和所述第一和第二偏置电压并产生延迟的时钟信号。

8. 发明申请

US20100060332A1 SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：半导体集成电路
公开(公告)号：US20100060332A1
公开(公告)日：2010-03-11
申请号：US12340912
申请日：2008-12-22
申请人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
发明人： Hee Woong Song , Yong Ju Kim , Sung Woo Han , Ic Su Oh , Hyung Soo Kim , Tae Jin Hwang , Hae Rang Choi , Ji Wang Lee , Jae Min Jang , Chang Kun Park
IPC分类号： H03L7/06
CPC分类号： H03K3/0322 , H03K5/1504 , H03K2005/00208 , H03L7/083 , H03L7/24
摘要： A semiconductor integrated circuit comprises a PLL (Phase Locked Loop (PLL) circuit configured to generate a control voltage in response to a frequency of a reference clock signal, and to generate a PLL clock signal having a frequency that corresponds to a level of the control voltage, and a voltage controlled oscillator configured to oscillate an output clock signal in response to the PLL clock signal, and to allow the PLL clock signal to have a frequency that corresponds to a level of the control voltage.
摘要翻译：半导体集成电路包括PLL（锁相环）电路，其被配置为响应于参考时钟信号的频率产生控制电压，并且产生具有对应于控制电平的频率的PLL时钟信号电压和被配置为响应于PLL时钟信号而振荡输出时钟信号的压控振荡器，并且允许PLL时钟信号具有对应于控制电压电平的频率。

9. 发明授权

US07633351B2 Differential ring oscillator 失效
标题翻译：差分环形振荡器
公开(公告)号：US07633351B2
公开(公告)日：2009-12-15
申请号：US11892444
申请日：2007-08-23
申请人： Kazuhisa Raita , Ichiro Yamane , Yoshitaka Kitao , Toshifumi Hamaguchi , Takahiro Inauchi
发明人： Kazuhisa Raita , Ichiro Yamane , Yoshitaka Kitao , Toshifumi Hamaguchi , Takahiro Inauchi
IPC分类号： H03B5/24 , H03K3/03 , H03L1/00 , H03L1/02 , H03L7/08
CPC分类号： H03K3/0322 , H03K5/133 , H03K2005/00058 , H03K2005/00208 , H03L1/00 , H03L7/0995
摘要： A differential amplifier circuit includes: a differential transistor pair composed of first and second transistors; a first resistance connected to a junction point of the first and second transistors at one terminal and to a first voltage node at the other terminal; second and third resistances provided between the first and second transistors, respectively, and a second voltage node; and first and second passive circuits respectively connected to the second and third resistances, the load characteristics of the passive circuits changing according to a control signal supplied. A ring oscillator is composed of a plurality of such differential amplifier circuits connected in a loop.
摘要翻译：差分放大电路包括：由第一和第二晶体管组成的差分晶体管对; 连接到一个端子处的第一和第二晶体管的连接点的第一电阻和另一个端子处的第一电压节点的第一电阻; 分别设置在第一和第二晶体管之间的第二和第三电阻和第二电压节点; 以及分别连接到第二和第三电阻的第一和第二无源电路，无源电路的负载特性根据提供的控制信号而变化。环形振荡器由以循环连接的多个这样的差分放大器电路组成。

10. 发明申请

US20090185413A1 SEMICONDUCTOR DEVICE HAVING INPUT CIRCUIT WITH OUTPUT PATH CONTROL UNIT 失效
标题翻译：具有输出路径控制单元的输入电路的半导体器件
公开(公告)号：US20090185413A1
公开(公告)日：2009-07-23
申请号：US12136878
申请日：2008-06-11
申请人： Mi Hye KIM , Jae Jin LEE
发明人： Mi Hye KIM , Jae Jin LEE
IPC分类号： H03K5/12 , G11C11/34
CPC分类号： G11C5/147 , G11C5/143 , G11C7/1078 , G11C7/1084 , H03K19/00384 , H03K2005/0013 , H03K2005/00208
摘要： A semiconductor device minimizes generation of an output signal skew of an input buffer and thus stabilizes the operation of the semiconductor device. The semiconductor integrated circuit includes an input potential detection unit outputting a detection signal in response to a level of an input signal, an input buffer buffering the input signal, and an output path control unit that receives the output signal of the input buffer and the detection signal of the input potential detection unit and outputs an output driving signal in response to the level of the detection signal.
摘要翻译：半导体器件最小化输入缓冲器的输出信号偏斜的产生，从而稳定半导体器件的操作。半导体集成电路包括输入电位检测单元，其响应于输入信号的电平，缓冲输入信号的输入缓冲器和接收输入缓冲器的输出信号和检测的输出路径控制单元输出检测信号信号，并且响应于检测信号的电平而输出输出驱动信号。

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