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1. 发明申请

US20130162311A1 FILTERING CIRCUIT, PHASE IDENTITY DETERMINATION CIRCUIT AND DELAY LOCKED LOOP 有权
标题翻译：滤波电路，相位识别电路和延时锁定环
公开(公告)号：US20130162311A1
公开(公告)日：2013-06-27
申请号：US13607234
申请日：2012-09-07
申请人： Dae-Han KWON , Yong-Ju Kim , Taek-Sang Song
发明人： Dae-Han KWON , Yong-Ju Kim , Taek-Sang Song
IPC分类号： H03L7/06 , H03K5/00
CPC分类号： H03L7/093 , H03L7/0812 , H03L7/235
摘要： A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.
摘要翻译：滤波电路包括时钟选择单元，其被配置为响应于频率信号将具有低于第一时钟的频率的第一时钟或第二时钟作为工作时钟传送;以及滤波器，被配置为滤波输入信号并生成滤波的信号与操作时钟同步。

2. 发明申请

US20130070512A1 NON-VOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件
公开(公告)号：US20130070512A1
公开(公告)日：2013-03-21
申请号：US13340074
申请日：2011-12-29
申请人： Hyuck-Sang Yim , Kwang-Seok Kim , Taek-Sang Song , Chul-Hyun Park
发明人： Hyuck-Sang Yim , Kwang-Seok Kim , Taek-Sang Song , Chul-Hyun Park
IPC分类号： G11C11/00
CPC分类号： G11C5/147 , G11C13/0004 , G11C13/004 , G11C2013/0054
摘要： A non-volatile memory device includes a memory cell including a resistance variable device and a switching unit for controlling a current flowing through the resistance variable device; a read reference voltage generator configured to generate a reference voltage according to a skew occurring in the switching unit; and a sense amplifier configured to sense a voltage corresponding to the current that flows through the resistance variable device based on the reference voltage.
摘要翻译：非易失性存储器件包括：存储单元，包括电阻可变器件和用于控制流过电阻可变器件的电流的开关单元; 读取参考电压发生器，被配置为根据在所述开关单元中发生的偏斜产生参考电压; 以及感测放大器，被配置为基于所述参考电压来感测对应于流过所述电阻可变器件的电流的电压。

3. 发明申请

US20120262323A1 BUFFER CONTROL CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME 有权
标题翻译：缓冲器控制电路和集成电路，包括它们
公开(公告)号：US20120262323A1
公开(公告)日：2012-10-18
申请号：US13333983
申请日：2011-12-21
申请人： Taek-Sang SONG , Dae-Han Kwon
发明人： Taek-Sang SONG , Dae-Han Kwon
IPC分类号： H04L17/02
CPC分类号： H03K5/2481 , H03K19/0027 , H03K19/0948
摘要： A buffer control circuit includes a current supply unit configured to supply current and adjust the current in response to codes, an amplifying buffer configured to operate using the current and output a value obtained by comparing a reference potential and the reference potential, a second buffer configured to buffer an output of the first buffer, and a code generation unit configured to generate the codes in response to an output of the second buffer.
摘要翻译：缓冲器控制电路包括：电流供给单元，被配置为响应于代码提供电流并调节电流;放大缓冲器，被配置为使用电流进行操作并输出通过比较参考电位和参考电位获得的值;配置的第二缓冲器以缓冲第一缓冲器的输出;以及代码生成单元，被配置为响应于第二缓冲器的输出而生成代码。

4. 发明申请

US20120250402A1 SEMICONDUCTOR MEMORY APPARATUS 有权
标题翻译：半导体存储器
公开(公告)号：US20120250402A1
公开(公告)日：2012-10-04
申请号：US13340755
申请日：2011-12-30
申请人： Taek Sang SONG , Dae Han KWON
发明人： Taek Sang SONG , Dae Han KWON
IPC分类号： G11C11/00
CPC分类号： G11C11/00 , G11C7/14 , G11C13/0004 , G11C13/004 , G11C2013/0045 , G11C2013/0054
摘要： A semiconductor memory apparatus includes a resistive memory cell; a data sensing unit configured to sense an output voltage, formed by a sensing current supplied to the resistive memory cell, based on a reference voltage, and output data having a value corresponding to the sensing result; and a reference voltage generation unit comprising a dummy memory cell including first and second resistors having first and second resistance values, respectively, and configured to output a voltage formed by the sensing current supplied to the dummy memory cell as the reference voltage.
摘要翻译：半导体存储装置包括电阻式存储单元; 数据感测单元，被配置为基于参考电压感测由提供给所述电阻性存储单元的感测电流形成的输出电压，以及输出具有与所述感测结果对应的值的数据; 以及参考电压产生单元，包括分别包括具有第一和第二电阻值的第一和第二电阻器的虚拟存储单元，并且被配置为输出由提供给虚拟存储单元的感测电流形成的电压作为参考电压。

5. 发明授权

US08253465B2 Semiconductor memory device and method for operating the same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US08253465B2
公开(公告)日：2012-08-28
申请号：US13186366
申请日：2011-07-19
申请人： Dae-Kun Yoon , Dae-Han Kwon , Taek-Sang Song
发明人： Dae-Kun Yoon , Dae-Han Kwon , Taek-Sang Song
IPC分类号： H03K3/00 , H03K5/13 , H03H11/16
CPC分类号： G11C7/22 , G11C7/1066 , G11C7/1072 , G11C7/222 , H03L7/0814
摘要： A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.
摘要翻译：半导体存储器件包括边缘检测器，被配置为接收两对互补时钟以检测时钟的边沿;比较器，被配置为比较边缘检测器的输出信号，以检测同一对的时钟是否具有180度的相位差;以及检测不同对的时钟是否具有90度的相位差，控制信号发生器被配置为根据比较器的输出信号产生用于控制时钟相位的控制信号;以及相位校正器，被配置为校正时钟的相位响应于控制信号。

6. 发明申请

US20110204943A1 DELAY CELL AND PHASE LOCKED LOOP USING THE SAME 有权
标题翻译：延迟细胞和相位锁定环使用它
公开(公告)号：US20110204943A1
公开(公告)日：2011-08-25
申请号：US13102938
申请日：2011-05-06
申请人： Taek-Sang SONG , Kyung-Hoon KIM , Dae-Han KWON
发明人： Taek-Sang SONG , Kyung-Hoon KIM , Dae-Han KWON
IPC分类号： H03L7/08
CPC分类号： H03L7/0995 , H03K3/0322 , H03K5/133 , H03K2005/00208 , H03K2005/00234 , H03L2207/06
摘要： A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.
摘要翻译：通过根据PVT的条件控制延迟单元的延迟时间来产生内部时钟的锁相环，从而提高内部时钟的抖动特性。延迟单元包括响应于控制电压控制第一和第二电流的第一电流控制器，以及响应频率范围选择信号控制第一和第二电流的第二电流控制器。锁相环包括用于将参考时钟与反馈时钟进行比较的相位比较器，用于产生对应于相位比较器的输出的控制电压的控制电压发生器和用于产生具有频率的内部时钟的压控振荡器响应于控制电压和一个或多个频率范围控制信号，其中使用内部时钟产生反馈时钟。

7. 发明授权

US07986161B2 Termination resistance circuit 有权
标题翻译：端接电阻电路
公开(公告)号：US07986161B2
公开(公告)日：2011-07-26
申请号：US12327294
申请日：2008-12-03
申请人： Jun-Woo Lee , Dae-Han Kwon , Taek-Sang Song
发明人： Jun-Woo Lee , Dae-Han Kwon , Taek-Sang Song
IPC分类号： H03K17/16
CPC分类号： H03K19/018585 , H04L25/0298
摘要： A termination resistance circuit includes a control signal generator for generating a control signal whose logical value changes when a calibration code has a predetermined value, a plurality of parallel resistors which are respectively turned on/off in response to the calibration code, and a resistance value changing unit for changing the total resistance value of the termination resistance circuit in response to the control signal.
摘要翻译：终端电阻电路包括控制信号发生器，用于产生当校准码具有预定值时其逻辑值改变的控制信号，响应于校准码分别导通/关断的多个并联电阻器，以及电阻值改变单元，用于响应于控制信号改变终端电阻电路的总电阻值。

8. 发明授权

US07961026B2 Delay cell and phase locked loop using the same 有权
标题翻译：延迟单元和锁相环使用相同
公开(公告)号：US07961026B2
公开(公告)日：2011-06-14
申请号：US12003676
申请日：2007-12-31
申请人： Taek-Sang Song , Kyung-Hoon Kim , Dae-Han Kwon
发明人： Taek-Sang Song , Kyung-Hoon Kim , Dae-Han Kwon
IPC分类号： H03H11/26
CPC分类号： H03L7/0995 , H03K3/0322 , H03K5/133 , H03K2005/00208 , H03K2005/00234 , H03L2207/06
摘要： A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.
摘要翻译：通过根据PVT的条件控制延迟单元的延迟时间来产生内部时钟的锁相环，从而提高内部时钟的抖动特性。延迟单元包括响应于控制电压控制第一和第二电流的第一电流控制器，以及响应频率范围选择信号控制第一和第二电流的第二电流控制器。锁相环包括用于将参考时钟与反馈时钟进行比较的相位比较器，用于产生对应于相位比较器的输出的控制电压的控制电压发生器和用于产生具有频率的内部时钟的压控振荡器响应于控制电压和一个或多个频率范围控制信号，其中使用内部时钟产生反馈时钟。

9. 发明申请

US20110121860A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20110121860A1
公开(公告)日：2011-05-26
申请号：US12648477
申请日：2009-12-29
申请人： Taek-Sang SONG , Dae-Han Kwon , Jun-Woo Lee
发明人： Taek-Sang SONG , Dae-Han Kwon , Jun-Woo Lee
IPC分类号： H03K19/0175 , H03K19/094
CPC分类号： H03K19/017509 , H03K19/018514 , H03K19/018528
摘要： A semiconductor device includes a swing level shifting unit configured to use a first power supply voltage as a power supply voltage, receive a CML clock swinging around a first voltage level, and shift a swing reference voltage level of the CML clock to a second voltage level lower than the first voltage level, and a CML clock transfer buffering unit configured to use a second power supply voltage as a power supply voltage and buffer the CML clock, which is transferred from the swing level shifting unit and swings around the second voltage level.
摘要翻译：一种半导体器件包括：摆动电平移位单元，被配置为使用第一电源电压作为电源电压，接收围绕第一电压电平摆动的CML时钟，并将CML时钟的摆幅参考电压电平移位到第二电压电平低于第一电压电平的CML时钟传送缓冲单元，以及CML时钟传送缓冲单元，被配置为使用第二电源电压作为电源电压，并缓冲从摆动电平移位单元传送的CML时钟，并围绕第二电压电平摆动。

10. 发明授权

US07929358B2 Data output circuit 有权
标题翻译：数据输出电路
公开(公告)号：US07929358B2
公开(公告)日：2011-04-19
申请号：US12327397
申请日：2008-12-03
申请人： Jun-Woo Lee , Dae-Han Kwon , Taek-Sang Song
发明人： Jun-Woo Lee , Dae-Han Kwon , Taek-Sang Song
IPC分类号： G11C7/10
CPC分类号： G11C7/02 , G11C7/1006 , G11C7/1051 , G11C7/1066 , G11C7/22 , G11C8/18 , G11C11/4076 , G11C11/4096 , G11C2207/107
摘要： A data output circuit includes a serial data output unit for outputting a plurality of parallel data as serial data according to an operation mode, an internal information output unit for outputting internal information data according to the operation mode, and a buffering unit for receiving the serial data and the internal information data through an identical input end and buffering the received data.
摘要翻译：数据输出电路包括：串行数据输出单元，用于根据操作模式输出多个并行数据作为串行数据;内部信息输出单元，用于根据操作模式输出内部信息数据;以及缓冲单元，用于接收串行数据数据和内部信息数据通过相同的输入端并缓冲接收到的数据。

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