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1. 发明申请

US20170038610A1 POCKELS CELL DRIVER CIRCUIT COMPRISING RESISTIVE, INDUCTIVE OR CAPACITIVE ELEMENTS 有权
标题翻译：包含电阻，电感或电容元件的电池驱动电路
公开(公告)号：US20170038610A1
公开(公告)日：2017-02-09
申请号：US15229701
申请日：2016-08-05
申请人： BME Messgeräte Entwicklung KG , Helmholz-Zentrum Dresden-Rossendorf e. V.
发明人： Thorald Horst Bergmann , Fedor Bergmann , Mathias Siebold , Markus Löser
IPC分类号： G02F1/03 , H01S3/10 , H01S3/16 , H01S3/107
CPC分类号： G02F1/0327 , G02F1/03 , H01S3/10038 , H01S3/10061 , H01S3/107 , H01S3/1618 , H01S3/1643 , H01S3/235 , H03K5/07
摘要： The driver circuit comprises a first node (J1), which is connected to a first terminal of the Pockels cell (CP), a second node (J2), which is connected to a second terminal of the Pockels cell (CP), wherein the first node (J1) is connected to a first potential (+HV) via a first switching unit (S1) and the second node (J2) is connected to the first potential (+HV) via a second switching unit (S2) and wherein the first node (J1) is connected to a second potential (−HV) via a first resistance (R1) and the second node (J2) is connected to the second potential (−HV) via a second resistance (R2); and wherein the first node (J1) is connected to the second node (J2) via a series circuit comprising a third resistance (R3) and an inductance (L1).
摘要翻译：驱动器电路包括连接到普克尔斯单元（CP）的第一端子的第一节点（J1），连接到普克尔斯单元（CP）的第二端子的第二节点（J2），其中，第一节点（J1）经由第一开关单元（S1）连接到第一电位（+ HV），并且第二节点（J2）经由第二开关单元（S2）连接到第一电位（+ HV），并且其中第一节点（J1）经由第一电阻（R1）连接到第二电位（-HV），并且第二节点（J2）经由第二电阻（R2）连接到第二电位（-HV）; 并且其中所述第一节点（J1）经由包括第三电阻（R3）和电感（L1）的串联电路连接到所述第二节点（J2）。

2. 发明申请

US20170033785A1 ISOLATED OUTPUT SWITCHING CIRCUIT 有权
标题翻译：隔离输出开关电路
公开(公告)号：US20170033785A1
公开(公告)日：2017-02-02
申请号：US15180775
申请日：2016-06-13
申请人： TEXAS INSTRUMENTS INCORPORATED
发明人： TRI C. NGUYEN , MD. ABIDUR RAHMAN , DAVID J. BALDWIN
IPC分类号： H03K17/16 , H03K5/08 , H01L29/06 , H03K5/07 , H03K17/284 , H01L27/092
CPC分类号： H03K17/162 , H01L27/0928 , H03K5/07 , H03K5/08 , H03K17/163 , H03K17/284 , H03K2017/066
摘要： A semiconductor device includes an output switching device having an input node, an output node, and a control input node. The control input node enables an input voltage applied to the input node to be switched to the output node. A gate pull-down circuit controls the control input node of the output switching device in response to at least one control signal. The gate pull-down circuit activates the output switching device by raising the voltage level of the control input node above the voltage level of the output node and deactivates the output switching device by clamping the control input node to the voltage level of the output node. A gate pull-up circuit receives an enable signal and generates the at least one control signal to the gate pull-down circuit in response to the enable signal.
摘要翻译：半导体器件包括具有输入节点，输出节点和控制输入节点的输出开关器件。控制输入节点使得施加到输入节点的输入电压被切换到输出节点。门下拉电路响应于至少一个控制信号控制输出开关装置的控制输入节点。栅极下拉电路通过将控制输入节点的电压电平提高到输出节点的电压电平来激活输出开关装置，并且通过将控制输入节点钳位到输出节点的电压电平而使输出开关装置去激活。栅极上拉电路接收使能信号，并且响应于使能信号而将至少一个控制信号产生到栅极下拉电路。

3. 发明申请

US20140079169A1 RESONANT CLOCK AMPLIFIER WITH A DIGITALLY TUNABLE DELAY 有权
标题翻译：具有数字可调延时功能的谐振时钟放大器
公开(公告)号：US20140079169A1
公开(公告)日：2014-03-20
申请号：US14080733
申请日：2013-11-14
申请人： Broadcom Corporation
发明人： Bharath RAGHAVAN , Jun CAO , Afshin MOMTAZ
IPC分类号： H03K5/07 , H04L7/02
CPC分类号： H03K5/07 , H03K2005/00071 , H03K2005/00208 , H03M9/00 , H04L7/0079 , H04L7/02 , H04L7/027 , H04L7/033
摘要： A programmable frequency receiver includes a slicer for receiving data at a first frequency, a de-multiplexer for de-multiplexing the data at a second frequency, a programmable clock generator for generating a clock at the first frequency, and first and second resonant clock amplifiers for amplifying clock signals at the first and second frequencies. The resonant clock amplifiers include an inductor having a low Q value, allowing them to amplify clock signals over the programmable frequency range of the receiver. The second resonant clock amplifier includes digitally tunable delay elements to delay and center the amplified clock signal of the second frequency in the data window at the interface between the slicer and the de-multiplexer. The delay elements can be capacitors. A calibration circuit adjusts capacitive elements within a master clock generator to generate a master clock at the first frequency.
摘要翻译：可编程频率接收机包括用于以第一频率接收数据的分片器，用于以第二频率解复用数据的解复用器，用于产生第一频率的时钟的可编程时钟发生器，以及第一和第二谐振时钟放大器用于在第一和第二频率处放大时钟信号。谐振时钟放大器包括具有低Q值的电感器，允许它们在接收器的可编程频率范围上放大时钟信号。第二谐振时钟放大器包括数字可调谐延迟元件，以在限幅器和解复用器之间的接口处在数据窗口中延迟和居中放大的第二频率的时钟信号。延迟元件可以是电容器。校准电路调整主时钟发生器内的电容元件，以产生第一个频率的主时钟。

4. 发明授权

US08115343B2 Nanosecond pulse generator 失效
标题翻译：纳秒脉冲发生器
公开(公告)号：US08115343B2
公开(公告)日：2012-02-14
申请号：US12471229
申请日：2009-05-22
申请人： Jason Sanders , Andras Kuthi , Martin A. Gundersen , William Henry Moore
发明人： Jason Sanders , Andras Kuthi , Martin A. Gundersen , William Henry Moore
IPC分类号： H03K3/00
CPC分类号： H03K5/12 , C12M35/02 , H03K3/57 , H03K5/07 , H03K17/74
摘要： This invention relates to a pulse generator circuit for delivering a short high current pulse to a load. This pulse generator comprises a junction recovery diode, a switch, a first resonant circuit and a second resonant circuit. The diode may be configured to store charges in its depletion layer when there is a forward flow of a current and to rapidly switch open after the depletion layer is discharged by a reverse flow of a current. After the diode rapidly switch opens, the pulse generator may provide a reverse current to the load. This pulse generator may be configured to generate at least one pulse that is having a length of no more than 100 nanoseconds at the full-width-at-half-maximum and an amplitude of at least 1 kilovolt. Electrodes may be connected to the pulse generator to deliver one pulse or plurality of pulses to biological cells such as tumor cells.
摘要翻译：本发明涉及用于将短的高电流脉冲传送到负载的脉冲发生器电路。该脉冲发生器包括结恢复二极管，开关，第一谐振电路和第二谐振电路。二极管可以被配置为当存在电流的正向流时在其耗尽层中存储电荷，并且在耗尽层被电流的反向流放电之后快速地切换开路。二极管快速开关打开后，脉冲发生器可能会向负载提供反向电流。该脉冲发生器可以被配置为产生至少一个脉冲，该脉冲具有在全宽度最大值和至少1千伏的幅度下不超过100纳秒的长度。电极可以连接到脉冲发生器以将一个脉冲或多个脉冲递送到诸如肿瘤细胞的生物细胞。

5. 发明申请

US20100038971A1 NANOSECOND PULSE GENERATOR 失效
标题翻译： NANOSECOND脉冲发生器
公开(公告)号：US20100038971A1
公开(公告)日：2010-02-18
申请号：US12471229
申请日：2009-05-22
申请人： Jason Sanders , Andras Kuthi , Martin A. Gundersen , William Henry Moore
发明人： Jason Sanders , Andras Kuthi , Martin A. Gundersen , William Henry Moore
IPC分类号： H03K3/02
CPC分类号： H03K5/12 , C12M35/02 , H03K3/57 , H03K5/07 , H03K17/74
摘要： This invention relates to a pulse generator circuit for delivering a short high current pulse to a load. This pulse generator comprises a junction recovery diode, a switch, a first resonant circuit and a second resonant circuit. The diode may be configured to store charges in its depletion layer when there is a forward flow of a current and to rapidly switch open after the depletion layer is discharged by a reverse flow of a current. After the diode rapidly switch opens, the pulse generator may provide a reverse current to the load. This pulse generator may be configured to generate at least one pulse that is having a length of no more than 100 nanoseconds at the full-width-at-half-maximum and an amplitude of at least 1 kilovolt. Electrodes may be connected to the pulse generator to deliver one pulse or plurality of pulses to biological cells such as tumor cells.
摘要翻译：本发明涉及用于将短的高电流脉冲传送到负载的脉冲发生器电路。该脉冲发生器包括结恢复二极管，开关，第一谐振电路和第二谐振电路。二极管可以被配置为当存在电流的正向流时在其耗尽层中存储电荷，并且在耗尽层被电流的反向流放电之后快速地切换开路。二极管快速开关打开后，脉冲发生器可能会向负载提供反向电流。该脉冲发生器可以被配置为产生至少一个脉冲，该脉冲具有在全宽度在半最大值和至少1千伏的振幅下不超过100纳秒的长度。电极可以连接到脉冲发生器以将一个脉冲或多个脉冲递送到诸如肿瘤细胞的生物细胞。

6. 发明申请

US20090021309A1 Fully Integrated Ultra Wideband Transmitter Circuits and Systems 失效
标题翻译：全集成超宽带发射机电路和系统
公开(公告)号：US20090021309A1
公开(公告)日：2009-01-22
申请号：US11813047
申请日：2004-12-30
申请人： Yuan Jin Zheng
发明人： Yuan Jin Zheng
IPC分类号： H03F3/16 , H03K3/353
CPC分类号： H03K5/07 , H04B1/7172 , H04B1/7174
摘要： Disclosed is a novel design of a fully integrated UWB transmitter. The transmitter includes a pulse generator, a pulse modulator, and an ultra-wideband drive amplifier. A new low voltage low power pulse generator circuit is disclosed which can be fully integrated in CMOS or BiCMOS process. This circuit includes a squaring stage, an exponential stage, and a second-order derivative stage. Based on this, PPM, BPSK and PAM pulse modulator circuits and system are disclosed. The modulated pulse is symmetrical second-order derivative Gaussian pulses with a bandwidth up to 5 GHz and having sufficient swing for UWB applications. An ultra-wideband driver amplifier is proposed to amplify the modulator output and drive the antenna. For the driver amplifier, common source resistor and inductor shunt feedback with current reuse technique is employed to achieve the ultra-wideband bandwidth, high gain, and providing matching for the antenna simultaneously.
摘要翻译：公开了一种完全集成的UWB发射机的新颖设计。发射机包括脉冲发生器，脉冲调制器和超宽带驱动放大器。公开了一种新的低压低功率脉冲发生器电路，其可以完全集成在CMOS或BiCMOS工艺中。该电路包括平方级，指数级和二级微分级。基于此，公开了PPM，BPSK和PAM脉冲调制器电路和系统。调制脉冲是带宽高达5GHz的对称二阶导数高斯脉冲，并且对于UWB应用具有足够的摆幅。提出了一种超宽带驱动放大器来放大调制器输出并驱动天线。对于驱动放大器，采用电流复用技术的公共源电阻和电感分流反馈，实现超宽带宽，高增益，同时提供天线匹配。

7. 发明授权

US4345165A Methods and circuitry for varying a pulse output of a resonant circuit 失效
标题翻译：用于改变谐振电路的脉冲输出的方法和电路
公开(公告)号：US4345165A
公开(公告)日：1982-08-17
申请号：US189404
申请日：1980-09-22
申请人： Leo L. Radke
发明人： Leo L. Radke
IPC分类号： H03K5/07
CPC分类号： H03K5/07
摘要： A pulse generating circuit includes a first trigger circuit including a resistor (43) and transistors (34 and 42) for applying a current pulse to a resonant circuit (capacitor 31-inductor 32) to produce a sinusoidal output pulse having a predetermined width and amplitude, and a second trigger circuit including a resistor (64) and transistors (34 and 67) for applying current to a resonant circuit (capacitors 31 and 33-inductor 32) to produce a sinusoidal output pulse having a second predetermined width. In another embodiment, an inductor (76) contained in a resonant circuit (inductor 76-capacitor 77) is magnetically coupled to the base of a transistor (79) contained in an operate circuit. By selectively connecting various capacitors (99 and 112) and resistors (91 and 114) into the resonant and operate circuits, the overall circuit functions to produce output signals at a first frequency and amplitude and at a second frequency and amplitude or at a third frequency and amplitude when both sets of capacitors and resistors are simultaneously connected.
摘要翻译：脉冲发生电路包括：第一触发电路，包括用于向谐振电路（电容器31-电感器32）施加电流脉冲以产生具有预定宽度和幅度的正弦输出脉冲的电阻器（43）和晶体管（34和42）以及包括用于向谐振电路（电容器31和33-电感器32）施加电流以产生具有第二预定宽度的正弦输出脉冲的电阻器（64）和晶体管（34和67）的第二触发电路。在另一个实施例中，包含在谐振电路（电感器76-电容器77）中的电感器76被磁耦合到包含在操作电路中的晶体管79的基极。通过将各种电容器（99和112）和电阻器（91和114）选择性地连接到谐振和操作电路中，总电路用于以第一频率和幅度以及第二频率和振幅或第三频率产生输出信号当两组电容器和电阻器同时连接时的振幅。

8. 发明授权

US3411096A Electrical storage networks 失效
标题翻译：电力存储网络
公开(公告)号：US3411096A
公开(公告)日：1968-11-12
申请号：US38913164
申请日：1964-08-12
申请人： MARCONI CO LTD , STANDARD TELEPHONES CABLES LTD
发明人： PETER RAINGER , ARTHUR HUNT GEORGE
IPC分类号： G11C27/02 , H03K5/00 , H03K5/05 , H03K5/07 , H03K5/135 , H04J3/20 , H04N7/01
CPC分类号： H03K5/07 , G11C27/02 , H03K5/00 , H03K5/05 , H03K5/135 , H04J3/20 , H04N7/01

9. 发明授权

US3163777A Driver circuit employing charged tuned load for converting voltage level changes to current pulses 失效
标题翻译：驱动电路采用充电调谐负载，将电压电平变化转换为电流脉冲
公开(公告)号：US3163777A
公开(公告)日：1964-12-29
申请号：US13384461
申请日：1961-08-25
申请人： BUNKER RAMO
发明人： CORBELL RAYMOND C , MELLOTT ROBERT N
IPC分类号： H03K3/45 , H03K5/07
CPC分类号： H03K3/45 , H03K5/07

10. 发明授权

US2968766A Pulse-sharpening circuit 失效
标题翻译：脉冲锐化电路
公开(公告)号：US2968766A
公开(公告)日：1961-01-17
申请号：US61947556
申请日：1956-10-31
申请人： BLONDER TONGUE LAB
发明人： IRVING HOROWITZ
IPC分类号： H03K5/07 , H04N5/208
CPC分类号： H03K5/07 , H04N5/208

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