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1. 发明申请

US20040259280A1 Solid-state image pickup device and fabrication method thereof 有权
标题翻译：固态摄像装置及其制造方法
公开(公告)号：US20040259280A1
公开(公告)日：2004-12-23
申请号：US10889157
申请日：2004-07-12
申请人： Sony Corporation
发明人： Junji Yamane , Kunihiko Hikichi
IPC分类号： H01L021/00
CPC分类号： H01L29/76891 , H01L27/14683 , H01L27/14812 , H01L27/14831 , H01L27/14843 , H01L29/66946 , H01L29/76866
摘要： A method of fabricating a solid-state image pickup device comprising forming mask patterns corresponding to patterns of first and third transfer electrodes, which are to be alternately arranged in each vertical transfer register formation region and which are to extend in parallel to each other between light receiving portions adjacent to each other in the vertical direction, on a first electrode material layer. The method also includes forming side walls on each of the mask patterns. The method further includes patterning the first electrode material layer via the mask patterns having the side walls, to form first and third transfer electrodes formed by the first layer. The method yet further includes forming second transfer electrodes by a second electrode material layer via an insulating film in such a manner that each of said second transfer electrodes is disposed between the first and third transfer electrodes of the first layer in said vertical transfer register formation region and between the light receiving portions. The method still further includes forming fourth transfer electrodes by a third electrode material layer via an insulating film in such a manner that each of the fourth transfer electrodes is between the third and first transfer electrodes of the first layer in the vertical transfer register formation region and between the light receiving portions.
摘要翻译：一种制造固态图像拾取装置的方法，包括形成对应于第一和第三转印电极的图案的掩模图案，所述掩模图案将交替布置在每个垂直传送寄存器形成区域中并且在光之间彼此平行延伸在第一电极材料层上在垂直方向上彼此相邻的接收部分。该方法还包括在每个掩模图案上形成侧壁。该方法还包括通过具有侧壁的掩模图案来图案化第一电极材料层，以形成由第一层形成的第一和第三转移电极。该方法还包括通过绝缘膜通过第二电极材料层形成第二转移电极，使得所述第二转移电极中的每一个设置在所述垂直转移寄存器形成区域中的第一层的第一和第三转移电极之间并且在光接收部分之间。该方法还包括通过绝缘膜通过第三电极材料层形成第四转移电极，使得第四转移电极中的每一个在垂直转移寄存器形成区域中位于第一层的第三和第一转移电极之间，以及在光接收部分之间。

2. 发明授权

US5043293A Dual oxide channel stop for semiconductor devices 失效
标题翻译：半导体器件的双重氧化物通道阻挡
公开(公告)号：US5043293A
公开(公告)日：1991-08-27
申请号：US532153
申请日：1990-06-01
申请人： Michael A. Kinch , Arturo Simmons
发明人： Michael A. Kinch , Arturo Simmons
IPC分类号： H01L21/441 , H01L21/471 , H01L21/473 , H01L29/06 , H01L29/768
CPC分类号： H01L21/441 , H01L21/471 , H01L21/473 , H01L29/0638 , H01L29/76866 , Y10S438/91
摘要： The disclosure relates to oxide-semiconductor interfaces which are grown with varying amounts of fixed positive (or negative) charge. The invention utilizes these different values to form a channel stop for a charge transfer device. For HgCdTe two different oxides are used, namely, those produced by wet anodization (having large values of fixed positive charge) and plasma oxidation (having low values of fixed charge). The voltage range of operation of the active gate is determined by the difference in fixed positive charge for these regions and the insulator thicknesses.
摘要翻译：本公开涉及以不同量的固定正（或负）电荷生长的氧化物半导体界面。本发明利用这些不同的值来形成用于电荷转移装置的通道停止。对于HgCdTe，使用两种不同的氧化物，即通过湿阳极氧化（具有大的固定正电荷值）和等离子体氧化（具有低固定电荷值）产生的氧化物。有源栅极的工作电压范围由这些区域的固定正电荷差和绝缘体厚度决定。

3. 发明授权

US5015876A High speed charge-coupled sampler and rate reduction circuit 失效
标题翻译：高速电荷耦合采样器和速率降低电路
公开(公告)号：US5015876A
公开(公告)日：1991-05-14
申请号：US375238
申请日：1989-06-30
申请人： Knud L. Knudsen
发明人： Knud L. Knudsen
IPC分类号： H01L29/762 , G11C19/28 , G11C27/04 , H01L21/339 , H01L27/105 , H01L29/768
CPC分类号： G11C19/285 , G11C27/04 , H01L27/1057 , H01L29/76866
摘要： A high speed charge-coupled sampler and rate reduction circuit is disclosed. The present invention allows measurement of high frequency input signals while reducing actual data rates for a series of accurately interleaved sampler data streams. The charge-coupled sampler includes a source means for providing a steady supply of charge and a sampling gate means adjacent to the source means for dividing the charge stream into discrete charge packets separated uniformly in time. An input gate means, adjacent to the sampling gate means, modulates the discrete charge packets, such that size of each charge packet is directly proportional to the instantaneous voltage applied to the input gate means. A plurality of sequential charge output means in turn surround and are adjacent to the input signal gate means. Each sequential charge output means comprises a transfer gate and a storage gate for transferring and storing the charge packet modulated by the input gate means. Once a charge packet is stored by storage gate, it is available for further processing as part of that particular data stream. By interleaving the data streams from all sequential charge output means, the original input signal may be reconstructed. The high speed charge-coupled sampler and rate reduction circuit disclosed and claimed in this patent application provides an advanced, highly accurate and compact instrument for high frequency data acquisition and processing.

4. 发明授权

US4200848A Transversal filter 失效
标题翻译：横向过滤器
公开(公告)号：US4200848A
公开(公告)日：1980-04-29
申请号：US907011
申请日：1978-05-18
申请人： Karl Knauer , Hans-Joerg Pfleiderer
发明人： Karl Knauer , Hans-Joerg Pfleiderer
IPC分类号： G11C27/00 , H01L21/339 , H01L29/40 , H01L29/417 , H01L29/76 , H01L29/762 , H01L29/768 , H03H15/02 , H03H7/28 , G11C19/14 , H03H7/30 , H03K5/159
CPC分类号： H03H15/023 , G11C27/00 , H01L29/40 , H01L29/76 , H01L29/76866 , H03H15/02
摘要： A transversal filter has at least one analog shift register which includes a number of parallel inputs and one series output. A further number of individual, predeterminable evaluator circuits are provided, each evaluator circuit having at least one signal input for the input of the signal to be filtered and at least one output, and each evaluator circuit comprises a pair of capacitors arranged on a surface of a substrate. The substrate has at least one substrate terminal and comprises doped semiconductor material which carries a first insulating layer or blocking layer capacitor which contacts an oppositely doped zone located on the surface of the substrate and which is provided with a terminal contact. A second insulating layer or blocking layer capacitor is arranged beside the first capacitor, the second capacitor connectible, via a switching element, to an associated parallel input. At least one evaluator circuit is designed such that its doped zone has a recess into which the first insulating layer or blocking layer capacitor is disposed, the first capacitor likewise having a recess into which the second capacitor is disposed so that the second capacitor is surrounded by the doped zone and by the first capacitor.
摘要翻译：横向滤波器具有至少一个模拟移位寄存器，其包括多个并行输入和一个串联输出。提供了另外数量的单个可预定的评估器电路，每个评估器电路具有用于输入待滤波的信号和至少一个输出的至少一个信号输入，并且每个评估器电路包括一对电容器，其布置在底物。衬底具有至少一个衬底端子，并且包括掺杂半导体材料，该掺杂半导体材料携带第一绝缘层或阻挡层电容器，该第一绝缘层或阻挡层电容器接触位于衬底表面上并且具有端子触点的相对掺杂区。第二绝缘层或阻挡层电容器设置在第一电容器旁边，第二电容器经由开关元件连接到相关的并行输入端。至少一个评估器电路被设计成使得其掺杂区具有设置有第一绝缘层或阻挡层电容器的凹槽，第一电容器同样具有凹槽，第二电容器被设置在该凹槽中，使得第二电容器被掺杂区和第一电容。

5. 发明授权

US4172983A Charge transfer filter 失效
标题翻译：电荷转移过滤器
公开(公告)号：US4172983A
公开(公告)日：1979-10-30
申请号：US879899
申请日：1978-02-21
申请人： Donald J. MacLennan
发明人： Donald J. MacLennan
IPC分类号： G11C27/04 , H01L29/768 , H03H15/02 , G11C19/28 , H01L29/34 , H01L29/78
CPC分类号： H03H15/02 , G11C27/04 , H01L29/76866
摘要： A charge transfer filter utilizing charge transfer accumulator structures for exponential smoothing of analog signals is described. The charge transfer accumulator structures provide short equilibration times, long smoothing time constants, high data rates and low dark currents.
摘要翻译：描述了利用电荷转移累加器结构进行模拟信号指数平滑处理的电荷转移滤波器。电荷转移累积器结构提供短平衡时间，长平滑时间常数，高数据速率和低暗电流。

6. 发明授权

US4124862A Charge transfer filter 失效
公开(公告)号：US4124862A
公开(公告)日：1978-11-07
申请号：US775662
申请日：1977-03-08
申请人： William E. Engeler , Jerome J. Tiemann
发明人： William E. Engeler , Jerome J. Tiemann
IPC分类号： G11C19/28 , H01L29/768 , H03H15/02 , H01L29/78
CPC分类号： H01L29/76866 , G11C19/285 , H01L29/76808 , H03H15/02
摘要： A charge transfer filter includes an accumulator charge storage location and means for alternately introducing charge into the accumulator charge storage location and then for removing a preselected fraction of the total charge in the accumulator charge storage location so that the total accumulated charge is known.

7. 发明授权

US4072939A Analog-to-digital and digital-to-analog converter circuits employing charge redistribution 失效
标题翻译：采用电荷再分配的模数和数模转换电路
公开(公告)号：US4072939A
公开(公告)日：1978-02-07
申请号：US662626
申请日：1976-03-01
申请人： Lawrence G. Heller , Lewis M. Terman
发明人： Lawrence G. Heller , Lewis M. Terman
IPC分类号： H03M1/44 , H01L29/768 , H01L29/78 , H03M1/00 , H03K13/03
CPC分类号： H01L29/76866 , H03M1/40 , H03M1/46 , Y10T307/352
摘要： Analog-to-digital (A/D) and digital-to-analog (D/A) converter circuits are provided using charge redistribution. The analog-to-digital converter circuit also employs successive approximation binary search techniques wherein the number of search voltages generated is a minimum. The analog-to-digital circuit includes a digital-to-analog converter circuit, a comparator circuit and a logic control means. The digital-to-analog circuit, under control of the logic means, accepts a reference voltage input and produces a sequence of search voltages which are compared with an unknown analog input voltage at the comparator. The resultant outputs from the comparator are applied to the control logic to determine the search voltage sequence. The digital-to-analog converter for the aforesaid circuit is provided in one embodiment employing charge-coupled-device technology. A substrate and two storage electrodes are combined to produce two potential storage wells and a transfer electrode is provided to move charge carriers between the storage wells. A reference charge packet Q.sub.R is stored and divided by charge redistribution between the two potential wells to produce a sequence of charge packets of value Q.sub.R /2, Q.sub.R /4, Q.sub.R /8, Q.sub.R /16 etc. which can be selectively combined to produce analog output of a D/A converter. In the A/D converter the same sequence of charge packets is used to generate the equivalent of a binary search sequence Q.sub.R /2, Q.sub.R /2.+-.Q.sub.R /4, Q.sub.R /2.+-.Q.sub.R /4.+-.Q.sub.R /8 etc. In another embodiment a bucket brigade device is provided to accomplish the same result. Because of the technique of charge redistribution wherein precise amounts of charge can be shifted in either direction between storage means, the total number of search value steps is a minimum.
摘要翻译：使用电荷再分配提供模数（A / D）和数/模（D / A）转换器电路。模数转换器电路还采用逐次逼近二进制搜索技术，其中产生的搜索电压的数量是最小的。该模数转换电路包括一个数模转换器电路，一个比较器电路和一个逻辑控制装置。在逻辑装置的控制下，数模转换电路接受参考电压输入，并产生与比较器上的未知模拟输入电压进行比较的搜索电压序列。来自比较器的结果输出被施加到控制逻辑以确定搜索电压序列。在使用电荷耦合器件技术的一个实施例中提供了用于上述电路的数模转换器。将衬底和两个存储电极组合以产生两个潜在的存储阱，并且提供转移电极以在存储阱之间移动电荷载流子。存储参考电荷分组QR，并通过两个势阱之间的电荷再分配来分割，以产生QR / 2，QR / 4，QR / 8，QR / 16等的电荷分组序列，其可以选择性地组合以产生 D / A转换器的模拟输出。在A / D转换器中，使用相同的电荷包序列来产生二进制搜索序列QR / 2，QR / 2 +/- QR / 4，QR / 2 +/- QR / 4 +/- QR / 8等。在另一实施例中，提供铲斗装置以实现相同的结果。由于电荷重新分配的技术，其中精确量的电荷可以在存储装置之间的任一方向上移动，所以搜索值步长的总数是最小的。

8. 发明授权

US4064524A Two-phase charge transfer device image sensor 失效
标题翻译：两相电荷转移装置图像传感器
公开(公告)号：US4064524A
公开(公告)日：1977-12-20
申请号：US703792
申请日：1976-07-09
申请人： Yoshiaki Hagiwara , Hiroshi Yamazaki
发明人： Yoshiaki Hagiwara , Hiroshi Yamazaki
IPC分类号： H01L21/339 , H01L27/148 , H01L29/06 , H01L29/10 , H01L29/762 , H01L29/768 , H04N5/335 , H04N5/341 , H04N5/3728 , H01L29/78 , H01J39/12 , H01L27/14 , H01L31/00
CPC分类号： H01L29/76866 , H01L27/14831 , H01L29/0646 , H01L29/1062
摘要： A charge coupled device capable of operating with two phase clock pulses wherein asymmetrical potential wells are established by the use of channel stoppers which are formed on opposite edges of the charge coupled device and which have restricted portions through which the charges can flow from one storage area to the other.The invention also comprises an information storage device including an array of photosensors with certain photosensors coupled to a particular charge transfer device according to the invention wherein channel stoppers with restricted passages are formed so as to provide asymmetrical charge transfer between the photosensors and various elements of the charge transfer device.
摘要翻译：一种电荷耦合器件，其能够用两相脉冲脉冲操作，其中通过使用形成在电荷耦合器件的相对边缘上的通道阻挡器来建立不对称势阱，并且具有限制部分，电荷可以通过该限制部分从一个存储区域到另一个

9. 发明授权

US4041520A Uniphase charge transfer device 失效
标题翻译：单相电荷转移装置
公开(公告)号：US4041520A
公开(公告)日：1977-08-09
申请号：US712302
申请日：1976-08-06
申请人： Wallace Edward Tchon
发明人： Wallace Edward Tchon
IPC分类号： G11C27/04 , H01L21/339 , H01L29/10 , H01L29/762 , H01L29/768 , H03H11/26 , H01L29/78 , G11C19/28 , H01L29/04
CPC分类号： H01L29/76866 , H01L29/1062
摘要： A uniphase charge transfer device comprises a plurality of electrode pairs disposed over a layer of gate oxide which overlies a semiconductor substrate. Within the substrate are a plurality of first conduction regions which are doped to a conductivity type opposite to that of the substrate. The first conduction regions underlie the separations between electrode pairs, and each one is electrically connected to one member of each electrode pair. A plurality of second conduction regions in the substrate are of the same conductivity type as the substrate but are of a substantially greater density of impurity atoms, and each of the second conduction regions underlies a portion of the other member of each electrode pair. A single clock line is connected to that member of each electrode pair which overlies the second conduction region. By alternatingly applying a predetermined voltage to the single clock line, charge packets representing information are moved unidirectionally through the device.
摘要翻译：单相电荷转移装置包括设置在半导体衬底上的栅极氧化物层上的多个电极对。在衬底内部是多个第一导电区域，其被掺杂成与衬底的导电类型相反的导电类型。第一导电区域位于电极对之间的分离之下，并且每个导电区域电连接到每个电极对的一个构件。衬底中的多个第二导电区域具有与衬底相同的导电类型，但是具有大大地更大的杂质浓度，并且每个第二导电区域位于每个电极对的另一个部件的一部分的下方。单个时钟线连接到覆盖在第二导电区域上的每个电极对的构件。通过交替地向单个时钟线施加预定电压，表示信息的电荷分组被单向地移动通过该装置。

10. 发明授权

US4035821A Device for introducing charge 失效
标题翻译：引入电荷的装置
公开(公告)号：US4035821A
公开(公告)日：1977-07-12
申请号：US653677
申请日：1976-01-29
申请人： Kamleshwar C. Gunsagar , Gilbert F. Amelio
发明人： Kamleshwar C. Gunsagar , Gilbert F. Amelio
IPC分类号： H01L29/768 , H01L29/78
CPC分类号： H01L29/76808 , H01L29/76866 , H01L29/76875
摘要： A device for introducing a known amount of charge to a line of charge storage elements in a charge-coupled device fabricated in a conductor-insulator-semiconductor system includes a buffer charge storage element fabricated adjacent a first charge storage element in the line of charge storage elements, the buffer charge storage element having its gate electrode controlled by a logic pulse whose level determines whether charge is to be introduced to the line of charge storage elements, and precharge means coupled to this buffer charge storage element for supplying a saturating charge to the buffer charge storage element.
摘要翻译：在导体 - 绝缘体 - 半导体系统中制造的电荷耦合器件中的电荷存储元件线上引入已知量的电荷的器件包括：在电荷存储线路中的第一电荷存储元件附近制造的缓冲电荷存储元件元件，其缓冲电荷存储元件的栅极由逻辑脉冲控制，逻辑脉冲的电平决定是否将电荷引入电荷存储元件，以及预充电装置，耦合到该缓冲电荷存储元件，用于将饱和电荷提供给缓冲电荷存储元件。

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