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1. 发明申请

US20190238148A1 Dual Reset Branch Analog-to-Digital Conversion 审中-公开
公开(公告)号：US20190238148A1
公开(公告)日：2019-08-01
申请号：US16378532
申请日：2019-04-08
申请人： Forza Silicon Corporation
发明人： Daniel Van Blerkom
IPC分类号： H03M1/12 , H03M1/46 , H03M1/40 , H03M1/38
CPC分类号： H03M1/1215 , H03M1/1205 , H03M1/122 , H03M1/123 , H03M1/38 , H03M1/40 , H03M1/403 , H03M1/46 , H03M1/462 , H03M1/464 , H03M1/466 , H03M1/468
摘要： Methods and systems for analog-to-digital conversion using two side branches that may be operated with overlapped timing such that a sampling phase may be overlapped with a previous conversion phase. Some embodiments provide a method of successive approximation A/D converting, comprising sampling a first signal onto a first capacitor that is configured to selectively couple to an analog input of a comparator, sampling a second signal onto capacitors that are coupled to a second analog input of the comparator and configured for charge redistribution successive approximation A/D conversion; carrying out, based on the first signal and the second signal, a charge redistribution successive approximation A/D conversion using the capacitors; and while carrying out the charge redistribution successive approximation A/D conversion based on the first and second signals, sampling a third signal onto a third capacitor that is configured to selectively couple to the analog input of a comparator.

2. 发明申请

US20150346272A1 SYSTEM FOR TESTING INTEGRATED CIRCUIT 有权
标题翻译：用于测试集成电路的系统
公开(公告)号：US20150346272A1
公开(公告)日：2015-12-03
申请号：US14288358
申请日：2014-05-27
申请人： Kumar Abhishek , Kushal Kamal , Vandana Sapra
发明人： Kumar Abhishek , Kushal Kamal , Vandana Sapra
IPC分类号： G01R31/28
CPC分类号： G01R31/2856 , H03M1/1245 , H03M1/38 , H03M1/40 , H03M1/42 , H03M1/466
摘要： An integrated circuit (IC) is connected to an automated test equipment (ATE) with pogo pins. The IC includes an analog-to-digital converter (ADC), a voltage controlled oscillator (VCO), and a compensation circuit. The ATE provides reference voltage signals to the ADC by way of the pogo pins. A potential drop across a pogo pin introduces an error in a reference voltage signal that is reflected in a digital signal generated by the ADC. The VCO generates reference frequency signals corresponding to the reference voltage signals. The compensation circuit receives the reference frequency signals and the digital signal and generates a compensation factor signal. The compensation circuit multiplies the compensation factor signal and the digital signal to generate a compensated digital signal to compensate for the error introduced by the potential drop across the pogo pins.
摘要翻译：集成电路（IC）连接到具有弹簧针的自动测试设备（ATE）。该IC包括模数转换器（ADC），压控振荡器（VCO）和补偿电路。 ATE通过弹簧引脚向ADC提供参考电压信号。在pogo引脚上的电压降引起在ADC产生的数字信号中反映的参考电压信号中的误差。 VCO产生对应于参考电压信号的参考频率信号。补偿电路接收参考频率信号和数字信号，并产生补偿因子信号。补偿电路将补偿因子信号和数字信号相乘以产生补偿数字信号，以补偿由pogo引脚上的电位降引入的误差。

3. 发明授权

US08754798B2 High-speed successive-approximation-register analog-to-digital converter and method thereof 有权
标题翻译：高速逐次逼近寄存器模数转换器及其方法
公开(公告)号：US08754798B2
公开(公告)日：2014-06-17
申请号：US13706600
申请日：2012-12-06
申请人： Realtek Semiconductor Corp.
发明人： Chia-Liang Lin
IPC分类号： H03M1/12 , H03M1/38 , H03M1/10
CPC分类号： H03M1/38 , H03M1/0692 , H03M1/10 , H03M1/1009 , H03M1/125 , H03M1/40 , H03M1/403 , H03M1/468
摘要： In one embodiment, a SAR (successive-approximation register) ADC (analog-to-digital converter) comprising: a plurality of capacitors, a switch controlled by a sampling signal for connecting a common node to a ground node when the sampling signal is asserted; a plurality of switching networks controlled by the sampling signal and a plurality of control bits comprising a respective grounding bit and a respective data bit, each of the plurality of switching networks for connecting a bottom plate of a respective capacitor to an analog input signal, a ground node, a first reference voltage, or a second reference voltage depending on the asserted signal or bit; a comparator for detecting a polarity of a voltage at the common node and outputting a binary decision along with a complementary binary decision when a comparing signal is asserted; a logic gate for receiving the binary decision and the complementary binary decision and outputting a ready signal indicating whether a decision is readily made; a timer for receiving the comparing signal and outputting a time out signal; and a SAR logic for receiving the binary decision, the ready signal, and the time out signal and outputting the sampling signal, the comparing signal, the plurality of control bits, and an output data.
摘要翻译：在一个实施例中，SAR（逐次逼近寄存器）ADC（模拟 - 数字转换器）包括：多个电容器，当采样信号被断言时由用于将公共节点连接到接地节点的采样信号控制的开关 ; 由采样信号控制的多个交换网络和包括相应的接地位和相应的数据位的多个控制位，用于将相应电容器的底板连接到模拟输入信号的多个开关网络中的每一个，接地节点，第一参考电压或第二参考电压，这取决于被断言的信号或位; 比较器，用于检测公共节点处的电压的极性，并且当比较信号被断言时，输出二进制判定以及互补的二进制判定; 用于接收二进制判定和互补二进制判定的逻辑门，并输出指示是否容易做出判定的就绪信号; 定时器，用于接收比较信号并输出超时信号; 以及用于接收二进制判定，就绪信号和超时信号并输出采样信号，比较信号，多个控制位和输出数据的SAR逻辑。

4. 发明授权

US08149150B2 Cyclic analog/digital converter 有权
标题翻译：循环模拟/数字转换器
公开(公告)号：US08149150B2
公开(公告)日：2012-04-03
申请号：US12812204
申请日：2009-01-08
申请人： Shoji Kawahito
发明人： Shoji Kawahito
IPC分类号： H03M1/00
CPC分类号： H03M1/0602 , H03M1/0695 , H03M1/40
摘要： A cyclic A/D converter 21 provides an amplification type noise cancellation process and cyclic A/D conversion in which a plurality of capacitors and an operational amplifier are shared without complicated processing. In the cyclic A/D converter 21, a gain stage 23 uses first to third capacitors 33, 35 and 37 and an operational amplifier circuit 39 to perform the process for noise cancellation and amplification to generate a difference signal between first and second signal levels. In the process for noise cancellation, the difference between the first signal level VR and the second signal level VS is generated. The amplification of this difference is carried out in conjunction with the process for noise cancellation. The gain stage 23 uses the first to third capacitors 33, 35 and 37 and the operational amplifier circuit 39 to perform the process for cyclic A/D conversion of the difference signal. A sub A/D converter circuit 25 receives a signal VOP from an output (e.g., a non-inverting output) 39a of the operational amplifier circuit 39.
摘要翻译：循环A / D转换器21提供放大型噪声消除处理和循环A / D转换，其中共享多个电容器和运算放大器，而不需要复杂的处理。在循环A / D转换器21中，增益级23使用第一至第三电容器33,35和37以及运算放大器电路39执行噪声消除和放大的处理，以在第一和第二信号电平之间产生差分信号。在消除噪声的过程中，产生第一信号电平VR与第二信号电平VS之差。该差异的放大结合噪声消除的过程进行。增益级23使用第一至第三电容器33,35和37以及运算放大器电路39执行用于差分信号的循环A / D转换的处理。子A / D转换电路25从运算放大器电路39的输出（例如，非反相输出）39a接收信号VOP。

5. 发明申请

US20110309963A1 SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER, METHOD OF CONTROLLING SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER, SOLID-STATE IMAGING DEVICE, AND IMAGING APPARATUS 有权
标题翻译：连续逼近型A / D转换器，控制类似A / D转换器，固态成像装置和成像装置的控制方法
公开(公告)号：US20110309963A1
公开(公告)日：2011-12-22
申请号：US13222062
申请日：2011-08-31
申请人： Masaki Sakakibara
发明人： Masaki Sakakibara
IPC分类号： H03M1/34
CPC分类号： H03M1/0675 , H03M1/066 , H03M1/20 , H03M1/40 , H03M1/462 , H03M1/806 , H04N5/363 , H04N5/378
摘要： A successive approximation type A/D converter includes: a reference signal generating section generating a reference signal; a comparator comparing an analog signal input thereto with the reference signal and converting the analog signal into a digital signal; and a control section controlling the reference signal to perform oversampling by executing an A/D conversion process on the analog signal at the comparator plural times such that the analog signal is A/D-converted into a digital value of N bits at the first A/D conversion process and such that the second and subsequent A/D conversion processes are performed starting with a lower bit of the (N−n)-th or lower order with upper n bits of the N-bit digital value obtained at the first A/D conversion process fixed.
摘要翻译：逐次逼近型A / D转换器包括：产生参考信号的参考信号产生部分; 比较将输入的模拟信号与参考信号进行比较并将模拟信号转换为数字信号的比较器; 以及控制部，通过对比较器的模拟信号多次执行A / D转换处理，控制参考信号进行过采样，使得模拟信号在A的第一个A处被A / D转换成N位的数字值 / D转换处理，并且使得从第（N-n）个或更低阶的较低位开始执行第二和随后的A / D转换处理，其中在第一（N-n）位获得的N位数字值的高n位 A / D转换过程固定。

6. 发明授权

US07928885B2 A/D converter 失效
标题翻译： A / D转换器
公开(公告)号：US07928885B2
公开(公告)日：2011-04-19
申请号：US12480094
申请日：2009-06-08
申请人： Tomohiko Sugimoto
发明人： Tomohiko Sugimoto
IPC分类号： H03M1/12
CPC分类号： H03M1/002 , H03M1/40 , H03M1/44
摘要： An A/D converter provides one or more operational amplifiers as components. The A/D converter includes a current controlling unit that is activated before an actual operation of the A/D converter to control a current of at least one of the operational amplifiers based on a settling characteristic of the operational amplifier.
摘要翻译： A / D转换器提供一个或多个运算放大器作为组件。 A / D转换器包括电流控制单元，其在A / D转换器的实际操作之前被激活，以基于运算放大器的稳定特性来控制至少一个运算放大器的电流。

7. 发明申请

US20090102688A1 MULTISTAGE ANALOG/DIGITAL CONVERTER AND METHOD FOR CALIBRATING SAID CONVERTER 有权
标题翻译：多模式模拟/数字转换器和校准转换器的方法
公开(公告)号：US20090102688A1
公开(公告)日：2009-04-23
申请号：US12198709
申请日：2008-08-26
申请人： Giovanni Antonio Cesura , Roberto Giampiero Massolini
发明人： Giovanni Antonio Cesura , Roberto Giampiero Massolini
IPC分类号： H03M1/10 , H03M1/12 , H03M1/00
CPC分类号： H03M1/1061 , H03M1/1004 , H03M1/162 , H03M1/164 , H03M1/40 , H03M1/44
摘要： A multistage analog/digital converter for converting in multi-step cycles an input signal into respective digital codes, each cycle step resolving at least one bit of a respective digital code. The converter includes: a sampling circuit inputting the signal and outputting a first sequence of analog samples; a generation block of a pseudorandom sequence of samples; a summing node, such as to input the first sequence and the pseudorandom sequence, obtaining in output a second sequence of analog samples including non-pseudorandom samples; a converter having a controllable digital gain receiving the second sequence and outputting bits of the digital codes; a feedback loop with a loop gain and including an analog amplifier; a digital calibration block to match the digital gain to the loop gain and including a prediction block to produce a digital estimation of said input signal starting from the bits resulting from converting the non-pseudorandom samples.
摘要翻译：一种用于以多步循环将输入信号转换成相应数字代码的多级模拟/数字转换器，每个循环步骤分辨相应数字代码的至少一位。转换器包括：采样电路，输入信号并输出第一序列模拟样本; 伪随机序列样本的生成块; 求和节点，诸如输入第一序列和伪随机序列，在输出中获得包括非伪随机样本的模拟样本的第二序列; 转换器，其具有可控数字增益，接收第二序列并输出数字码的位; 具有环路增益并包括模拟放大器的反馈回路; 数字校准块，用于将数字增益与环路增益相匹配，并包括预测块，以从转换非伪随机采样得到的位开始产生所述输入信号的数字估计。

8. 发明授权

US07508332B2 On die thermal sensor having analog-to-digital converter for use in semiconductor memory device 有权
标题翻译：具有用于半导体存储器件的模拟 - 数字转换器的管芯式热传感器
公开(公告)号：US07508332B2
公开(公告)日：2009-03-24
申请号：US11819795
申请日：2007-06-29
申请人： Chun-Seok Jeong , Jae-Jin Lee
发明人： Chun-Seok Jeong , Jae-Jin Lee
IPC分类号： H03M1/34
CPC分类号： G01K7/015 , G01K7/425 , H03M1/005 , H03M1/0863 , H03M1/109 , H03M1/40 , H03M1/46
摘要： An On Die Thermal Sensor (ODTS) of a semiconductor memory device includes: a temperature detector for detecting an internal temperature of the semiconductor memory device to generate a temperature voltage corresponding to the detected internal temperature; a tracking ADC for outputting a digital code by comparing the temperature voltage with a tracking voltage and performing a counting operation to the result of comparison; and an operation controller for controlling operations of the temperature detector and the analog-to-digital converter, wherein the tracking ADC performs the counting operation using a first tracking scheme having a relatively large unit variation width of the digital code value during an initial tracking period and a second tracking scheme having a relatively small unit variation width of the digital code value after the initial tracking period.
摘要翻译：半导体存储器件的散热片传感器（ODTS）包括：温度检测器，用于检测半导体存储器件的内部温度以产生对应于检测到的内部温度的温度电压; 跟踪ADC，用于通过将温度电压与跟踪电压进行比较来输出数字代码，并对比较结果执行计数操作; 以及用于控制温度检测器和模数转换器的操作的操作控制器，其中跟踪ADC使用在初始跟踪周期期间具有数字码值的相对大的单位变化宽度的第一跟踪方案来执行计数操作以及在初始跟踪周期之后具有数字码值的相对小的单位变化宽度的第二跟踪方案。

9. 发明授权

US07495589B1 Circuit and method for gain error correction in ADC 有权
标题翻译： ADC中增益误差校正的电路和方法
公开(公告)号：US07495589B1
公开(公告)日：2009-02-24
申请号：US11901355
申请日：2007-09-17
申请人： Dimitar T. Trifonov , Jerry L. Doorenbos
发明人： Dimitar T. Trifonov , Jerry L. Doorenbos
IPC分类号： H03M1/06
CPC分类号： H03M1/1019 , H03M1/40 , H03M1/46 , H03M3/382 , H03M3/43 , H03M3/456
摘要： Gain errors are corrected in an ADC chip including an integrator (17), a comparator (30), and a digital filter (37) by storing a gain-adjusted LSB size based on measured gain error in a memory (44). The gain-adjusted LSB size is applied to the digital filter to cause gain-adjusted LSB size values to be added to or subtracted from accumulated content of the digital filter in accordance with a first or second state, respectively, of the comparator (30) during each cycle of the ADC. The final accumulated content after all required cycles of the ADC is a gain-corrected digital output signal (Dout(gain-corrected)).
摘要翻译：通过将经增益调整的LSB大小基于测量的增益误差存储在存储器（44）中，在包括积分器（17），比较器（30）和数字滤波器（37）的ADC芯片中校正增益误差。经增益调整的LSB大小被施加到数字滤波器，以使得根据比较器（30）的第一或第二状态，增加经调整的LSB大小值被添加到数字滤波器的累积内容或从累积内容中减去，在ADC的每个周期。 ADC所需的所有周期之后的最终累加内容是增益校正的数字输出信号（Dout（增益校正））。

10. 发明授权

US06906657B1 Successive approximation analog-to-digital converter with sample and hold element 失效
标题翻译：具有采样和保持元件的逐次逼近模数转换器
公开(公告)号：US06906657B1
公开(公告)日：2005-06-14
申请号：US10750198
申请日：2003-12-31
申请人： Chandra Shekar A
发明人： Chandra Shekar A
IPC分类号： H03M1/34 , H03M1/40
CPC分类号： H03M1/40
摘要： According to some embodiments, a successive approximation analog-to-digital converter is provided.
摘要翻译：根据一些实施例，提供逐次逼近模数转换器。

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