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1. 发明授权

US5831452A Leak tolerant low power dynamic circuits 失效
标题翻译：耐漏电低功率动态电路
公开(公告)号：US5831452A
公开(公告)日：1998-11-03
申请号：US803582
申请日：1997-02-20
申请人： Edward Joseph Nowak , Minh Ho Tong , Lawrence G. Heller
发明人： Edward Joseph Nowak , Minh Ho Tong , Lawrence G. Heller
IPC分类号： H03K19/096 , H03K19/0948
CPC分类号： H03K19/0963
摘要： A novel precharge circuit is provided for dynamic CMOS logic circuits which are immune to leakage currents and reduce overall power consumption. The circuit comprises a precharge transistor for precharging a node to a high voltage level indicting a first logic state during a standby mode. Thereafter, during an active mode, the node may or may not be discharged by connected logic circuitry. If the node is discharged, then an additional transistor is provided to inhibit the precharging of the already charged node during a subsequent standby mode. Similarly, if the node is not discharged, a small keeper transistor is provided to keep the node at a fully precharged level.
摘要翻译：为动态CMOS逻辑电路提供了一种新颖的预充电电路，其免于漏电流并降低总体功耗。电路包括用于在待机模式期间将节点预充电到指示第一逻辑状态的高电压电平的预充电晶体管。此后，在活动模式期间，节点可以被连接的逻辑电路放电，也可以不被放电。如果节点放电，则提供附加晶体管以在随后的待机模式期间禁止已经充电的节点的预充电。类似地，如果节点不被放电，则提供小的保持晶体管以保持节点处于完全预充电电平。

2. 发明授权

US5260952A Fault tolerant logic system 失效
标题翻译：容错逻辑系统
公开(公告)号：US5260952A
公开(公告)日：1993-11-09
申请号：US693509
申请日：1991-04-30
申请人： Kenneth E. Beilstein, Jr. , John A. Fifield , Lawrence G. Heller , Hsing-San Lee , Charles H. Stapper
发明人： Kenneth E. Beilstein, Jr. , John A. Fifield , Lawrence G. Heller , Hsing-San Lee , Charles H. Stapper
IPC分类号： G01R31/317 , G06F11/08 , G06F11/10 , G06F11/16 , G11C29/00 , H03K19/00 , H03K19/003 , G01K31/28
CPC分类号： H03K19/00392 , G06F11/1044 , G11C29/84
摘要： A logic system including a first logic block for providing first differential outputs; a second logic block, identical to the first logic block, for providing second differential outputs; a fault detecting device, coupled to the first logic block, for detecting a fault in the first differential outputs; and a selecting device, coupled to the first and second logic blocks and to the fault detecting device, for selecting an output of one of the first and second logic blocks depending on whether the fault detecting device detects a fault.
摘要翻译：一种逻辑系统，包括用于提供第一差分输出的第一逻辑块; 第二逻辑块，与第一逻辑块相同，用于提供第二差分输出; 耦合到第一逻辑块的故障检测装置，用于检测第一差分输出中的故障; 以及耦合到第一和第二逻辑块和故障检测装置的选择装置，用于根据故障检测装置是否检测到故障来选择第一和第二逻辑块之一的输出。

3. 发明授权

US4638482A Random logic error detecting system for differential logic networks 失效
标题翻译：差分逻辑网络的随机逻辑误差检测系统
公开(公告)号：US4638482A
公开(公告)日：1987-01-20
申请号：US685880
申请日：1984-12-24
申请人： William R. Griffin , Lawrence G. Heller , Peter N. Horowitz
发明人： William R. Griffin , Lawrence G. Heller , Peter N. Horowitz
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G06F11/0751
摘要： A system for testing a differential logic network is provided which includes a differential exclusive OR circuit having a plurality of inputs for receiving complementary signals from the differential logic network and first and second output terminals and means, e.g., a conventional exclusive OR circuit, for determining the voltage difference between the first and second output terminals to indicate the presence or absence of a fault or error in the differential logic network under test.
摘要翻译：提供了一种用于测试差分逻辑网络的系统，其包括具有多个输入的差分异或电路，用于从差分逻辑网络和第一和第二输出端子接收互补信号，以及用于确定第一和第二输出端子之间的电压差，以指示被测差分逻辑网络中存在或不存在故障或错误。

4. 发明授权

US4230954A Permanent or semipermanent charge transfer storage systems 失效
标题翻译：永久或半永久电荷转移存储系统
公开(公告)号：US4230954A
公开(公告)日：1980-10-28
申请号：US974409
申请日：1978-12-29
申请人： Lawrence G. Heller
发明人： Lawrence G. Heller
IPC分类号： G11C17/00 , G11C11/35 , G11C14/00 , G11C16/04 , G11C19/28 , H01L21/8246 , H01L27/108 , H01L27/112 , H03K5/00 , G11C11/34 , H01L29/34 , H01L29/78
CPC分类号： H01L27/108 , G11C11/35 , G11C14/00 , G11C16/0466 , G11C19/282
摘要： Storage systems are provided with memory cells made of devices having different voltage thresholds for storing information permanently or semipermanently. The devices are arranged adjacent to each other and communicating with a diffusion region in a semiconductor substrate. Information is sensed by detecting the charge transferred from a selected cell to the diffusion region. In an embodiment of the invention, a P-type substrate has an N+ diffusion region formed therein with a plurality of adjacent and parallelly arranged word lines insulated from the substrate and disposed adjacent to the N+ diffusion region. A P+ region, preferably implanted into the substrate, is disposed under selected segments of the word lines to provide devices having a first or high threshold voltage magnitude. The remaining devices which are not associated with a P-30 region have a second or low threshold voltage magnitude. By applying a voltage of the same magnitude to each of the word lines, potential wells are formed which are filled by charge or carriers from the diffusion region. Since the potential wells associated with the high threshold devices hold less charge than do the low threshold devices, a charge or voltage sensing circuit connected to the N+ diffusion region is used to detect the amount of charge flowing between the wells and the diffusion region to thus identify the high and low threshold devices when the voltage on the selected word line is decreased. By eliminating the P+ regions and storing charge, e.g., electrons, at selected locations under the word lines in dual insulating layers, the cells may be electrically programmable.
摘要翻译：存储系统具有由具有不同电压阈值的设备制成的存储单元，用于永久地或半永久地存储信息。器件彼此相邻布置并与半导体衬底中的扩散区域连通。通过检测从所选择的单元传输到扩散区的电荷来感测信息。在本发明的一个实施例中，P型衬底具有形成在其中的多个相邻且平行布置的字线的N +扩散区，其与衬底绝缘并且邻近于N +扩散区设置。优选地植入衬底中的P +区被布置在字线的选定段下方以提供具有第一或高阈值电压幅度的器件。与P-30区域不相关的其余器件具有第二或低阈值电压幅度。通过向每个字线施加相同大小的电压，形成由扩散区域的电荷或载流子填充的势阱。由于与高阈值器件相关联的势阱比低阈值器件具有更少的电荷，所以使用连接到N +扩散区的电荷或电压感测电路来检测在阱和扩散区之间流动的电荷量，从而当所选字线上的电压降低时识别高和低阈值器件。通过在双重绝缘层中的字线下方的选定位置处消除P +区并且将电荷例如存储，电池可以是电可编程的。

5. 发明授权

US4300210A Calibrated sensing system 失效
标题翻译：校准传感系统
公开(公告)号：US4300210A
公开(公告)日：1981-11-10
申请号：US108242
申请日：1979-12-27
申请人： Satya N. Chakravarti , Lawrence G. Heller , Wilbur D. Pricer
发明人： Satya N. Chakravarti , Lawrence G. Heller , Wilbur D. Pricer
IPC分类号： G11C11/409 , G11C11/4091 , G11C11/56 , G11C19/36 , H03K5/08 , G11C27/00 , G11C11/24 , G11C11/40
CPC分类号： G11C11/565 , G11C11/4091 , G11C19/36 , G11C7/06
摘要： A calibrated sensing system is provided in accordance with the teachings of this invention for sensing charge in a storage medium, such as a storage capacitor, coupled to an access or bit/sense line which compensates for most sources of variability in the storage medium and in the access line. In the system, the unknown charge stored in the storage medium is transferred to a first capacitor or potential well via the access line. A high charge state of the storage medium is written into the storage medium and known fractional packets of charge are prepared therefrom, transferred selectively to a second capacitor or potential well and compared with the unknown charge in the first potential to determine the relative level of the unknown charge that was stored in the storage medium. By selectively using two or more fractional packets of charge multilevel sensing is performed.
摘要翻译：根据本发明的教导，提供了一种校准的感测系统，用于感测存储介质（例如存储电容器）中的电荷，该存储介质耦合到访问或位/检测线，其补偿存储介质中的大部分变异源，并且接入线路。在系统中，存储在存储介质中的未知电荷经由存取线路传送到第一电容器或势阱。将存储介质的高电荷状态写入存储介质，并且从其准备已知的分数电荷分组，将其选择性地传输到第二电容器或势阱，并与第一电位中的未知电荷进行比较，以确定第存储在存储介质中的未知电荷。通过选择性地使用两个或更多个电荷多级感测的分数分组。

6. 发明授权

US4137464A Charge-transfer binary search generating circuit 失效
标题翻译：电荷转移二进制搜索生成电路
公开(公告)号：US4137464A
公开(公告)日：1979-01-30
申请号：US825016
申请日：1977-08-16
申请人： Lawrence G. Heller , Lewis M. Terman
发明人： Lawrence G. Heller , Lewis M. Terman
IPC分类号： H03M1/44 , G11C11/56 , G11C19/18 , G11C19/36 , G11C27/02 , H03K4/02 , H03M1/00 , H03M1/66
CPC分类号： G11C27/024 , G11C19/186 , G11C19/36 , H03M1/804
摘要： A bucket brigade circuit is described for generating a sequence of packets of charge carriers of the form Q.sub.R /2, Q.sub.R /4, Q.sub.R /8....Q.sub.R /2.sup.N where N is an integer. The charge packets thus generated can be employed in combinations in either digital-to-analog or analog-to-digital converters. The charge generation circuit requires two equal capacitors which are used for charge redistribution. To obtain accurate quantities of charge in the generated charge packets the capacitors employed should be large, however the use of large capacitors results in low operating speed because of the large charge transfer time constants involved. The described circuit provides a scheme to reduce charge transfer time constants and therefore obtain greater speed while still permitting the use of large capacitors for high accuracy. The circuit includes a small coupling capacitor connected in series with one of the charge redistribution capacitors to produce a total capacitance which is equal to or smaller than the coupling capacitance. The sequence of charge carriers produced by the circuit can be injected into either a bucket brigade circuit or a charge-coupled-device circuit for use, for example, in digital-to-analog and analog-to-digital converters.
摘要翻译：描述了用于产生形式为QR / 2，QR / 4，QR / 8 .... QR / 2N的电荷载体的序列序列的桶旅电路，其中N是整数。这样产生的电荷包可以以数模转换器或模数转换器的组合使用。电荷产生电路需要用于电荷再分配的两个相等的电容器。为了在产生的电荷包中获得准确的电荷量，所使用的电容应该是大的，然而由于涉及大的电荷转移时间常数，使用大的电容器导致低的操作速度。所描述的电路提供了一种减少电荷转移时间常数并因此获得更高速度同时允许使用大电容器以获得高精度的方案。电路包括与电荷再分配电容器中的一个串联连接的小耦合电容器，以产生等于或小于耦合电容的总电容。由电路产生的电荷载体的序列可以被注入到例如在数模转换器和模数转换器中使用的桶式电路或电荷耦合器件电路中。

7. 发明授权

US6118318A Self biased differential amplifier with hysteresis 失效
标题翻译：具有滞后的自偏置差分放大器
公开(公告)号：US6118318A
公开(公告)日：2000-09-12
申请号：US853963
申请日：1997-05-09
申请人： John A. Fifield , Lawrence G. Heller
发明人： John A. Fifield , Lawrence G. Heller
IPC分类号： H03K3/3525 , H03K3/295 , H03K19/0948
CPC分类号： H03K3/3525
摘要： A self biased differential amplifier has a switching point accurately set according to a reference voltage. DC hysteresis is provided, by a circuit internal to the differential amplifier. The amplifier has an input circuit having first and second series connected transistors, wherein the beta ratio of these first and second transistors is changed by enabling an additional transistor of a hysteresis circuit according to an output state of the differential amplifier. When the output state is "high", the switching point is decreased in order that temporary small drops (due to noise or glitches) in the input signal are ignored. Conversely, when the output state is "low", the switching point is increased in order that temporary small increases in the input signal are ignored.
摘要翻译：自偏置差分放大器具有根据参考电压精确设定的开关点。通过差分放大器内部的电路提供直流滞后。放大器具有输入电路，该输入电路具有第一和第二串联连接的晶体管，其中通过根据差分放大器的输出状态启用滞后电路的附加晶体管来改变这些第一和第二晶体管的β比。当输出状态为“高”时，切换点减小，以便忽略输入信号中的临时小的下降（由于噪声或毛刺）。相反，当输出状态为“低”时，切换点增加，以便忽略输入信号的临时小的增加。

8. 发明授权

US4570084A Clocked differential cascode voltage switch logic systems 失效
标题翻译：时钟差分共源共栅电压开关逻辑系统
公开(公告)号：US4570084A
公开(公告)日：1986-02-11
申请号：US554146
申请日：1983-11-21
申请人： William R. Griffin , Lawrence G. Heller
发明人： William R. Griffin , Lawrence G. Heller
IPC分类号： H03K19/0175 , H03K19/096 , H03K19/173 , H03K19/017 , H03K19/20 , H03K19/21
CPC分类号： H03K19/1738
摘要： A differential logic system is provided for a complete logic family which has a first switching circuit that produces a given output signal at a first output node and a second switching circuit that produces a second output signal which is the complement of that of the given output signal at a second output node. First and second clocked devices are connected from the first and second output nodes, respectively, to a voltage source, and first and second inverters are connected to the first and second output nodes, respectively. Additionally, a regenerative circuit may be connected between the first and second output nodes and the voltage source.
摘要翻译：提供了一种用于完整逻辑系列的差分逻辑系统，其具有在第一输出节点处产生给定输出信号的第一开关电路和产生与给定输出信号的补码相乘的第二输出信号的第二开关电路在第二输出节点。第一和第二时钟装置分别从第一和第二输出节点连接到电压源，第一和第二反相器分别连接到第一和第二输出节点。此外，再生电路可以连接在第一和第二输出节点和电压源之间。

9. 发明授权

US4459609A Charge-stabilized memory 失效
标题翻译：电荷稳定记忆
公开(公告)号：US4459609A
公开(公告)日：1984-07-10
申请号：US301563
申请日：1981-09-14
申请人： John A. Fifield , Lawrence G. Heller , Lloyd A. Walls
发明人： John A. Fifield , Lawrence G. Heller , Lloyd A. Walls
IPC分类号： G11C11/404 , G11C11/56 , G11C27/02 , H01L29/78 , G11C11/24 , H01L27/02
CPC分类号： G11C11/404 , G11C11/565 , G11C27/024 , Y10S257/92
摘要： A dense memory is provided which includes a one device random access memory cell using charge fill and spill techniques wherein a potential well under a storage node is filled with charge and the excess charge above a predetermined level is spilled to a diffusion or drain region connected to a sense line through a channel region controlled by pulses on a word line. One bit or two or more bits of information may be stored in the potential well at any given instant of time. Depending upon the value of the increment of voltage applied to the storage node or electrode, a given analog charge packet is stored in a potential well formed under the storage electrode. Information is read by applying a voltage to the word line to turn on the channel region and then stepping down the voltage on the storage electrode in fractional, preferably one half, increments. Charge from a charge packet spilled from the potential well under the storage electrode is detected by a sensing circuit connected to the sense line. To rewrite information into the potential well, the original increment of voltage is applied to the storage node and the sense line is pulled to ground so that the diffusion region acts as a source of charge for the potential well.
摘要翻译：提供了一种密集存储器，其包括使用电荷填充和溢出技术的一个器件随机存取存储器单元，其中存储节点下方的势阱填充有电荷，并且超过预定水平的超量电荷溢出到连接到通过由字线上的脉冲控制的通道区域的感测线。信息的一位或两位或更多位可以在任何给定的时刻存储在潜在井中。取决于施加到存储节点或电极的电压增量的值，给定的模拟电荷包被存储在形成在存储电极下方的势阱中。通过向字线施加电压来读取信息以打开通道区域，然后以分数，优选为一半的增量降低存储电极上的电压。通过连接到感测线的感测电路来检测从存储电极下方的电位阱溢出的电荷分组的充电。为了将信息重写到势阱中，电压的原始增量被施加到存储节点，并且感测线被拉到地，使得扩散区充当势阱的电荷源。

10. 发明授权

US4282646A Method of making a transistor array 失效
标题翻译：制造晶体管阵列的方法
公开(公告)号：US4282646A
公开(公告)日：1981-08-11
申请号：US68282
申请日：1979-08-20
申请人： Andres G. Fortino , Henry J. Geipel, Jr. , Lawrence G. Heller , Ronald Silverman
发明人： Andres G. Fortino , Henry J. Geipel, Jr. , Lawrence G. Heller , Ronald Silverman
IPC分类号： H01L21/822 , G11C11/56 , G11C17/12 , H01L21/225 , H01L21/8246 , H01L27/04 , H01L27/112 , H01L29/78 , H01L21/26
CPC分类号： H01L27/11266 , G11C11/56 , G11C11/5692 , G11C17/12 , H01L21/2253 , H01L27/112
摘要： A method of making a transistor array includes forming a plurality of gate electrodes insulated from a semiconductor substrate having an impurity of a given conductivity, introducing a first impurity having a conductivity opposite to that of the given conductivity into a given region of the substrate which is adjacent to an edge of each of the gate electrodes, introducing a second impurity having the given conductivity into given regions adjacent to selected gate electrodes, the second impurity having a significantly higher diffusivity than that of the first impurity in the semiconductor substrate, and driving the second impurity along the surface of the semiconductor substrate to form in the substrate under each of the selected gate electrodes a region having a concentration of impurity of the given conductivity higher than that of the semiconductor substrate. The transistor array may be used, e.g. to make a read only memory (ROM) by connecting appropriate current sensing means to each of the given regions to indicate the presence or absence of the higher diffusivity impurity when a predetermined voltage is applied to the gate electrodes. In one embodiment, the semiconductor substrate is made of P type conductivity, the first impurity is arsenic which produces N type conductivity regions and the second impurity is boron, which produces P type conductivity. Since boron has a higher diffusivity than arsenic, after they are driven by heating the boron impurity produces a high threshold region under the gate electrode when introduced in sufficiently high concentration.
摘要翻译：制造晶体管阵列的方法包括形成与具有给定导电性的杂质的半导体衬底绝缘的多个栅电极，将具有与所述导电性相反的导电性的第一杂质引入衬底的给定区域与每个栅电极的边缘相邻，将具有给定导电性的第二杂质引入到与所选择的栅电极相邻的给定区域中，第二杂质具有比半导体衬底中的第一杂质显着更高的扩散率，并驱动沿着半导体衬底的表面形成第二杂质，以在所选择的栅电极的每一个下的衬底中形成具有比半导体衬底的导电性高的给定导电性的杂质浓度的区域。可以使用晶体管阵列，例如，通过将适当的电流感测装置连接到每个给定区域来形成只读存储器（ROM），以指示当将预定电压施加到栅电极时存在或不存在较高扩散性杂质。在一个实施例中，半导体衬底由P型导电性制成，第一杂质是产生N型导电区域的砷，第二杂质是硼，产生P型导电性。由于硼具有比砷更高的扩散性，因此通过加热驱动硼杂质，当以足够高的浓度引入时，在栅电极下产生高阈值区域。

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