专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20180358105A1 MAGNETIC WALL UTILIZATION SPIN MOSFET AND MAGNETIC WALL UTILIZATION ANALOG MEMORY 审中-公开
公开(公告)号：US20180358105A1
公开(公告)日：2018-12-13
申请号：US15781836
申请日：2017-04-14
申请人： TDK CORPORATION
发明人： Tomoyuki SASAKI
IPC分类号： G11C19/14 , G11C11/54 , G11C11/16 , H01L43/02 , G11C11/56 , G11C27/00 , H01L27/22
摘要： A magnetic wall utilization spin MOSFET includes a magnetic wall driving layer including a magnetic wall, a first region, a second region, and a third region located between the first region and the second region, a channel layer, a magnetization free layer provided at a first end portion of a first surface of the channel layer, and arranged so as to be in contact with the third region of the magnetic wall driving layer, a magnetization fixed layer provided at a second end portion opposite to the first end portion, and a gate electrode provided between the first end portion and the second end portion of the channel layer through a gate insulating layer.

2. 发明授权

US4516263A Spatially integral, video signal processor 失效
标题翻译：空间积分，视频信号处理器
公开(公告)号：US4516263A
公开(公告)日：1985-05-07
申请号：US373620
申请日：1982-04-30
申请人： Brock S. Dew , Paul Greiff
发明人： Brock S. Dew , Paul Greiff
IPC分类号： G01S3/784 , G01S3/786 , H04N5/378 , G06K9/00 , G11C19/14 , H01L27/00 , H03H15/02
CPC分类号： G01S3/7864 , G01S3/784 , H04N3/1575
摘要： A video signal processor, particularly for use in identifying light source position, in which a video signal stream from an image detector is processed directly on a substrate using charge coupled device stored image transfer technology. The video signal is clocked through an array of charge coupled devices in a plurality of closely adjacent channels on a single semiconductor chip in such manner that the pattern of signals stored on the chip in the region of the adjacent channels corresponds to the light source image on the detector. Video signal processing is shared between the chip and external electronics to provide an indication of signal strength (acquisition), signal background, and signal centroiding in both horizontal and vertical axes. Much of the signal processing is provided directly on the chip by segmenting and intercoupling the charge coupled device electrodes in a predetermined pattern. There results a reduction in the amount of interconnection, external electronics and the spatial distribution of the video signal that improves the system immunity to environmental noise and limits weight aloft.
摘要翻译：特别是用于识别光源位置的视频信号处理器，其中使用电荷耦合器件存储的图像传输技术在基板上直接处理来自图像检测器的视频信号流。视频信号通过在单个半导体芯片上的多个紧密相邻的通道中的电荷耦合器件的阵列进行计时，以使存储在相邻通道区域中的芯片上的信号的模式对应于光源图像检测器。视频信号处理在芯片和外部电子设备之间共享，以提供在水平轴和垂直轴上的信号强度（采集），信号背景和信号质心的指示。信号处理的大部分通过以预定图案分段和互耦合电荷耦合的器件电极而直接在芯片上提供。结果导致互连量，外部电子设备和视频信号的空间分布的减少，这提高了系统对环境噪声的抵抗力并且在高处限制了重量。

3. 发明授权

US4426629A Two-dimensional kernel generator for transversal filters 失效
标题翻译：用于横向滤波器的二维核心发生器
公开(公告)号：US4426629A
公开(公告)日：1984-01-17
申请号：US334109
申请日：1981-12-24
申请人： Scott D. Fouse
发明人： Scott D. Fouse
IPC分类号： G06T5/20 , G11C19/38 , H03H15/02 , G11C19/14 , H01L27/00
CPC分类号： H03H15/02 , G06T5/20 , G11C19/38
摘要： In the present invention, image processing is performed at speeds comparable to those achieved in parallel processing without requiring substantially more area on the substrate than that required in serial processing. In this invention, for an N.times.N processing kernel, N rows of image memory are processed in parallel through a plurality of N floating gate arrays of dimension N.times.N, N-1 of the data rows from the memory being recirculated through the N floating gate structures before being discarded. Each of the floating gate structures is offset from the adjacent floating gate structure by one row so that the data from memory need be recirculated only once.
摘要翻译：在本发明中，以与并行处理中实现的速度相当的速度执行图像处理，而不需要比在串行处理中所需要的基板上更多的面积。在本发明中，对于N×N处理核，N行图像存储器通过N×N，N-N个数量行的多个N个浮置门阵列并行地从存储器中经过N个浮动门结构再循环被丢弃浮动栅极结构中的每一个都从相邻的浮动栅极结构偏移一行，使得来自存储器的数据仅需要再循环一次。

4. 发明授权

US11276711B2 Semiconductor device, display device, and electronic device 有权
公开(公告)号：US11276711B2
公开(公告)日：2022-03-15
申请号：US15821006
申请日：2017-11-22
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Hiroki Inoue , Fumika Akasawa
IPC分类号： G11C19/00 , H01L27/12 , H03K3/356 , G09G3/36 , G09G3/3266 , G09G3/3233 , G11C19/28 , G11C19/14 , G06F3/041
摘要： A level shifter including a transistor that can be formed through the same process as a display portion is provided. A semiconductor device serves as a level shifter including transistors having the same conductivity type. The semiconductor device includes a so-called MIS capacitor in which metal, an insulator, and a semiconductor are stacked as a capacitor for boosting an input signal. Since the MIS capacitor is used, the gate-source voltage of a transistor for generating an output signal can be increased. Thus, boosting operation to generate the output signal can be performed more surely.

5. 发明授权

US10482987B2 Magnetic wall utilization spin MOSFET and magnetic wall utilization analog memory 有权
公开(公告)号：US10482987B2
公开(公告)日：2019-11-19
申请号：US15781836
申请日：2017-04-14
申请人： TDK CORPORATION
发明人： Tomoyuki Sasaki
IPC分类号： G11C19/14 , H01L43/08 , G11C11/16 , G11C11/54 , G11C11/56 , G11C27/00 , H01L27/22 , H01L43/02 , G11C19/08 , H01L29/66 , G06N3/063
摘要： A magnetic wall utilization spin MOSFET includes a magnetic wall driving layer including a magnetic wall, a first region, a second region, and a third region located between the first region and the second region, a channel layer, a magnetization free layer provided at a first end portion of a first surface of the channel layer, and arranged so as to be in contact with the third region of the magnetic wall driving layer, a magnetization fixed layer provided at a second end portion opposite to the first end portion, and a gate electrode provided between the first end portion and the second end portion of the channel layer through a gate insulating layer.

6. 发明申请

US20180123548A1 SIGNAL CHANNEL FOR REDUCING CROSSTALK NOISE, MODULE SUBSTRATE AND MEMORY MODULE INCLUDING THE SAME 审中-公开
公开(公告)号：US20180123548A1
公开(公告)日：2018-05-03
申请号：US15720326
申请日：2017-09-29
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： DONG-YEOP KIM , Jae-Jun Lee
IPC分类号： H03H7/38 , H01P3/08 , H05K1/02 , G11C19/14 , G11C5/06 , G11C7/10 , G11C5/04
CPC分类号： H03H7/38 , G11C5/04 , G11C5/063 , G11C7/10 , G11C19/14 , H01P3/02 , H01P3/081 , H01P5/187 , H05K1/0243 , H05K2201/09236 , H05K2201/10159
摘要： A signal channel includes at least one first signal line positioned in a first signal layer and at least one second signal line positioned in a second signal layer. The first signal layer extends in a first horizontal direction. The second signal layer extends along a second horizontal plane parallel to the first horizontal plane and spaced apart from the first horizontal plane along a vertical direction orthogonal to the first and second horizontal planes. The first signal line includes a first coupling segment and the second signal line includes a second coupling segment. The first coupling segment at least partially overlaps the second coupling segment along the vertical direction. The first and second coupling segments are positioned to form a greater degree of capacitive coupling between the first and second coupling segments than a degree of capacitive coupling formed between other segments of the first and second signal lines.

7. 发明授权

US10536127B2 Signal channel for reducing crosstalk noise, module substrate and memory module including the same 有权
公开(公告)号：US10536127B2
公开(公告)日：2020-01-14
申请号：US15720326
申请日：2017-09-29
申请人： SAMSUNG ELECTRONICS CO., LTD.
发明人： Dong-Yeop Kim , Jae-Jun Lee
IPC分类号： H03H7/38 , H01P3/08 , G11C7/10 , H05K1/02 , G11C19/14 , G11C5/06 , H01P3/02 , H01P5/18 , G11C5/04
摘要： A signal channel includes at least one first signal line positioned in a first signal layer and at least one second signal line positioned in a second signal layer. The first signal layer extends in a first horizontal direction. The second signal layer extends along a second horizontal plane parallel to the first horizontal plane and spaced apart from the first horizontal plane along a vertical direction orthogonal to the first and second horizontal planes. The first signal line includes a first coupling segment and the second signal line includes a second coupling segment. The first coupling segment at least partially overlaps the second coupling segment along the vertical direction. The first and second coupling segments are positioned to form a greater degree of capacitive coupling between the first and second coupling segments than a degree of capacitive coupling formed between other segments of the first and second signal lines.

8. 发明授权

US4292609A Recursive filter for transfer of charge deposits 失效
标题翻译：递归滤波器用于传输电荷沉积物
公开(公告)号：US4292609A
公开(公告)日：1981-09-29
申请号：US48155
申请日：1979-06-13
申请人： Michel Feldman , Jeannine Le Goff epouse Henaff
发明人： Michel Feldman , Jeannine Le Goff epouse Henaff
IPC分类号： H03H15/00 , H03H15/02 , G11C19/14 , H03H17/04
CPC分类号： H03H15/00 , H03H15/02
摘要： A CTD recursive filter includes a single channel with two side-by-side CTD delay lines wherein charges are transferred in opposite directions. Each electrode of the first delay line forms a pair with a corresponding electrode of the second delay line. Each even pair of electrodes are separated from the next odd pair of electrodes by an even bridge electrode occupying the entire width of the channel. Each odd pair of electrodes are separated from the next even pair of electrodes by an odd bridge electrode also occupying the entire width of the channel. An electrode of the first line in an even pair and the electrode of the second line in the next odd pair have lengths the sum of which is a constant. An electrode of the first line in an odd pair and the electrode of the second line in the next even pair have lengths, the sum of which is equal to the constant. At each odd clock pulse, the odd bridge electrode charges are distributed to the closer even bridge electrodes. At each even clock pulse, the even bridge electrode charges are distributed to the closer odd bridge electrodes. Each delay line is connected from an input for a signal to be filtered and to an output for the filtered signal.
摘要翻译： CTD递归滤波器包括具有两个并排CTD延迟线的单通道，其中电荷以相反的方向传送。第一延迟线的每个电极与第二延迟线的对应电极形成一对。每个偶数对电极通过占据通道整个宽度的均匀的桥接电极与下一个奇数对电极分离。每个奇数对电极通过奇数桥电极与下一个偶数对电极分离，也占据通道的整个宽度。偶数对的第一行的电极和下一个奇数对中的第二行的电极的总和的长度是常数。奇数对中的第一行的电极和下一偶数对中的第二行的电极具有等于该常数的长度。在每个奇数时钟脉冲，奇数桥电极电荷分布到更近的偶数桥电极。在每个偶数时钟脉冲中，偶数桥电极电荷分布到更近的奇数桥电极。每个延迟线从要滤波的信号的输入端连接到滤波信号的输出。

9. 发明授权

US4277699A Latch circuit operable as a D-type edge trigger 失效
标题翻译：锁存电路可用作D型边沿触发器
公开(公告)号：US4277699A
公开(公告)日：1981-07-07
申请号：US60933
申请日：1979-07-26
申请人： David J. Brown , Ronald G. Walther , Thomas W. Williams , Michael D. Wrigglesworth
发明人： David J. Brown , Ronald G. Walther , Thomas W. Williams , Michael D. Wrigglesworth
IPC分类号： G01R31/3185 , G06F7/00 , G06F11/22 , G11C19/00 , G11C19/14 , G11C19/28 , H03K3/027 , H03K3/037 , H03K3/286 , H03K5/15 , H03K19/20 , H03K23/00
CPC分类号： H03K5/15 , G01R31/318541 , G06F7/00 , G11C19/00 , G11C19/14 , G11C19/28 , H03K3/037
摘要： A shift register latch circuit (FIG. 1) comprised of a polarity hold latch 1 connected to a set/reset latch 2. The latches can be clocked with separate non-overlapping clock trains (+A, +B and +C) so that automatically generated test patterns can be applied to a scan input S to test the circuit. This conforms to the so-called Level Sensitive Scan Design (LSSD) rules. During system operation, the shift register latch circuit operates as a `D` type edge trigger by connecting the clock input +B of the set/reset latch 2 to the clock -C supplied to the polarity hold latch 1. By connecting a number of shift register latches together a Johnson counter can be formed and by clocking all latches with a single oscillator, a series of non-overlapping clock trains can be produced. Implementations of the shift register latch in AND circuits or AND OR INVERT circuits are described.
摘要翻译：一个移位寄存器锁存电路（图1），包括一个连接到一个置位/复位锁存器2的极性保持锁存器1.锁存器可以用单独的非重叠时钟序列（+ A，+ B和+ C）计时，以便自动生成的测试图案可以应用于扫描输入S来测试电路。这符合所谓的水平敏感扫描设计（LSSD）规则。在系统操作期间，移位寄存器锁存电路通过将设置/复位锁存器2的时钟输入+ B连接到提供给极性保持锁存器1的时钟-C来作为“D”型边沿触发。通过连接多个移位寄存器锁存在一起可以形成约翰逊计数器，并且通过使用单个振荡器对所有锁存器进行计时，可以产生一系列不重叠的时钟列。描述了AND电路中的移位寄存器锁存器的实现，或AND或INVERT电路。

10. 发明授权

US4200848A Transversal filter 失效
标题翻译：横向过滤器
公开(公告)号：US4200848A
公开(公告)日：1980-04-29
申请号：US907011
申请日：1978-05-18
申请人： Karl Knauer , Hans-Joerg Pfleiderer
发明人： Karl Knauer , Hans-Joerg Pfleiderer
IPC分类号： G11C27/00 , H01L21/339 , H01L29/40 , H01L29/417 , H01L29/76 , H01L29/762 , H01L29/768 , H03H15/02 , H03H7/28 , G11C19/14 , H03H7/30 , H03K5/159
CPC分类号： H03H15/023 , G11C27/00 , H01L29/40 , H01L29/76 , H01L29/76866 , H03H15/02
摘要： A transversal filter has at least one analog shift register which includes a number of parallel inputs and one series output. A further number of individual, predeterminable evaluator circuits are provided, each evaluator circuit having at least one signal input for the input of the signal to be filtered and at least one output, and each evaluator circuit comprises a pair of capacitors arranged on a surface of a substrate. The substrate has at least one substrate terminal and comprises doped semiconductor material which carries a first insulating layer or blocking layer capacitor which contacts an oppositely doped zone located on the surface of the substrate and which is provided with a terminal contact. A second insulating layer or blocking layer capacitor is arranged beside the first capacitor, the second capacitor connectible, via a switching element, to an associated parallel input. At least one evaluator circuit is designed such that its doped zone has a recess into which the first insulating layer or blocking layer capacitor is disposed, the first capacitor likewise having a recess into which the second capacitor is disposed so that the second capacitor is surrounded by the doped zone and by the first capacitor.
摘要翻译：横向滤波器具有至少一个模拟移位寄存器，其包括多个并行输入和一个串联输出。提供了另外数量的单个可预定的评估器电路，每个评估器电路具有用于输入待滤波的信号和至少一个输出的至少一个信号输入，并且每个评估器电路包括一对电容器，其布置在底物。衬底具有至少一个衬底端子，并且包括掺杂半导体材料，该掺杂半导体材料携带第一绝缘层或阻挡层电容器，该第一绝缘层或阻挡层电容器接触位于衬底表面上并且具有端子触点的相对掺杂区。第二绝缘层或阻挡层电容器设置在第一电容器旁边，第二电容器经由开关元件连接到相关的并行输入端。至少一个评估器电路被设计成使得其掺杂区具有设置有第一绝缘层或阻挡层电容器的凹槽，第一电容器同样具有凹槽，第二电容器被设置在该凹槽中，使得第二电容器被掺杂区和第一电容。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式