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1. 发明授权

US06903411B1 Architecture for circuit connection of a vertical transistor 有权
标题翻译：垂直晶体管的电路连接架构
公开(公告)号：US06903411B1
公开(公告)日：2005-06-07
申请号：US09648164
申请日：2000-08-25
申请人： Yih-Feng Chyan , John Michael Hergenrother , Donald Paul Monroe
发明人： Yih-Feng Chyan , John Michael Hergenrother , Donald Paul Monroe
IPC分类号： H01L27/10 , H01L21/336 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L21/8244 , H01L27/092 , H01L27/11 , H01L29/78 , H01L29/778
CPC分类号： H01L29/66666 , H01L21/76895 , H01L21/823885 , H01L27/11 , H01L27/1104 , H01L29/7827
摘要： An architecture for connection between regions in or adjacent a semiconductor layer. According to one embodiment a semiconductor device includes a first layer of semiconductor material and a first field effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The device includes a second field effect transistor also having a first source/drain region formed in the first layer. A channel region of the second transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. A conductive layer comprising a metal is positioned between the first source/drain region of each transistor to conduct current from one first source/drain region to the other first source/drain region.In another embodiment a first device region, is formed on a semiconductor layer. A second device region, is also formed on the semiconductor layer. A conductor layer comprising metal is positioned adjacent the first and second device regions to effect electrical connection between the first and second device regions. A first field effect transistor gate region is formed over the first device region and the conductor layer and a second field effect transistor gate region is formed over the second device region and the conductor layer.
摘要翻译：用于在半导体层中或邻近半导体层之间的区域之间连接的架构。根据一个实施例，半导体器件包括第一层半导体材料和第一场效应晶体管，其具有形成在第一层中的第一源/漏区。在第一层上形成晶体管的沟道区，并且在沟道区上形成相关联的第二源极/漏极区。该器件包括第二场效应晶体管，其还具有形成在第一层中的第一源/漏区。在第一层上形成第二晶体管的沟道区，并且在沟道区上形成相关联的第二源极/漏极区。包括金属的导电层位于每个晶体管的第一源极/漏极区之间，以将电流从一个第一源极/漏极区传导到另一个第一源极/漏极区。在另一个实施例中，第一器件区域形成在半导体层上。第二器件区域也形成在半导体层上。包括金属的导体层定位成邻近第一和第二器件区域以实现第一和第二器件区域之间的电连接。第一场效应晶体管栅极区域形成在第一器件区域上，并且导体层和第二场效应晶体管栅极区域形成在第二器件区域和导体层上。

2. 发明授权

US06358807B1 Bipolar semiconductor device and method of forming same having reduced transient enhanced diffusion 有权
标题翻译：双极半导体器件及其形成方法具有减少的瞬时增强扩散
公开(公告)号：US06358807B1
公开(公告)日：2002-03-19
申请号：US09504306
申请日：2000-02-15
申请人： Yih-Feng Chyan , Chung Leung
发明人： Yih-Feng Chyan , Chung Leung
IPC分类号： H01L21331
CPC分类号： H01L29/66272 , H01L21/8249 , H01L27/0623 , H01L29/167
摘要： A BiCMOS semiconductor device and a method of forming same are disclosed. A bipolar transistor region is formed adjacent a CMOS device region within a semiconductor substrate. Carbon is implanted in an amount ranging from about 1013 to about 1014 cm−2 before forming the base, emitter and collector within the bipolar transistor region to aid in suppressing transient enhanced diffusion. The bipolar transistor region is subject to rapid thermal annealing to aid in suppressing the transient enhanced diffusion.
摘要翻译：公开了一种BiCMOS半导体器件及其形成方法。在半导体衬底内的CMOS器件区域附近形成双极晶体管区域。在双极晶体管区域内形成基极，发射极和集电极之前，以约1013至约1014cm-2的量注入碳，以有助于抑制瞬时增强的扩散。双极晶体管区域经受快速热退火，有助于抑制瞬时增强的扩散。

3. 发明授权

US6001701A Process for making bipolar having graded or modulated collector 失效
标题翻译：制备具有渐变或调制收集器的双极的方法
公开(公告)号：US6001701A
公开(公告)日：1999-12-14
申请号：US871385
申请日：1997-06-09
申请人： Michael Scott Carroll , Samir Chaudhry , Alan Sangone Chen , Yih-Feng Chyan , Kuo-Hua Lee , William John Nagy
发明人： Michael Scott Carroll , Samir Chaudhry , Alan Sangone Chen , Yih-Feng Chyan , Kuo-Hua Lee , William John Nagy
IPC分类号： H01L21/331 , H01L21/762 , H01L21/8249
CPC分类号： H01L29/66272 , H01L21/76218 , H01L21/8249 , Y10S148/009 , Y10S148/01 , Y10S148/011
摘要： A bipolar fabrication process, illustratively suited for integration into a conventional CMOS process to thereby form a BiCMOS integrated circuits is disclosed. The collector and base are formed through multiple implants and a single masking step to thereby provide a continuous low resistance collector region.
摘要翻译：公开了一种双极制造工艺，其示意性地适合于集成到常规CMOS工艺中，从而形成BiCMOS集成电路。集电极和基极通过多个注入和单个掩模步骤形成，从而提供连续的低电阻集电区。

4. 发明授权

US06537887B2 Integrated circuit fabrication 有权
公开(公告)号：US06537887B2
公开(公告)日：2003-03-25
申请号：US09727325
申请日：2000-11-30
申请人： Yih-Feng Chyan , Chung Wai Leung , Yi Ma , Demi Nguyen
发明人： Yih-Feng Chyan , Chung Wai Leung , Yi Ma , Demi Nguyen
IPC分类号： H01L218222
CPC分类号： H01L29/66272 , H01L21/26506 , H01L21/31155 , H01L21/8249 , H01L27/0623
摘要： An integrated circuit and a process for making the same are provided. The circuit has a nitrogen implanted emitter window, wherein the nitrogen has been implanted into the emitter window after the emitter window etch, but prior to the emitter conductor deposition. Nitrogen implantation is expected to minimize oxide growth variation.

5. 发明授权

US06359317B1 Vertical PNP bipolar transistor and its method of fabrication 有权
标题翻译：垂直PNP双极晶体管及其制造方法
公开(公告)号：US06359317B1
公开(公告)日：2002-03-19
申请号：US09222587
申请日：1998-12-28
申请人： Michael S. Carroll , Yih-Feng Chyan , Samir Chaudhry , Tony G. Ivanov , Robert W. Dail , Alan S. Chen
发明人： Michael S. Carroll , Yih-Feng Chyan , Samir Chaudhry , Tony G. Ivanov , Robert W. Dail , Alan S. Chen
IPC分类号： H01L2976
CPC分类号： H01L29/66272 , H01L21/8249 , H01L27/0623 , H01L29/7322
摘要： A bipolar vertical PNP transistor compatible with CMOS processing and useful in a complementary BiMOS structure is characterized in that it is devoid of an epitaxial layer and employs a high-energy implanted phosphorus layer to provide N-type substrate isolation.
摘要翻译：与CMOS处理兼容并且可用于互补BiMOS结构的双极性垂直PNP晶体管的特征在于其没有外延层并且采用高能注入磷层来提供N型衬底隔离。

6. 发明授权

US06750528B2 Bipolar device 有权
标题翻译：双极器件
公开(公告)号：US06750528B2
公开(公告)日：2004-06-15
申请号：US09767477
申请日：2001-01-23
申请人： Yih-Feng Chyan
发明人： Yih-Feng Chyan
IPC分类号： H01L2900
CPC分类号： H01L29/66287 , H01L27/0623 , H01L27/0826
摘要： An integrated electronic device includes a semiconductor substrate layer having a major surface formed along a crystal plane. In one embodiment a first conductivity type region is formed in the substrate layer and a substantially monocrystalline semiconductor layer is deposited thereon. The deposited layer includes a first portion of a second conductivity type and a second portion of the first conductivity type formed over the first portion. The first portion and the first region form a pn junction. An upper-most substrate surface formed along a first plane and a first doped region of a first conductivity type is formed above the first plane. A second doped region of a second conductivity type is formed over the first doped region resulting in formation of a p-n junction in a second plane above the first plane. Electrical connection is provided to the first doped region with a conductor formed between the first and second planes.
摘要翻译：集成电子器件包括具有沿着晶面形成的主表面的半导体衬底层。在一个实施例中，在衬底层中形成第一导电类型区域，并且在其上沉积基本单晶半导体层。沉积层包括形成在第一部分上的第二导电类型的第一部分和第一导电类型的第二部分。第一部分和第一区域形成pn结。沿着第一平面形成的最上面的衬底表面和第一导电类型的第一掺杂区域形成在第一平面上方。在第一掺杂区域上形成第二导电类型的第二掺杂区域，导致在第一平面上方的第二平面中形成p-n结。电连接被提供给第一掺杂区域，其中导体形成在第一和第二平面之间。

7. 发明授权

US06451660B1 Method of forming bipolar transistors comprising a native oxide layer formed on a substrate by rinsing the substrate in ozonated water 有权
标题翻译：一种形成双极晶体管的方法，该方法包括通过在臭氧水中漂洗该衬底而在衬底上形成的自然氧化物层
公开(公告)号：US06451660B1
公开(公告)日：2002-09-17
申请号：US09591037
申请日：2000-06-09
申请人： Yi Ma , Yih-Feng Chyan , Chung Wai Leung , Jane Qian Liu , Timothy Scott Campbell
发明人： Yi Ma , Yih-Feng Chyan , Chung Wai Leung , Jane Qian Liu , Timothy Scott Campbell
IPC分类号： H01L2131
CPC分类号： H01L29/66272 , H01L21/02238 , H01L21/02255 , H01L21/02307 , H01L21/31675 , H01L29/0804
摘要： A bipolar device (10) includes an oxide layer (24) which is grown on the surface (16) of a semiconductor substrate (12) by immersing the surface in ozonated deionized water. By selecting an appropriate temperature of the water and concentration of the ozone, the thickness of the film can be maintained within fine tolerances from lot to lot, and over the surface of a wafer (W) comprising the substrate.
摘要翻译：双极器件（10）包括通过将表面浸入臭氧化去离子水中而在半导体衬底（12）的表面（16）上生长的氧化物层（24）。通过选择水的适当温度和臭氧的浓度，可以将薄膜的厚度保持在大量的精细公差之内，并且在包含基底的晶片（W）的表面上。

8. 发明授权

US06274490B1 Method of manufacturing semiconductor devices having high pressure anneal 有权
标题翻译：制造具有高压退火的半导体器件的方法
公开(公告)号：US06274490B1
公开(公告)日：2001-08-14
申请号：US09521268
申请日：2000-03-08
申请人： Yih-Feng Chyan , Yi Ma
发明人： Yih-Feng Chyan , Yi Ma
IPC分类号： H01L2144
CPC分类号： H01L29/518 , H01L21/28176 , H01L21/3003 , H01L21/324 , H01L21/76826 , H01L21/76834
摘要： The present invention provides a method of passivating a semiconductor device having a capping layer formed thereover, comprising: (1) subjecting the semiconductor device to a high pressure within a pressure chamber and (2) exposing the semiconductor device to a passivating gas. The high pressure causes the passivating gas, such as a deuterated passivating gas, to penetrate the capping layer and thereby passivate the semiconductor device. The method provided by the present invention is, therefore, particularly useful in those instances where a final passivation step is desired after the formation of the capping layer. It is believed that the hydrogen isotope bonds to dangling bond sites within the semiconductor device, which are most often present at a silicon/silicon dioxide interface. Further, because of their larger mass, these hydrogen isotope atoms are not easily removed by electron flow during the operation of the device as is the case with the lighter hydrogen atoms.
摘要翻译：本发明提供一种钝化具有形成在其上的覆盖层的半导体器件的方法，包括：（1）使半导体器件在压力室内受到高压，以及（2）将半导体器件暴露于钝化气体。高压使诸如氘代钝化气体的钝化气体穿透封盖层，从而钝化半导体器件。因此，本发明提供的方法在形成覆盖层之后需要最终钝化步骤的情况下特别有用。据信氢同位素结合到半导体器件内的悬挂键合位置，其通常存在于硅/二氧化硅界面处。此外，由于它们的质量较大，与较轻的氢原子一样，这些氢同位素原子在器件的操作过程中不容易被电子流除去。

9. 发明授权

US06815302B2 Method of making a bipolar transistor with an oxygen implanted emitter window 有权
标题翻译：制造具有氧注入发射器窗口的双极晶体管的方法
公开(公告)号：US06815302B2
公开(公告)日：2004-11-09
申请号：US10028614
申请日：2001-12-21
申请人： Alan Sangone Chen , Yih-Feng Chyan , Chung Wai Leung , Yi Ma , William John Nagy
发明人： Alan Sangone Chen , Yih-Feng Chyan , Chung Wai Leung , Yi Ma , William John Nagy
IPC分类号： H01L218228
CPC分类号： H01L29/66272 , H01L21/8249 , H01L27/0635 , H01L29/7375
摘要： The present invention provides a method of manufacturing a bipolar transistor. The method may comprise forming a collector in a semiconductor wafer substrate, forming a base in the collector, implanting an oxide region within said collector and over the base, and forming an emitter over the substrate such that the oxide region is located between the emitter and the base.
摘要翻译：本发明提供一种制造双极晶体管的方法。该方法可以包括在半导体晶片衬底中形成集电极，在集电极中形成基极，在所述集电极内部和底部上注入氧化物区域，并在衬底上形成发射极，使得氧化物区域位于发射极和发射极之间的基地。

10. 发明授权

US06657281B1 Bipolar transistor with a low K material in emitter base spacer regions 失效
标题翻译：在发射极基极间隔区域中具有低K材料的双极晶体管
公开(公告)号：US06657281B1
公开(公告)日：2003-12-02
申请号：US09631755
申请日：2000-08-03
申请人： Yih-Feng Chyan , Chunchieh Huang , Chung Wai Leung , Yi Ma , Shahriar Moinian
发明人： Yih-Feng Chyan , Chunchieh Huang , Chung Wai Leung , Yi Ma , Shahriar Moinian
IPC分类号： H01L27082
CPC分类号： H01L29/66272 , H01L21/8249 , H01L29/0804
摘要： The present invention provides a bipolar transistor located on a semiconductor wafer substrate. The bipolar transistor may comprise a collector located in the semiconductor wafer substrate, a base located in the collector, and an emitter located on the base and in contact with at least a portion of the base, wherein the emitter has a low K layer located therein. The low K layer may be, for example, located proximate a side of the emitter, or it may be located proximate opposing sides of the emitter. In all embodiments, however, the low K layer does not interfere with the proper functioning of the bipolar transistor, and substantially reduces the emitter-base capacitance typically associated with conventional bipolar transistors.
摘要翻译：本发明提供一种位于半导体晶片基板上的双极晶体管。双极晶体管可以包括位于半导体晶片衬底中的集电极，位于集电极中的基极和位于基极上并与基极的至少一部分接触的发射极，其中发射极具有位于其中的低K层。例如，低K层可以位于靠近发射极的一侧，或者它可以位于发射极的相对侧附近。然而，在所有实施例中，低K层不干扰双极晶体管的正常功能，并且基本上减小了通常与常规双极晶体管相关联的发射极 - 基极电容。

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