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1. 发明授权

US06903411B1 Architecture for circuit connection of a vertical transistor 有权
标题翻译：垂直晶体管的电路连接架构
公开(公告)号：US06903411B1
公开(公告)日：2005-06-07
申请号：US09648164
申请日：2000-08-25
申请人： Yih-Feng Chyan , John Michael Hergenrother , Donald Paul Monroe
发明人： Yih-Feng Chyan , John Michael Hergenrother , Donald Paul Monroe
IPC分类号： H01L27/10 , H01L21/336 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L21/8244 , H01L27/092 , H01L27/11 , H01L29/78 , H01L29/778
CPC分类号： H01L29/66666 , H01L21/76895 , H01L21/823885 , H01L27/11 , H01L27/1104 , H01L29/7827
摘要： An architecture for connection between regions in or adjacent a semiconductor layer. According to one embodiment a semiconductor device includes a first layer of semiconductor material and a first field effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The device includes a second field effect transistor also having a first source/drain region formed in the first layer. A channel region of the second transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. A conductive layer comprising a metal is positioned between the first source/drain region of each transistor to conduct current from one first source/drain region to the other first source/drain region.In another embodiment a first device region, is formed on a semiconductor layer. A second device region, is also formed on the semiconductor layer. A conductor layer comprising metal is positioned adjacent the first and second device regions to effect electrical connection between the first and second device regions. A first field effect transistor gate region is formed over the first device region and the conductor layer and a second field effect transistor gate region is formed over the second device region and the conductor layer.
摘要翻译：用于在半导体层中或邻近半导体层之间的区域之间连接的架构。根据一个实施例，半导体器件包括第一层半导体材料和第一场效应晶体管，其具有形成在第一层中的第一源/漏区。在第一层上形成晶体管的沟道区，并且在沟道区上形成相关联的第二源极/漏极区。该器件包括第二场效应晶体管，其还具有形成在第一层中的第一源/漏区。在第一层上形成第二晶体管的沟道区，并且在沟道区上形成相关联的第二源极/漏极区。包括金属的导电层位于每个晶体管的第一源极/漏极区之间，以将电流从一个第一源极/漏极区传导到另一个第一源极/漏极区。在另一个实施例中，第一器件区域形成在半导体层上。第二器件区域也形成在半导体层上。包括金属的导体层定位成邻近第一和第二器件区域以实现第一和第二器件区域之间的电连接。第一场效应晶体管栅极区域形成在第一器件区域上，并且导体层和第二场效应晶体管栅极区域形成在第二器件区域和导体层上。

2. 发明授权

US06197641B1 Process for fabricating vertical transistors 有权
标题翻译：制造垂直晶体管的工艺
公开(公告)号：US06197641B1
公开(公告)日：2001-03-06
申请号：US09335707
申请日：1999-06-18
申请人： John Michael Hergenrother , Donald Paul Monroe , Gary Robert Weber
发明人： John Michael Hergenrother , Donald Paul Monroe , Gary Robert Weber
IPC分类号： H01L21336
CPC分类号： H01L29/66666 , H01L29/161 , H01L29/7827 , H01L29/78642
摘要： A process for fabricating a vertical MOSFET device for use in integrated circuits is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET. In the process the first and third layers have etch rates that are significantly lower than the etch rate of the second layer in an etchant selected to remove the second layer. The top layer, which is either the third or subsequent layer, is a stop layer for a subsequently performed mechanical polishing step that is used to remove materials formed over the at least three layers. After the at least three layers of material are formed on the substrate, a window or trench is formed in the layers. The window terminates at the surface of the silicon substrate in which one of either a source or drain region is formed in the silicon substrate. The window or trench is then filled with a semiconductor material. This semiconductor plug becomes the vertical channel of the transistor. Therefore the crystalline semiconductor plug is doped to form a source extension, a drain extension, and a channel region in the plug. Subsequent processing forms the other of a source or drain on top of the vertical channel and removes the sacrificial second material layer. The removal of the sacrificial second layer exposes a portion of the doped semiconductor plug. The device gate dielectric is then formed on the exposed portion of the doped semiconductor plug. The gate electrode is then deposited. The physical gate length of the resulting device corresponds to the deposited thickness of the second material layer.
摘要翻译：公开了用于制造用于集成电路的垂直MOSFET器件的工艺。在该过程中，在半导体衬底上依次形成至少三层材料。三层被布置成使得第二层介于第一层和第三层之间。第二层是牺牲性的，即在随后的处理期间该层被完全去除。第二层的厚度限定了垂直MOSFET的物理栅极长度。在该过程中，第一层和第三层的蚀刻速率明显低于蚀刻剂中被选择去除第二层的第二层的蚀刻速率。顶层，其是第三层或后续层，是用于随后执行的机械抛光步骤的停止层，其用于去除在至少三层上形成的材料。在衬底上形成至少三层材料之后，在这些层中形成窗口或沟槽。窗口终止于在硅衬底中形成源区或漏区之一的硅衬底的表面。然后用半导体材料填充窗口或沟槽。该半导体插头成为晶体管的垂直沟道。因此，晶体半导体插头被掺杂以在插头中形成源延伸部，漏极延伸部和沟道区域。随后的处理形成垂直通道顶部的源极或漏极中的另一个，并去除牺牲的第二材料层。牺牲第二层的去除暴露了掺杂半导体插件的一部分。然后在掺杂半导体插头的暴露部分上形成器件栅极电介质。然后沉积栅电极。所得装置的物理栅极长度对应于第二材料层的沉积厚度。

3. 发明授权

US06653181B2 CMOS integrated circuit having vertical transistors and a process for fabricating same 有权
标题翻译：具有垂直晶体管的CMOS集成电路及其制造方法
公开(公告)号：US06653181B2
公开(公告)日：2003-11-25
申请号：US10211674
申请日：2002-08-02
申请人： John Michael Hergenrother , Donald Paul Monroe
发明人： John Michael Hergenrother , Donald Paul Monroe
IPC分类号： H01L218238
CPC分类号： H01L21/823885 , H01L27/0688 , H01L27/092
摘要： A process for fabricating a CMOS integrated circuit with vertical MOSFET devices is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET devices. After the at least three layers of material are formed on the substrate, the resulting structure is selectively doped to form an n-type region and a p-type region in the structure. Windows or trenches are formed in the layers in both the n-type region and the p-type region. The windows terminate at the surface of the silicon substrate in which one of either a source or drain region is formed. The windows or trenches are then filled with a semiconductor material. This semiconductor plug becomes the vertical channel of the transistor. Therefore the crystalline semiconductor plug is doped to form a source extension, a drain extension, and a channel region in the plug. Subsequent processing forms the other of a source or drain on top of the vertical channel and removes the sacrificial second material layer. The removal of the sacrificial second layer exposes a portion of the doped semiconductor plug. The device gate dielectric is then formed on the exposed portion of the doped semiconductor plug. The gate electrode is then deposited. The physical gate length of the resulting device corresponds to the deposited thickness of the second material layer.
摘要翻译：公开了一种用于制造具有垂直MOSFET器件的CMOS集成电路的工艺。在该过程中，在半导体衬底上依次形成至少三层材料。三层被布置成使得第二层介于第一层和第三层之间。第二层是牺牲性的，即在随后的处理期间该层被完全去除。第二层的厚度限定了垂直MOSFET器件的物理栅极长度。在衬底上形成至少三层材料之后，所得结构被选择性地掺杂以在该结构中形成n型区域和p型区域。 Windows或沟槽形成在n型区域和p型区域中的层中。窗口终止于其中形成源极或漏极区域之一的硅衬底的表面。然后用半导体材料填充窗口或沟槽。该半导体插头成为晶体管的垂直沟道。因此，晶体半导体插头被掺杂以在插头中形成源延伸部，漏极延伸部和沟道区域。随后的处理形成垂直通道顶部的源极或漏极中的另一个，并去除牺牲的第二材料层。牺牲第二层的去除暴露了掺杂半导体插件的一部分。然后在掺杂半导体插头的暴露部分上形成器件栅极电介质。然后沉积栅电极。所得装置的物理栅极长度对应于第二材料层的沉积厚度。

4. 发明授权

US6027975A Process for fabricating vertical transistors 有权
标题翻译：制造垂直晶体管的工艺
公开(公告)号：US6027975A
公开(公告)日：2000-02-22
申请号：US143274
申请日：1998-08-28
申请人： John M. Hergenrother , Donald Paul Monroe
发明人： John M. Hergenrother , Donald Paul Monroe
IPC分类号： H01L21/336 , H01L29/161 , H01L29/78 , H01L29/786
CPC分类号： H01L29/66666 , H01L29/161 , H01L29/7827 , H01L29/78642
摘要： A process for fabricating a vertical MOSFET device for use in integrated circuits is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET. In the process the first and third layers have etch rates that are significantly lower than the etch rate of the second layer in an etchant selected to remove the second layer.After the at least three layers of material are formed on the substrate, a window or trench is formed in the layers. The window terminates at the surface of the silicon substrate in which one of either a source or drain region is formed in the silicon substrate. The window or trench is then filled with a semiconductor material. This semiconductor plug becomes the vertical channel of the transistor. Therefore the crystalline semiconductor plug is doped to form a source extension, a drain extension, and a channel region in the plug. Subsequent processing forms the other of a source or drain on top of the vertical channel and removes the sacrificial second material layer. The removal of the sacrificial second layer exposes a portion of the doped semiconductor plug. The device gate dielectric is then formed on the exposed portion of the doped semiconductor plug. The gate electrode is then deposited. The physical gate length of the resulting device corresponds to the deposited thickness of the second material layer.
摘要翻译：公开了用于制造用于集成电路的垂直MOSFET器件的工艺。在该过程中，在半导体衬底上依次形成至少三层材料。三层被布置成使得第二层介于第一层和第三层之间。第二层是牺牲性的，即在随后的处理期间该层被完全去除。第二层的厚度限定了垂直MOSFET的物理栅极长度。在该过程中，第一层和第三层的蚀刻速率明显低于蚀刻剂中被选择去除第二层的第二层的蚀刻速率。在衬底上形成至少三层材料之后，在这些层中形成窗口或沟槽。窗口终止于在硅衬底中形成源区或漏区之一的硅衬底的表面。然后用半导体材料填充窗口或沟槽。该半导体插头成为晶体管的垂直沟道。因此，晶体半导体插头被掺杂以在插头中形成源延伸部，漏极延伸部和沟道区域。随后的处理形成垂直通道顶部的源极或漏极中的另一个，并去除牺牲的第二材料层。牺牲第二层的去除暴露了掺杂半导体插件的一部分。然后在掺杂半导体插头的暴露部分上形成器件栅极电介质。然后沉积栅电极。所得装置的物理栅极长度对应于第二材料层的沉积厚度。

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