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1. 发明授权

US06756279B2 Method for manufacturing a bipolar transistor in a CMOS integrated circuit 有权
标题翻译：在CMOS集成电路中制造双极晶体管的方法
公开(公告)号：US06756279B2
公开(公告)日：2004-06-29
申请号：US10209190
申请日：2002-07-30
申请人： Olivier Menut , Hervé Jaouen , Guillaume Bouche
发明人： Olivier Menut , Hervé Jaouen , Guillaume Bouche
IPC分类号： H01L218228
CPC分类号： H01L29/66272 , H01L21/8249
摘要： A method for manufacturing a contact between a semiconductor substrate and a doped polysilicon layer deposited on the substrate with an interposed insulating layer, wherein elements adapted to making the insulating layer permeable to the migration of dopants from the polysilicon layer to the substrate are implanted.
摘要翻译：一种用于制造半导体衬底和沉积在具有中间绝缘层的衬底上的掺杂多晶硅层之间的接触的方法，其中植入适于使掺杂剂从多晶硅层迁移至衬底的绝缘层可渗透的元件。

2. 发明授权

US06265277B1 Method for making a bipolar transistor for the protection of an integrated circuit against electrostatic discharges 失效
标题翻译：制造用于保护集成电路免受静电放电的双极晶体管的方法
公开(公告)号：US06265277B1
公开(公告)日：2001-07-24
申请号：US09220635
申请日：1998-12-24
申请人： François Tailliet
发明人： François Tailliet
IPC分类号： H01L218228
CPC分类号： H01L27/0259
摘要： In a method for the making of a lateral bipolar transistor, the formation of a field oxide layer on the surface of the substrate, between the collector and the emitter of the protection transistor, is avoided. The lateral bipolar transistors made by the disclosed method are advantageously used to protect MOS type integrated circuits against electrical discharges.
摘要翻译：在制造横向双极晶体管的方法中，避免了在保护晶体管的集电极和发射极之间的衬底表面上形成场氧化物层。通过所公开的方法制造的横向双极晶体管有利地用于保护MOS型集成电路免受放电。

3. 发明授权

US06573146B2 Methods of manufacturing complementary bipolar transistors 失效
标题翻译：制造互补双极晶体管的方法
公开(公告)号：US06573146B2
公开(公告)日：2003-06-03
申请号：US09978521
申请日：2001-10-16
申请人： Jong-Hwan Kim , Tae-Hoon Kwon , Cheol-Joong Kim , Suk-Kyun Lee
发明人： Jong-Hwan Kim , Tae-Hoon Kwon , Cheol-Joong Kim , Suk-Kyun Lee
IPC分类号： H01L218228
CPC分类号： H01L21/8226 , H01L21/8224 , H01L21/8228 , H01L21/82285 , H01L27/0233 , H01L27/0647 , H01L27/0826
摘要： A complementary bipolar transistor having a lateral npn bipolar transistor, a vertical and a lateral pnp bipolar transistor, an integrated injection logic, a diffusion capacitor, a polysilicon capacitor and polysilicon resistors are disclosed. The lateral pnp bipolar transistor has an emitter region and a collector region which includes high-density regions and low-density regions, and the emitter region is formed in an n type tub region. In the integrated injection logic circuit, collector regions are surrounded by a high-density p type region, and low-density p type regions are formed under the collector regions. The diffusion capacitor and the polysilicon capacitor are formed in one substrate. The diffusion regions except the regions formed by diffusing the impurities in the polysilicon resistors into the epitaxial layer are formed before forming the polysilicon resistors, and polysilicon electrodes are formed along with the polysilicon resistors.
摘要翻译：公开了具有横向npn双极晶体管，垂直和侧向pnp双极晶体管，集成注入逻辑，扩散电容器，多晶硅电容器和多晶硅电阻器的互补双极晶体管。横向pnp双极晶体管具有包括高密度区域和低密度区域的发射极区域和集电极区域，并且发射极区域形成在n型槽区域中。在集成注入逻辑电路中，集电极区域被高密度p型区域包围，在集电极区域形成低密度p型区域。扩散电容器和多晶硅电容器形成在一个衬底中。在形成多晶硅电阻器之前形成除了将多晶硅电阻器中的杂质扩散到外延层中形成的区域之外的扩散区域，并且多晶硅电极与多晶硅电阻器一起形成。

4. 发明授权

US06249022B1 Trench flash memory with nitride spacers for electron trapping 失效
标题翻译：沟槽闪存，用于电子捕获的氮化物间隔物
公开(公告)号：US06249022B1
公开(公告)日：2001-06-19
申请号：US09425395
申请日：1999-10-22
申请人： Chih-Hung Lin , Robin Lee
发明人： Chih-Hung Lin , Robin Lee
IPC分类号： H01L218228
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/7923
摘要： A method for fabricating a flash memory cell is described. A conformal ultra thin oxide layer is formed on a substrate having a trench formed therein, followed by forming silicon nitride spacers on the portion of the ultra thin oxide layer which covers the sidewalls of the trench. The silicon nitride spacers are separated into a first silicon nitride spacer on the right sidewall and a second silicon nitride spacer on the left sidewall. Thereafter, a gate oxide layer is formed on the silicon nitride spacers, followed by forming a polysilicon gate on the gate oxide layer in the substrate. Subsequently, a source/drain region is formed on both sides of the polysilicon gate in the substrate.
摘要翻译：描述了一种制造闪存单元的方法。在其上形成有沟槽的衬底上形成共形的超薄氧化物层，然后在覆盖沟槽的侧壁的超薄氧化物层的部分上形成氮化硅间隔物。氮化硅间隔物被分成右侧壁上的第一氮化硅间隔物和左侧壁上的第二氮化硅间隔物。此后，在氮化硅间隔物上形成栅极氧化层，随后在衬底的栅极氧化物层上形成多晶硅栅极。随后，在衬底中的多晶硅栅极的两侧上形成源/漏区。

5. 发明授权

US06232193B1 Method of forming isolated integrated injection logic gate 失效
标题翻译：形成隔离集成注入逻辑门的方法
公开(公告)号：US06232193B1
公开(公告)日：2001-05-15
申请号：US09640110
申请日：2000-08-15
申请人： Chun-Yu Chen , Gilles Marcel Ferru , Serge Bardy
发明人： Chun-Yu Chen , Gilles Marcel Ferru , Serge Bardy
IPC分类号： H01L218228
CPC分类号： H01L21/8226 , H01L27/0237
摘要： An integrated injection logic device is provided in which each collector of an I2L gate is isolated by a field oxide (“FOX”), or by other suitable isolation such as, for example, an isolation trench. The connection of the base to the collectors, between the base contact region and the bottom of the collectors, is made underneath the field oxide using a buried p type layer (TN3 in the Figures illustrating the invention). Because both silicide and heavy implant p+ implant is present at the base contact point only, the recombination current is reduced. This reduces the current loss when compared to the current loss of the known device. Additionally, current gain is also improved by placing a deep base implant close to the emitter of the upside own NPN transistor in the integrated logic device. The area of the base and the area of the collectors is decoupled, i.e. one can adjust the base to collector areas and the base contact area, independently to control the total base current, thus allowing more freedom in layout optimization of the I2L gate and allowing more freedom in optimizing the gain of the I2L gate.
摘要翻译：提供了一种集成注入逻辑器件，其中I2L栅极的每个集电极由场氧化物（“FOX”）隔离，或通过其他合适的隔离，例如隔离沟槽隔离。使用掩埋p型层（图中示出本发明的图中的TN3），在场氧化物的下面，将基底与集电体之间，集电体的底部接触区域和集电体的底部之间的连接制成。因为硅化物和重注入物p +植入物仅存在于基极接触点处，所以复合电流降低。这与已知装置的电流损耗相比降低了电流损耗。另外，通过在集成逻辑器件中放置靠近上侧自己的NPN晶体管的发射极的深基极注入也可以提高电流增益。底座的面积和收集器的面积被去耦合，即可以独立地调整基极到集电极区域和基极接触面积，以控制总基极电流，从而允许I2L栅极的布局优化更多的自由度，并允许更优化I2L门增益的自由度。

6. 发明授权

US06815302B2 Method of making a bipolar transistor with an oxygen implanted emitter window 有权
标题翻译：制造具有氧注入发射器窗口的双极晶体管的方法
公开(公告)号：US06815302B2
公开(公告)日：2004-11-09
申请号：US10028614
申请日：2001-12-21
申请人： Alan Sangone Chen , Yih-Feng Chyan , Chung Wai Leung , Yi Ma , William John Nagy
发明人： Alan Sangone Chen , Yih-Feng Chyan , Chung Wai Leung , Yi Ma , William John Nagy
IPC分类号： H01L218228
CPC分类号： H01L29/66272 , H01L21/8249 , H01L27/0635 , H01L29/7375
摘要： The present invention provides a method of manufacturing a bipolar transistor. The method may comprise forming a collector in a semiconductor wafer substrate, forming a base in the collector, implanting an oxide region within said collector and over the base, and forming an emitter over the substrate such that the oxide region is located between the emitter and the base.
摘要翻译：本发明提供一种制造双极晶体管的方法。该方法可以包括在半导体晶片衬底中形成集电极，在集电极中形成基极，在所述集电极内部和底部上注入氧化物区域，并在衬底上形成发射极，使得氧化物区域位于发射极和发射极之间的基地。

7. 发明授权

US06596600B1 Integrated injection logic semiconductor device and method of fabricating the same 有权
标题翻译：集成注入逻辑半导体器件及其制造方法
公开(公告)号：US06596600B1
公开(公告)日：2003-07-22
申请号：US09182520
申请日：1998-10-30
申请人： Takayuki Gomi
发明人： Takayuki Gomi
IPC分类号： H01L218228
CPC分类号： H01L27/0233
摘要： A logic circuit is formed of an I2L cell structure in which a difference of switching speeds at every collectors in a multi-collector structure is small. In a semiconductor device in which an integrated injection logic cell including a constant current source transistor and a switch transistor is formed on a common semiconductor substrate, a first semiconductor layer (13) doped with a first conductivity type impurity and a second semiconductor layer (19) doped with a second conductivity impurity are electrically isolated from each other on a semiconductor substrate. A plurality of collector electrodes of the switch transistor and a plurality of collector regions (20) based on diffusion of impurity are formed by the second semiconductor layer (19). The first semiconductor layer (13) includes a base electrode deriving portion, and a direct contact portion which directly contacts with the semiconductor substrate between a plurality of collector regions (20). An external base region (17) is formed by diffusion of first conductivity type impurity from the direct contact portion.
摘要翻译：逻辑电路由I2L单元结构形成，其中多集电极结构中的每个集电极的开关速度差异小。在公共半导体衬底上形成有包括恒流源晶体管和开关晶体管的集成注入逻辑单元的半导体器件中，掺杂有第一导电型杂质的第一半导体层（13）和第二半导体层（19 ）掺杂有第二导电杂质在半导体衬底上彼此电隔离。由第二半导体层（19）形成开关晶体管的多个集电极和基于杂质扩散的多个集电极区域（20）。第一半导体层（13）包括基极导出部分和在多个集电极区域（20）之间与半导体衬底直接接触的直接接触部分。通过从直接接触部分扩散第一导电型杂质形成外部基极区（17）。

8. 发明授权

US06440811B1 Method of fabricating a poly-poly capacitor with a SiGe BiCMOS integration scheme 有权
标题翻译：使用SiGe BiCMOS集成方案制造多晶硅电容器的方法
公开(公告)号：US06440811B1
公开(公告)日：2002-08-27
申请号：US09745361
申请日：2000-12-21
申请人： Douglas Duane Coolbaugh , James Stuart Dunn , Stephen Arthur St. Onge
发明人： Douglas Duane Coolbaugh , James Stuart Dunn , Stephen Arthur St. Onge
IPC分类号： H01L218228
CPC分类号： H01L28/40 , H01L27/0635
摘要： A method for fabricating a poly-poly capacitor integrated with a BiCMOS process which includes forming a lower plate electrode of a poly-poly capacitor during deposition of a gate electrode of a CMOS transistor; and forming an upper SiGe plate electrode during growth of a SiGe base region of a heterojunction bipolar transistor.
摘要翻译：一种用于制造与BiCMOS工艺集成的多晶硅电容器的方法，包括在沉积CMOS晶体管的栅电极期间形成多晶硅电容器的下板电极; 以及在异质结双极晶体管的SiGe基区的生长期间形成上SiGe板电极。

9. 发明授权

US06297119B1 Semiconductor device and its manufacture 失效
标题翻译：半导体器件及其制造
公开(公告)号：US06297119B1
公开(公告)日：2001-10-02
申请号：US09369267
申请日：1999-08-06
申请人： Yutaka Tsutsui , Masaru Wakabayashi
发明人： Yutaka Tsutsui , Masaru Wakabayashi
IPC分类号： H01L218228
CPC分类号： H01L21/8249 , H01L21/82285 , H01L27/0623
摘要： The present invention discloses a semiconductor device having a PNP bipolar transistor and an NPN bipolar transistor having excellent transistor characteristics formed on the same semiconductor substrate, and a method of manufacturing the semiconductor device. This semiconductor device is provided with a first n-type well and a second n-type well formed at substantially the same depths in a semiconductor substrate, an NPN bipolar transistor formed within the first n-type well which uses the n-type well as its collector, a p-type well formed within the second n-type well, and a PNP bipolar transistor formed within the p-type well which uses the p-type well as its collector.
摘要翻译：本发明公开了一种具有PNP双极型晶体管的半导体器件和在同一半导体衬底上形成的具有优良晶体管特性的NPN双极晶体管，以及制造半导体器件的方法。该半导体器件设置有第一n型阱和在半导体衬底中基本上相同深度形成的第二n型阱，形成在第一n型阱内的NPN双极型晶体管，其使用n型阱作为其集电极，在第二n型阱内形成p型阱以及在p型阱中形成的使用p型阱作为其集电极的PNP双极晶体管。

10. 发明授权

US06174779B1 Method for manufacturing a lateral bipolar transistor 失效
标题翻译：横向双极晶体管的制造方法
公开(公告)号：US06174779B1
公开(公告)日：2001-01-16
申请号：US09267775
申请日：1999-03-15
申请人： Tomoaki Shino , Takashi Yamada , Makoto Yoshimi , Shigeru Kawanaka , Hideaki Nii , Kazumi Inoh , Tsuneaki Fuse , Sadayuki Yoshitomi , Mamoru Terauchi
发明人： Tomoaki Shino , Takashi Yamada , Makoto Yoshimi , Shigeru Kawanaka , Hideaki Nii , Kazumi Inoh , Tsuneaki Fuse , Sadayuki Yoshitomi , Mamoru Terauchi
IPC分类号： H01L218228
CPC分类号： H01L29/66265 , H01L21/84 , H01L27/1203 , H01L29/7317
摘要： In a lateral bipolar transistor, its emitter region, base region, link base region, and so forth, are made in self alignment with side walls of masks by using partly overlapping two mask patterns. Therefore, not relying on the mask alignment accuracy, these regions are made in a precisely controlled positional relation. Thus, the lateral bipolar transistor, thus obtained, is reduced in parasitic resistance of the base and parasitic junction capacitance between the emitter and the base, and alleviated in variance of characteristics caused by fluctuation of the length of a link base region, length of the emitter-base junction and relative positions of the emitter and the collector, and can be manufactured with a high reproducibility.
摘要翻译：在横向双极晶体管中，通过使用部分重叠的两个掩模图案，其发射极区域，基极区域，链路基极区域等与掩模的侧壁自对准。因此，不依赖于掩模对准精度，这些区域被精确控制位置关系。因此，如此获得的横向双极晶体管的基极的寄生电阻和发射极与基极之间的寄生结电容减小，并且由于链路基极区域的长度的波动引起的特性的变化减轻，发射极 - 基极结和发射极和集电极的相对位置，并且可以以高再现性制造。

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