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1. 发明授权

US06657281B1 Bipolar transistor with a low K material in emitter base spacer regions 失效
标题翻译：在发射极基极间隔区域中具有低K材料的双极晶体管
公开(公告)号：US06657281B1
公开(公告)日：2003-12-02
申请号：US09631755
申请日：2000-08-03
申请人： Yih-Feng Chyan , Chunchieh Huang , Chung Wai Leung , Yi Ma , Shahriar Moinian
发明人： Yih-Feng Chyan , Chunchieh Huang , Chung Wai Leung , Yi Ma , Shahriar Moinian
IPC分类号： H01L27082
CPC分类号： H01L29/66272 , H01L21/8249 , H01L29/0804
摘要： The present invention provides a bipolar transistor located on a semiconductor wafer substrate. The bipolar transistor may comprise a collector located in the semiconductor wafer substrate, a base located in the collector, and an emitter located on the base and in contact with at least a portion of the base, wherein the emitter has a low K layer located therein. The low K layer may be, for example, located proximate a side of the emitter, or it may be located proximate opposing sides of the emitter. In all embodiments, however, the low K layer does not interfere with the proper functioning of the bipolar transistor, and substantially reduces the emitter-base capacitance typically associated with conventional bipolar transistors.
摘要翻译：本发明提供一种位于半导体晶片基板上的双极晶体管。双极晶体管可以包括位于半导体晶片衬底中的集电极，位于集电极中的基极和位于基极上并与基极的至少一部分接触的发射极，其中发射极具有位于其中的低K层。例如，低K层可以位于靠近发射极的一侧，或者它可以位于发射极的相对侧附近。然而，在所有实施例中，低K层不干扰双极晶体管的正常功能，并且基本上减小了通常与常规双极晶体管相关联的发射极 - 基极电容。

2. 发明授权

US06815302B2 Method of making a bipolar transistor with an oxygen implanted emitter window 有权
标题翻译：制造具有氧注入发射器窗口的双极晶体管的方法
公开(公告)号：US06815302B2
公开(公告)日：2004-11-09
申请号：US10028614
申请日：2001-12-21
申请人： Alan Sangone Chen , Yih-Feng Chyan , Chung Wai Leung , Yi Ma , William John Nagy
发明人： Alan Sangone Chen , Yih-Feng Chyan , Chung Wai Leung , Yi Ma , William John Nagy
IPC分类号： H01L218228
CPC分类号： H01L29/66272 , H01L21/8249 , H01L27/0635 , H01L29/7375
摘要： The present invention provides a method of manufacturing a bipolar transistor. The method may comprise forming a collector in a semiconductor wafer substrate, forming a base in the collector, implanting an oxide region within said collector and over the base, and forming an emitter over the substrate such that the oxide region is located between the emitter and the base.
摘要翻译：本发明提供一种制造双极晶体管的方法。该方法可以包括在半导体晶片衬底中形成集电极，在集电极中形成基极，在所述集电极内部和底部上注入氧化物区域，并在衬底上形成发射极，使得氧化物区域位于发射极和发射极之间的基地。

3. 发明授权

US06451660B1 Method of forming bipolar transistors comprising a native oxide layer formed on a substrate by rinsing the substrate in ozonated water 有权
标题翻译：一种形成双极晶体管的方法，该方法包括通过在臭氧水中漂洗该衬底而在衬底上形成的自然氧化物层
公开(公告)号：US06451660B1
公开(公告)日：2002-09-17
申请号：US09591037
申请日：2000-06-09
申请人： Yi Ma , Yih-Feng Chyan , Chung Wai Leung , Jane Qian Liu , Timothy Scott Campbell
发明人： Yi Ma , Yih-Feng Chyan , Chung Wai Leung , Jane Qian Liu , Timothy Scott Campbell
IPC分类号： H01L2131
CPC分类号： H01L29/66272 , H01L21/02238 , H01L21/02255 , H01L21/02307 , H01L21/31675 , H01L29/0804
摘要： A bipolar device (10) includes an oxide layer (24) which is grown on the surface (16) of a semiconductor substrate (12) by immersing the surface in ozonated deionized water. By selecting an appropriate temperature of the water and concentration of the ozone, the thickness of the film can be maintained within fine tolerances from lot to lot, and over the surface of a wafer (W) comprising the substrate.
摘要翻译：双极器件（10）包括通过将表面浸入臭氧化去离子水中而在半导体衬底（12）的表面（16）上生长的氧化物层（24）。通过选择水的适当温度和臭氧的浓度，可以将薄膜的厚度保持在大量的精细公差之内，并且在包含基底的晶片（W）的表面上。

4. 发明授权

US06537887B2 Integrated circuit fabrication 有权
公开(公告)号：US06537887B2
公开(公告)日：2003-03-25
申请号：US09727325
申请日：2000-11-30
申请人： Yih-Feng Chyan , Chung Wai Leung , Yi Ma , Demi Nguyen
发明人： Yih-Feng Chyan , Chung Wai Leung , Yi Ma , Demi Nguyen
IPC分类号： H01L218222
CPC分类号： H01L29/66272 , H01L21/26506 , H01L21/31155 , H01L21/8249 , H01L27/0623
摘要： An integrated circuit and a process for making the same are provided. The circuit has a nitrogen implanted emitter window, wherein the nitrogen has been implanted into the emitter window after the emitter window etch, but prior to the emitter conductor deposition. Nitrogen implantation is expected to minimize oxide growth variation.

5. 发明授权

US06518622B1 Vertical replacement gate (VRG) MOSFET with a conductive layer adjacent a source/drain region and method of manufacture therefor 有权
标题翻译：具有邻近源极/漏极区的导电层的垂直替代栅极（VRG）MOSFET及其制造方法
公开(公告)号：US06518622B1
公开(公告)日：2003-02-11
申请号：US09528753
申请日：2000-03-20
申请人： Hongzong Chew , Yih-Feng Chyan , John M. Hergenrother , Yi Ma , Donald P. Monroe
发明人： Hongzong Chew , Yih-Feng Chyan , John M. Hergenrother , Yi Ma , Donald P. Monroe
IPC分类号： H01L2976
CPC分类号： H01L29/66666 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a VRG structure formed on a semiconductor wafer substrate. The VRG structure has a first source/drain region located in a semiconductor wafer substrate, and a conductive layer located adjacent the source/drain region, a second source/drain region and a conductive channel that extends from the first source/drain region to the second source/drain region. The conductive layer provides an electrical connection to the first source/drain region. The conductive layer may have a low sheet resistance that may be less than about 50 &OHgr;/square or less than about 20 &OHgr;/square, to the first source/drain region.
摘要翻译：本发明提供一种形成在半导体晶片基板上的VRG结构。 VRG结构具有位于半导体晶片衬底中的第一源极/漏极区域和位于源极/漏极区域附近的导电层，第二源极/漏极区域和导电沟道，其从第一源极/漏极区域延伸到第二源极/漏极区域。导电层提供到第一源/漏区的电连接。导电层可以具有低于第一源极/漏极区域的低电阻，其可以小于约50欧米亚/平方或小于约20欧米亚/平方。

6. 发明授权

US06274490B1 Method of manufacturing semiconductor devices having high pressure anneal 有权
标题翻译：制造具有高压退火的半导体器件的方法
公开(公告)号：US06274490B1
公开(公告)日：2001-08-14
申请号：US09521268
申请日：2000-03-08
申请人： Yih-Feng Chyan , Yi Ma
发明人： Yih-Feng Chyan , Yi Ma
IPC分类号： H01L2144
CPC分类号： H01L29/518 , H01L21/28176 , H01L21/3003 , H01L21/324 , H01L21/76826 , H01L21/76834
摘要： The present invention provides a method of passivating a semiconductor device having a capping layer formed thereover, comprising: (1) subjecting the semiconductor device to a high pressure within a pressure chamber and (2) exposing the semiconductor device to a passivating gas. The high pressure causes the passivating gas, such as a deuterated passivating gas, to penetrate the capping layer and thereby passivate the semiconductor device. The method provided by the present invention is, therefore, particularly useful in those instances where a final passivation step is desired after the formation of the capping layer. It is believed that the hydrogen isotope bonds to dangling bond sites within the semiconductor device, which are most often present at a silicon/silicon dioxide interface. Further, because of their larger mass, these hydrogen isotope atoms are not easily removed by electron flow during the operation of the device as is the case with the lighter hydrogen atoms.
摘要翻译：本发明提供一种钝化具有形成在其上的覆盖层的半导体器件的方法，包括：（1）使半导体器件在压力室内受到高压，以及（2）将半导体器件暴露于钝化气体。高压使诸如氘代钝化气体的钝化气体穿透封盖层，从而钝化半导体器件。因此，本发明提供的方法在形成覆盖层之后需要最终钝化步骤的情况下特别有用。据信氢同位素结合到半导体器件内的悬挂键合位置，其通常存在于硅/二氧化硅界面处。此外，由于它们的质量较大，与较轻的氢原子一样，这些氢同位素原子在器件的操作过程中不容易被电子流除去。

7. 发明授权

US08818132B2 Camera calibration with lens distortion from low-rank textures 有权
标题翻译：相机校准与低等级纹理的镜头失真
公开(公告)号：US08818132B2
公开(公告)日：2014-08-26
申请号：US13310729
申请日：2011-12-03
申请人： Zhengdong Zhang , Yasuyuki Matsushita , Yi Ma
发明人： Zhengdong Zhang , Yasuyuki Matsushita , Yi Ma
IPC分类号： G06K9/36 , G06T7/00
CPC分类号： G06T7/0018 , G06T7/80 , G06T2207/20104 , H04N17/002
摘要： A “Camera Calibrator” provides various techniques for recovering intrinsic camera parameters and distortion characteristics by processing a set of one or more input images. These techniques are based on extracting “Transform Invariant Low-Rank Textures” (TILT) from input images using high-dimensional convex optimization tools for matrix rank minimization and sparse signal recovery. The Camera Calibrator provides a simple, accurate, and flexible method to calibrate intrinsic parameters of a camera even with significant lens distortion, noise, errors, partial occlusions, illumination and viewpoint change, etc. Distortions caused by the camera can then be automatically corrected or removed from images. Calibration is achieved under a wide range of practical scenarios, including using multiple images of a known pattern, multiple images of an unknown pattern, single or multiple images of multiple patterns, etc. Significantly, calibration is achieved without extracting or manually identifying low-level features such as corners or edges from the calibration images.
摘要翻译： “相机校准器”提供了通过处理一组一个或多个输入图像来恢复本征相机参数和失真特性的各种技术。这些技术基于使用用于矩阵秩最小化和稀疏信号恢复的高维凸优化工具从输入图像中提取“变换不变低阶纹理”（TILT）。相机校准器提供了一种简单，准确和灵活的校准相机内在参数的方法，即使有明显的镜头失真，噪点，错误，部分遮挡，照明和视点更改等。然后可以自动更正相机造成的失真或从图像中删除在广泛的实际情况下实现校准，包括使用已知图案的多个图像，未知图案的多个图像，多个图案的单个或多个图像等。显着地，在不提取或手动识别低级别的情况下实现校准特征如校准图像的拐角或边缘。

8. 发明授权

US08426839B1 Conducting bridge random access memory (CBRAM) device structures 有权
标题翻译：传导桥随机存取存储器（CBRAM）器件结构
公开(公告)号：US08426839B1
公开(公告)日：2013-04-23
申请号：US12767552
申请日：2010-04-26
申请人： Yi Ma , Chakravarthy Gopalan , Antonio R. Gallo , Janet Wang
发明人： Yi Ma , Chakravarthy Gopalan , Antonio R. Gallo , Janet Wang
IPC分类号： H01L45/00 , H01L29/04 , H01L29/12
CPC分类号： H01L45/085 , H01L45/08 , H01L45/1233 , H01L45/1266 , H01L45/142 , H01L45/1608 , H01L45/165 , H01L45/1658 , H01L45/1675 , H01L45/1683
摘要： A conductive bridging memory cell may include an ion conductor layer formed over an active electrode that is a source of conductive ions for the ion conductor; a conductive layer; and a barrier layer formed below the active layer and in contact with the conductive, the barrier layer substantially preventing a movement of conductive ions therethrough.
摘要翻译：导电桥接存储单元可以包括在作为离子导体的导电离子源的有源电极上形成的离子导体层; 导电层; 以及形成在有源层下方并与导体接触的阻挡层，阻挡层基本上防止导电离子通过其移动。

9. 发明授权

US07871942B2 Methods for manufacturing high dielectric constant film 有权
标题翻译：制造高介电常数膜的方法
公开(公告)号：US07871942B2
公开(公告)日：2011-01-18
申请号：US12057113
申请日：2008-03-27
申请人： Shreyas S. Kher , Pravin K. Narwankar , Khaled Z. Ahmed , Yi Ma
发明人： Shreyas S. Kher , Pravin K. Narwankar , Khaled Z. Ahmed , Yi Ma
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/31645 , C23C14/083 , C23C16/56 , H01L21/3141
摘要： Processes for making a high K (dielectric constant) film using an ultra-high purity hafnium containing organometallic compound are disclosed. Also described are devices incorporating high K films made with high purity hafnium containing organometallic compounds.
摘要翻译：公开了使用含有超高纯度铪的有机金属化合物制造高K（介电常数）膜的方法。还描述了包含用高纯度铪含有有机金属化合物制成的高K膜的装置。

10. 发明授权

US07659158B2 Atomic layer deposition processes for non-volatile memory devices 失效
标题翻译：用于非易失性存储器件的原子层沉积工艺
公开(公告)号：US07659158B2
公开(公告)日：2010-02-09
申请号：US12059782
申请日：2008-03-31
申请人： Yi Ma , Shreyas S. Kher , Khaled Ahmed , Tejal Goyani , Maitreyee Mahajani , Jallepally Ravi , Yi-Chiau Huang
发明人： Yi Ma , Shreyas S. Kher , Khaled Ahmed , Tejal Goyani , Maitreyee Mahajani , Jallepally Ravi , Yi-Chiau Huang
IPC分类号： H01L21/8238 , H01L29/788
CPC分类号： H01L29/42324 , H01L21/28273 , H01L29/7881
摘要： Embodiments of the invention provide memory devices and methods for forming memory devices. In one embodiment, a memory device is provided which includes a floating gate polysilicon layer disposed over source/drain regions of a substrate, a silicon oxynitride layer disposed over the floating gate polysilicon layer, a first aluminum oxide layer disposed over the silicon oxynitride layer, a hafnium silicon oxynitride layer disposed over the first aluminum oxide layer, a second aluminum oxide layer disposed over the hafnium silicon oxynitride layer, and a control gate polysilicon layer disposed over the second aluminum oxide layer. In another embodiment, a memory device is provided which includes a control gate polysilicon layer disposed over an inter-poly dielectric stack disposed over a silicon oxide layer disposed over the floating gate polysilicon layer. The inter-poly dielectric stack contains two silicon oxynitride layers separated by a silicon nitride layer.
摘要翻译：本发明的实施例提供了用于形成存储器件的存储器件和方法。在一个实施例中，提供了一种存储器件，其包括设置在衬底的源极/漏极区域上的浮置栅极多晶硅层，设置在浮置栅极多晶硅层上的氧氮化硅层，设置在氧氮化硅层上的第一氧化铝层，设置在所述第一氧化铝层上的铪硅氮化物层，设置在所述铪硅氮氧化物层上的第二氧化铝层，以及设置在所述第二氧化铝层上的控制栅极多晶硅层。在另一个实施例中，提供了一种存储器件，其包括设置在布置在浮置多晶硅层上方的氧化硅层上的多晶硅介质叠层之间的控制栅极多晶硅层。多晶硅间介质堆叠包含由氮化硅层分隔的两个氮氧化硅层。

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