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1. 发明授权

US06451660B1 Method of forming bipolar transistors comprising a native oxide layer formed on a substrate by rinsing the substrate in ozonated water 有权
标题翻译：一种形成双极晶体管的方法，该方法包括通过在臭氧水中漂洗该衬底而在衬底上形成的自然氧化物层
公开(公告)号：US06451660B1
公开(公告)日：2002-09-17
申请号：US09591037
申请日：2000-06-09
申请人： Yi Ma , Yih-Feng Chyan , Chung Wai Leung , Jane Qian Liu , Timothy Scott Campbell
发明人： Yi Ma , Yih-Feng Chyan , Chung Wai Leung , Jane Qian Liu , Timothy Scott Campbell
IPC分类号： H01L2131
CPC分类号： H01L29/66272 , H01L21/02238 , H01L21/02255 , H01L21/02307 , H01L21/31675 , H01L29/0804
摘要： A bipolar device (10) includes an oxide layer (24) which is grown on the surface (16) of a semiconductor substrate (12) by immersing the surface in ozonated deionized water. By selecting an appropriate temperature of the water and concentration of the ozone, the thickness of the film can be maintained within fine tolerances from lot to lot, and over the surface of a wafer (W) comprising the substrate.
摘要翻译：双极器件（10）包括通过将表面浸入臭氧化去离子水中而在半导体衬底（12）的表面（16）上生长的氧化物层（24）。通过选择水的适当温度和臭氧的浓度，可以将薄膜的厚度保持在大量的精细公差之内，并且在包含基底的晶片（W）的表面上。

2. 发明授权

US06537887B2 Integrated circuit fabrication 有权
公开(公告)号：US06537887B2
公开(公告)日：2003-03-25
申请号：US09727325
申请日：2000-11-30
申请人： Yih-Feng Chyan , Chung Wai Leung , Yi Ma , Demi Nguyen
发明人： Yih-Feng Chyan , Chung Wai Leung , Yi Ma , Demi Nguyen
IPC分类号： H01L218222
CPC分类号： H01L29/66272 , H01L21/26506 , H01L21/31155 , H01L21/8249 , H01L27/0623
摘要： An integrated circuit and a process for making the same are provided. The circuit has a nitrogen implanted emitter window, wherein the nitrogen has been implanted into the emitter window after the emitter window etch, but prior to the emitter conductor deposition. Nitrogen implantation is expected to minimize oxide growth variation.

3. 发明授权

US06815302B2 Method of making a bipolar transistor with an oxygen implanted emitter window 有权
标题翻译：制造具有氧注入发射器窗口的双极晶体管的方法
公开(公告)号：US06815302B2
公开(公告)日：2004-11-09
申请号：US10028614
申请日：2001-12-21
申请人： Alan Sangone Chen , Yih-Feng Chyan , Chung Wai Leung , Yi Ma , William John Nagy
发明人： Alan Sangone Chen , Yih-Feng Chyan , Chung Wai Leung , Yi Ma , William John Nagy
IPC分类号： H01L218228
CPC分类号： H01L29/66272 , H01L21/8249 , H01L27/0635 , H01L29/7375
摘要： The present invention provides a method of manufacturing a bipolar transistor. The method may comprise forming a collector in a semiconductor wafer substrate, forming a base in the collector, implanting an oxide region within said collector and over the base, and forming an emitter over the substrate such that the oxide region is located between the emitter and the base.
摘要翻译：本发明提供一种制造双极晶体管的方法。该方法可以包括在半导体晶片衬底中形成集电极，在集电极中形成基极，在所述集电极内部和底部上注入氧化物区域，并在衬底上形成发射极，使得氧化物区域位于发射极和发射极之间的基地。

4. 发明授权

US06657281B1 Bipolar transistor with a low K material in emitter base spacer regions 失效
标题翻译：在发射极基极间隔区域中具有低K材料的双极晶体管
公开(公告)号：US06657281B1
公开(公告)日：2003-12-02
申请号：US09631755
申请日：2000-08-03
申请人： Yih-Feng Chyan , Chunchieh Huang , Chung Wai Leung , Yi Ma , Shahriar Moinian
发明人： Yih-Feng Chyan , Chunchieh Huang , Chung Wai Leung , Yi Ma , Shahriar Moinian
IPC分类号： H01L27082
CPC分类号： H01L29/66272 , H01L21/8249 , H01L29/0804
摘要： The present invention provides a bipolar transistor located on a semiconductor wafer substrate. The bipolar transistor may comprise a collector located in the semiconductor wafer substrate, a base located in the collector, and an emitter located on the base and in contact with at least a portion of the base, wherein the emitter has a low K layer located therein. The low K layer may be, for example, located proximate a side of the emitter, or it may be located proximate opposing sides of the emitter. In all embodiments, however, the low K layer does not interfere with the proper functioning of the bipolar transistor, and substantially reduces the emitter-base capacitance typically associated with conventional bipolar transistors.
摘要翻译：本发明提供一种位于半导体晶片基板上的双极晶体管。双极晶体管可以包括位于半导体晶片衬底中的集电极，位于集电极中的基极和位于基极上并与基极的至少一部分接触的发射极，其中发射极具有位于其中的低K层。例如，低K层可以位于靠近发射极的一侧，或者它可以位于发射极的相对侧附近。然而，在所有实施例中，低K层不干扰双极晶体管的正常功能，并且基本上减小了通常与常规双极晶体管相关联的发射极 - 基极电容。

5. 发明授权

US06555871B1 Flash memory device having a bipolar transistor formed integral thereto and a method of manufacture therefor 有权
标题翻译：具有与之形成一体的双极晶体管的闪存器件及其制造方法
公开(公告)号：US06555871B1
公开(公告)日：2003-04-29
申请号：US09488108
申请日：2000-01-20
申请人： Yih-Feng Chyan , Chung Wai Leung , Ranbir Singh
发明人： Yih-Feng Chyan , Chung Wai Leung , Ranbir Singh
IPC分类号： H01L29792
CPC分类号： H01L27/11526 , H01L27/0623 , H01L27/115 , H01L27/11521 , H01L27/11546
摘要： The present invention provides a bipolar transistor for use in increasing a speed of a flash memory cell having a source region and a drain region and first and second complementary tubs. In one embodiment, a base for the bipolar transistor is located in the first complementary tub. The first complementary tub functions as a collector for the bipolar transistor. The bipolar transistor base also uniquely functions as the source region. The bipolar transistor's emitter is also located in the first complementary tub and proximate the base. For example, the emitter may be located adjacent the base or actually located in the base. In an additional embodiment, the opposing bases and emitters are located on opposing sides of and proximate to the flash memory cell.
摘要翻译：本发明提供了一种双极晶体管，用于增加具有源极区和漏极区以及第一和第二互补阱的闪存单元的速度。在一个实施例中，双极晶体管的基极位于第一互补槽中。第一个辅助槽用作双极晶体管的集电极。双极晶体管基极也独特地用作源极区域。双极晶体管的发射极也位于第一个补充槽中，靠近基极。例如，发射器可以位于基座附近或实际位于基底中。在另外的实施例中，相对的基座和发射器位于快闪存储器单元的相对侧并且靠近闪存单元。

6. 发明授权

US07897659B2 Water-based moldable modeling dough and method preparing therefor 失效
标题翻译：水性可模塑造型面团及其制备方法
公开(公告)号：US07897659B2
公开(公告)日：2011-03-01
申请号：US12358248
申请日：2009-01-23
申请人： Chung Wai Leung
发明人： Chung Wai Leung
IPC分类号： C08J9/32
CPC分类号： C08K5/1545 , C08K7/22 , C08L29/04 , C08L31/04
摘要： A water-based moldable modeling dough includes polyvinyl alcohol (PVA), vinyl acetate resin, water, maltose, maltitol, and hollow microspheres each with a diameter about 5-100 μm.
摘要翻译：水性可成型造型面团包括直径约5-100μm的聚乙烯醇（PVA），乙酸乙烯酯树脂，水，麦芽糖，麦芽糖醇和中空微球。

7. 发明授权

US06700143B2 Dummy structures that protect circuit elements during polishing 有权
标题翻译：在抛光期间保护电路元件的虚拟结构
公开(公告)号：US06700143B2
公开(公告)日：2004-03-02
申请号：US10165741
申请日：2002-06-06
申请人： Hsing Ti Tuan , Chung Wai Leung
发明人： Hsing Ti Tuan , Chung Wai Leung
IPC分类号： H01L31119
CPC分类号： H01L27/11526 , H01L21/31053 , H01L21/823462 , H01L27/105 , H01L27/115 , H01L27/11546 , Y10S438/926
摘要： Circuit elements (e.g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.
摘要翻译：形成在半导体衬底上的电路元件（例如晶体管栅极）在上覆电介质的机械或化学机械抛光期间被相邻的虚设结构保护。

8. 发明授权

US07511333B2 Nonvolatile memory cell with multiple floating gates and a connection region in the channel 有权
标题翻译：具有多个浮动栅极和通道中的连接区域的非易失性存储单元
公开(公告)号：US07511333B2
公开(公告)日：2009-03-31
申请号：US11246447
申请日：2005-10-06
申请人： Yue-Song He , Chung Wai Leung , Jin-Ho Kim , Kwok Kwok Ng
发明人： Yue-Song He , Chung Wai Leung , Jin-Ho Kim , Kwok Kwok Ng
IPC分类号： H01L27/115 , H01L29/66
CPC分类号： H01L29/42336 , G11C16/0458 , G11C16/0491 , H01L27/115 , H01L27/11521
摘要： A memory cell (110) has a plurality of floating gates (120L, 120R). The channel region (170) comprises a plurality of sub-regions (220L, 220R) adjacent to the respective floating gates, and a connection region (210) between the floating gates. The connection region has the same conductivity type as the source/drain regions (160) to increase the channel conductivity. Therefore, the floating gates can be brought closer together even though the inter-gate dielectric (144) becomes thick between the floating gates, weakening the control gate's (104) electrical field in the channel.
摘要翻译：存储单元（110）具有多个浮动栅极（120L，120R）。沟道区域（170）包括与相应浮动栅极相邻的多个子区域（220L，220R），以及浮置栅极之间的连接区域（210）。连接区域具有与源极/漏极区域（160）相同的导电类型以增加沟道导电性。因此，即使栅极间电介质（144）在浮置栅极之间变厚，削弱了沟道中的控制栅极（104）电场，浮动栅极也可以更靠近在一起。

9. 发明授权

US06962848B2 Nonvolatile memory structures and fabrication methods 有权
标题翻译：非易失性存储器结构和制造方法
公开(公告)号：US06962848B2
公开(公告)日：2005-11-08
申请号：US10689908
申请日：2003-10-20
申请人： Chung Wai Leung , Chia-Shun Hsiao , Vei-Han Chan
发明人： Chung Wai Leung , Chia-Shun Hsiao , Vei-Han Chan
IPC分类号： H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.
摘要翻译：为了制造半导体存储器，在半导体衬底上形成一对或多对第一结构。每个第一结构包括（a）存储器单元的多个浮动栅极和（b）为存储器单元提供控制栅极的第一导电线。控制门覆盖浮动门。每对第一结构对应于多个掺杂区域，每个掺杂区域向存储单元提供源极/漏极区域，该存储器单元具有在一个或者结构中的浮动栅极和控制栅极，并且源极/漏极区域到具有浮置和/ 在另一个结构中控制门。对于每对，形成第二导线，其底表面在两个结构之间延伸并物理地接触对应的第一掺杂区域。在一些实施例中，第一掺杂区域被绝缘沟槽分开。第二导线可以形成至少部分地填充两个第一结构之间的区域的导电插塞。

10. 发明授权

US06566196B1 Sidewall protection in fabrication of integrated circuits 有权
标题翻译：集成电路制造中的侧壁保护
公开(公告)号：US06566196B1
公开(公告)日：2003-05-20
申请号：US10146979
申请日：2002-05-15
申请人： Barbara Haselden , Chia-Shun Hsiao , Chunchieh Huang , Jin-Ho Kim , Chung Wai Leung , Kuei-Chang Tsai
发明人： Barbara Haselden , Chia-Shun Hsiao , Chunchieh Huang , Jin-Ho Kim , Chung Wai Leung , Kuei-Chang Tsai
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324 , Y10S438/954
摘要： In a nonvolatile memory, a floating gate (124) is covered with ONO (98), and a control gate polysilicon layer (124) is formed on the ONO. After the control gate is patterned, the control gate sidewalls are oxidized to form a protective layer (101) of silicon dioxide. This oxide protects the control gate polysilicon during a subsequent etch of the silicon nitride portion (98.2) of the ONO. Therefore, the silicon nitride can be removed with an isotropic etch. A potential damage to the substrate isolation dielectric (210) is therefore reduced. Other embodiments are also provided.
摘要翻译：在非易失性存储器中，浮动栅极（124）被ONO（98）覆盖，并且在ONO上形成控制栅多晶硅层（124）。在控制栅极被图案化之后，控制栅极侧壁被氧化以形成二氧化硅的保护层（101）。该氧化物在ONO的氮化硅部分（98.2）的随后蚀刻期间保护控制栅极多晶硅。因此，可以用各向同性蚀刻去除氮化硅。因此，减小了对衬底隔离电介质（210）的潜在损害。还提供了其他实施例。

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