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1. 发明授权

US07491610B2 Fabrication method 有权
标题翻译：制作方法
公开(公告)号：US07491610B2
公开(公告)日：2009-02-17
申请号：US11809873
申请日：2007-06-01
申请人： Samir Chaudhry , Paul Arthur Layman , John Russell McMacken , J. Ross Thomson , Jack Qingsheng Zhao
发明人： Samir Chaudhry , Paul Arthur Layman , John Russell McMacken , J. Ross Thomson , Jack Qingsheng Zhao
IPC分类号： H01L21/8232
CPC分类号： H01L29/66666 , H01L27/0629 , H01L27/10808 , H01L27/10852 , H01L27/10861 , H01L27/10873 , H01L27/10876 , H01L28/60 , H01L29/66181 , H01L29/945
摘要： A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. The integrated circuit structure includes a semiconductor layer with a major surface and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. The integrated circuit includes a capacitor having a bottom plate, dielectric layer and a top plate. In an associated method of manufacture, a first device region. is formed on a semiconductor layer. A field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers and a dielectric layer is formed on the semiconductor layer.
摘要翻译：与集成电路中使用的垂直MOSFET器件和电容器相关的工艺和架构。集成电路结构包括具有主表面的半导体层，并且还包括形成在表面中的第一掺杂区域。与第一掺杂区域不同的导电类型的第二掺杂区域位于第一区域上方。与第二区域不同的导电类型的第三掺杂区域位于第二区域上方。集成电路包括具有底板，电介质层和顶板的电容器。在相关的制造方法中，第一装置区域。形成在半导体层上。在第一器件区域上形成场效应晶体管栅极区域。在半导体层上形成包括顶层和底层的电容器和电介质层。

2. 发明申请

US20070238243A1 Fabrication method 有权
标题翻译：制作方法
公开(公告)号：US20070238243A1
公开(公告)日：2007-10-11
申请号：US11809873
申请日：2007-06-01
申请人： Samir Chaudhry , Paul Layman , John McMacken , J. Thomson , Jack Zhao
发明人： Samir Chaudhry , Paul Layman , John McMacken , J. Thomson , Jack Zhao
IPC分类号： H01L21/765
CPC分类号： H01L29/66666 , H01L27/0629 , H01L27/10808 , H01L27/10852 , H01L27/10861 , H01L27/10873 , H01L27/10876 , H01L28/60 , H01L29/66181 , H01L29/945
摘要： A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate. In an associated method of manufacture, a first device region, selected from the group consisting of the source region and a drain region of a field-effect transistor is formed on a semiconductor layer. A first field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers with a dielectric layer disposed therebetween, is also formed on the semiconductor layer. In another embodiment, the capacitor layers are formed within a trench or window formed in the semiconductor layer.
摘要翻译：与集成电路中使用的垂直MOSFET器件和电容器相关的工艺和架构。通常，集成电路结构包括具有沿其平面形成的主表面的半导体层，并且还包括形成在表面中的第一掺杂区域。与第一掺杂区域不同的导电类型的第二掺杂区域位于第一区域上方。与第二区域不同的导电类型的第三掺杂区域位于第二区域上方。在本发明的一个实施例中，半导体器件包括第一层半导体材料和第一场效应晶体管，其具有形成在第一层中的第一源/漏区。在第一层上形成晶体管的沟道区，并且在沟道区上形成相关联的第二源极/漏极区。集成电路还包括具有底板，电介质层和顶部电容器板的电容器。在相关联的制造方法中，在半导体层上形成从由场效应晶体管的源极区域和漏极区域中选择的第一器件区域。第一场效应晶体管栅极区域形成在第一器件区域上。在半导体层上还形成有包括设置在其间的介电层的顶层和底层的电容器。在另一个实施例中，电容器层形成在形成在半导体层中的沟槽或窗口内。

3. 发明申请

US20070111414A1 A Vertical Replacement-Gate Silicon-On-Insulator Transistor 有权
标题翻译：垂直替代栅极硅绝缘体晶体管
公开(公告)号：US20070111414A1
公开(公告)日：2007-05-17
申请号：US11419356
申请日：2006-05-19
申请人： Samir Chaudhry , Paul Layman , John McMacken , J. Thomson , Jack Zhao
发明人： Samir Chaudhry , Paul Layman , John McMacken , J. Thomson , Jack Zhao
IPC分类号： H01L21/337
CPC分类号： H01L29/42392 , H01L21/84 , H01L27/1203 , H01L29/66666 , H01L29/7827 , H01L29/78642
摘要： An architecture for creating a vertical silicon-on-insulator MOSFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain contact region formed in the surface. A relatively thin single crystalline layer is oriented vertically above the major surface and comprises a first source/drain doped region over which is located a doped channel region, over which is located a second source/drain region. An insulating layer is disposed adjacent said first and said second source/drain regions and said channel region, serving as the insulating material of the SOI device. In another embodiment, insulating material is adjacent only said first and said second source/drain regions. A conductive region is adjacent the channel region for connecting the back side of the channel region to ground, for example, to prevent the channel region from floating. In an associated method of manufacturing the semiconductor device, a first source/drain region is formed in a relatively thin vertical layer of single crystalline material. A MOSFET gate region, including a channel and a gate electrode, is formed over the first source/drain region. A second source/drain region is then formed over the channel, the regions being appropriately doped to effect MOSFET action.
摘要翻译：一种用于创建垂直绝缘体上硅的MOSFET的架构。通常，集成电路结构包括具有沿着平面形成的主表面的半导体区域和形成在表面中的第一源极/漏极接触区域。相对薄的单晶层在主表面上垂直取向，并且包括第一源极/漏极掺杂区域，在该第一源极/漏极掺杂区域上定位有掺杂沟道区，其上定位有第二源极/漏极区。邻近所述第一和第二源极/漏极区域和所述沟道区域设置绝缘层，用作SOI器件的绝缘材料。在另一个实施例中，绝缘材料仅与所述第一和所述第二源极/漏极区相邻。导电区域与通道区域相邻，用于将沟道区域的背面连接到地，例如以防止沟道区域浮动。在制造半导体器件的相关方法中，第一源极/漏极区形成在相对薄的单晶材料垂直层中。在第一源极/漏极区域上形成包括沟道和栅电极的MOSFET栅极区域。然后在该通道上形成第二源极/漏极区域，该区域被适当地掺杂以实现MOSFET的动作。

4. 发明授权

US07049199B2 Method of ion implantation for achieving desired dopant concentration 有权
公开(公告)号：US07049199B2
公开(公告)日：2006-05-23
申请号：US10619058
申请日：2003-07-14
申请人： Paul Arthur Layman , Samir Chaudhry
发明人： Paul Arthur Layman , Samir Chaudhry
IPC分类号： H01L21/336 , H01L21/265
CPC分类号： H01L21/823807 , H01L21/2652 , H01L21/26586 , H01L21/823892
摘要： A method for forming a plurality of MOSFETs wherein each one of the MOSFET has a unique predetermined threshold voltage. A doped well or tub is formed for each MOSFET. A patterned mask is then used to form a material line proximate each semiconductor well, wherein the width of the line is dependent upon the desired threshold voltage for the MOSFET. A tilted ion implantation is performed at an acute angle with respect to the substrate surface such that the ion beam passes through the material line. Thicker lines have a lower transmission coefficient for the ion beam and thus the intensity of the ion beam reaching the adjacent semiconductor well is reduced. By appropriate selection of the line width the dopant density in the well, and thus the final MOSFET threshold voltage, is controllable.

5. 发明授权

US07033877B2 Vertical replacement-gate junction field-effect transistor 失效
公开(公告)号：US07033877B2
公开(公告)日：2006-04-25
申请号：US10723547
申请日：2003-11-26
申请人： Samir Chaudhry , Paul Arthur Layman , John Russell McMacken , Ross Thomson , Jack Qingsheng Zhao
发明人： Samir Chaudhry , Paul Arthur Layman , John Russell McMacken , Ross Thomson , Jack Qingsheng Zhao
IPC分类号： H01L21/8238 , H01L21/332 , H01L21/337
CPC分类号： H01L29/66909 , H01L21/823487 , H01L27/088 , H01L27/098 , H01L29/42392 , H01L29/66545 , H01L29/66742 , H01L29/78642 , H01L29/8083
摘要： An architecture for creating a vertical JFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain doped region formed in the surface. A second doped region forming a channel of different conductivity type than the first region is positioned over the first region. A third doped region is formed over the second doped region having an opposite conductivity type with respect to the second doped region, and forming a source/drain region. A gate is formed over the channel to form a vertical JFET.In an associated method of manufacturing the semiconductor device, a first source/drain region is formed in a semiconductor layer. A field-effect transistor gate region, including a channel and a gate electrode, is formed over the first source/drain region. A second source/drain region is then formed over the channel having the appropriate conductivity type.

6. 发明申请

US20050164516A1 Method and structure for graded gate oxides on vertical and non-planar surfaces 有权
标题翻译：垂直和非平面表面上分级栅极氧化物的方法和结构
公开(公告)号：US20050164516A1
公开(公告)日：2005-07-28
申请号：US10986984
申请日：2004-11-12
申请人： Samir Chaudhry , Pradip Roy
发明人： Samir Chaudhry , Pradip Roy
IPC分类号： C30B33/00 , H01L21/28 , H01L21/316 , H01L21/321 , H01L21/336 , H01L29/51 , H01L29/78 , H01L21/31 , H01L21/469
CPC分类号： H01L29/66666 , C30B29/06 , C30B33/005 , H01L21/02238 , H01L21/02255 , H01L21/28167 , H01L21/28194 , H01L21/31662 , H01L21/32105 , H01L29/513 , H01L29/518 , H01L29/7827
摘要： A method for forming an oxide layer on a vertical, non-planar semiconductor surface provides a low stress oxide layer having a pristine interface characterized by a roughness of less than 3 angstroms. The oxide layer includes a portion that is substantially amorphous and notably dense. The oxide layer is a graded growth oxide layer including a composite of a first oxide portion formed at a relatively low temperature below the viscoelastic temperature of the oxide film and a second oxide portion formed at a relatively high temperature above the viscoelastic temperature of the oxide film. The process for forming the oxide layer includes thermally oxidizing at a first temperature below the viscoelastic temperature of the film, and slowly ramping up the temperature to a second temperature above the viscoelastic temperature of the film and heating at the second temperature. After the second, high temperature oxidation above the viscoelastic temperature, the structure is then slowly cooled under gradual, modulated cooling conditions.
摘要翻译：在垂直非平面半导体表面上形成氧化物层的方法提供了具有粗糙度小于3埃的原始界面的低应力氧化物层。氧化物层包括基本无定形且特别密集的部分。氧化物层是分级生长氧化物层，其包括在低于氧化膜的粘弹性温度的较低温度下形成的第一氧化物部分和在高于氧化膜的粘弹性温度的较高温度下形成的第二氧化物部分的复合物。用于形成氧化物层的方法包括在低于膜的粘弹性温度的第一温度下热氧化，并将温度缓慢升高到高于膜的粘弹性温度的第二温度并在第二温度下加热。第二次，高于粘弹性温度的高温氧化，然后在逐渐调节的冷却条件下缓慢冷却结构。

7. 发明授权

US6001701A Process for making bipolar having graded or modulated collector 失效
标题翻译：制备具有渐变或调制收集器的双极的方法
公开(公告)号：US6001701A
公开(公告)日：1999-12-14
申请号：US871385
申请日：1997-06-09
申请人： Michael Scott Carroll , Samir Chaudhry , Alan Sangone Chen , Yih-Feng Chyan , Kuo-Hua Lee , William John Nagy
发明人： Michael Scott Carroll , Samir Chaudhry , Alan Sangone Chen , Yih-Feng Chyan , Kuo-Hua Lee , William John Nagy
IPC分类号： H01L21/331 , H01L21/762 , H01L21/8249
CPC分类号： H01L29/66272 , H01L21/76218 , H01L21/8249 , Y10S148/009 , Y10S148/01 , Y10S148/011
摘要： A bipolar fabrication process, illustratively suited for integration into a conventional CMOS process to thereby form a BiCMOS integrated circuits is disclosed. The collector and base are formed through multiple implants and a single masking step to thereby provide a continuous low resistance collector region.
摘要翻译：公开了一种双极制造工艺，其示意性地适合于集成到常规CMOS工艺中，从而形成BiCMOS集成电路。集电极和基极通过多个注入和单个掩模步骤形成，从而提供连续的低电阻集电区。

8. 发明申请

US20090130810A1 Fabrication method 失效
标题翻译：制作方法
公开(公告)号：US20090130810A1
公开(公告)日：2009-05-21
申请号：US12319603
申请日：2009-01-09
申请人： Samir Chaudhry , Paul Arthur Layman , John Russell McMacken , J. Ross Thomson , Jack Qingsheng Zhao
发明人： Samir Chaudhry , Paul Arthur Layman , John Russell McMacken , J. Ross Thomson , Jack Qingsheng Zhao
IPC分类号： H01L21/336
CPC分类号： H01L29/66666 , H01L27/0629 , H01L27/10808 , H01L27/10852 , H01L27/10861 , H01L27/10873 , H01L27/10876 , H01L28/60 , H01L29/66181 , H01L29/945
摘要： A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. The integrated circuit structure includes a semiconductor layer with a major surface and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. The integrated circuit includes a capacitor having a bottom plate, dielectric layer and a top plate. In an associated method of manufacture, a first device region, is formed on a semiconductor layer. A field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers and a dielectric layer is formed on the semiconductor layer.
摘要翻译：与集成电路中使用的垂直MOSFET器件和电容器相关的工艺和架构。集成电路结构包括具有主表面的半导体层，并且还包括形成在表面中的第一掺杂区域。与第一掺杂区域不同的导电类型的第二掺杂区域位于第一区域上方。与第二区域不同的导电类型的第三掺杂区域位于第二区域上方。集成电路包括具有底板，电介质层和顶板的电容器。在相关联的制造方法中，在半导体层上形成第一器件区域。在第一器件区域上形成场效应晶体管栅极区域。在半导体层上形成包括顶层和底层的电容器和电介质层。

9. 发明申请

US20070228440A1 Structure and fabrication method for capacitors integratible with vertical replacement gate transistors 失效
公开(公告)号：US20070228440A1
公开(公告)日：2007-10-04
申请号：US11809686
申请日：2007-05-31
申请人： Samir Chaudhry , Paul Layman , John McMacken , J. Thomson , Jack Zhao
发明人： Samir Chaudhry , Paul Layman , John McMacken , J. Thomson , Jack Zhao
IPC分类号： H01L29/94
CPC分类号： H01L29/66666 , H01L27/0629 , H01L27/10808 , H01L27/10852 , H01L27/10861 , H01L27/10873 , H01L27/10876 , H01L28/60 , H01L29/66181 , H01L29/945
摘要： A process and an architecture related to a vertical MOSFET device and a capacitor for use in integrated circuits. Generally, the integrated circuit structure includes a semiconductor layer with a major surface formed along a plane thereof and further including a first doped region formed in the surface. A second doped region of a different conductivity type than the first doped region is positioned over the first region. A third doped region of a different conductivity type than the second region is positioned over the second region. In one embodiment of the invention, a semiconductor device includes a first layer of semiconductor material and a first field-effect transistor having a first source/drain region formed in the first layer. A channel region of the transistor is formed over the first layer and an associated second source/drain region is formed over the channel region. The integrated circuit further includes a capacitor having a bottom plate, dielectric layer and a top capacitor plate. In an associated method of manufacture, a first device region, selected from the group consisting of the source region and a drain region of a field-effect transistor is formed on a semiconductor layer. A first field-effect transistor gate region is formed over the first device region. A capacitor comprising top and bottom layers with a dielectric layer disposed therebetween, is also formed on the semiconductor layer. In another embodiment, the capacitor layers are formed within a trench or window formed in the semiconductor layer.

10. 发明申请

US20050170554A1 Multi-layer inductor formed in a semiconductor substrate and having a core of ferromagnetic material 有权
标题翻译：多层电感器形成在半导体衬底中并且具有铁磁材料的芯
公开(公告)号：US20050170554A1
公开(公告)日：2005-08-04
申请号：US10513121
申请日：2003-05-07
申请人： Michelle Griglione , Paul Layman , Mohamed Laradji , J. Thomson , Samir Chaudhry
发明人： Michelle Griglione , Paul Layman , Mohamed Laradji , J. Thomson , Samir Chaudhry
IPC分类号： H01L21/02 , H01L27/08 , H01L29/12 , H01L21/00 , H01L21/16
CPC分类号： B82Y10/00 , H01L27/08 , H01L28/10 , H01L29/127
摘要： A thin-film multilayer high-Q inductor having a ferromagnetic core and spanning at least three metal layers is formed by forming a plurality of parallel first metal runners on the semiconductor substrate. A plurality of first and second vertical conductive vias are formed in electrical connection with each end of the plurality of metal runners. A plurality of third and fourth conductive vias are formed over the plurality of first and second conductive vias and a plurality of second metal runners are formed interconnecting the plurality of third and fourth conductive vias. The first metal runners and second metal runners are oriented such that one end of a first metal runner is connected to an overlying end of a second metal runner by way of the first and third vertical conductive vias. The other end of the second metal runner is connected to the next metal one runner by way of the second and fourth vertical conductive vias., forming a continuously conductive structure having a generally helical shape. An inductor core is formed by first forming a silicon layer between each one of the plurality of first metal runners. A germanium layer is formed thereover and the structure is annealed, causing formation of quantum dots of germanium. A cobalt layer is then formed over the quantum dots and another anneal process drives the cobalt into the quantum dots, where it is captured to form the ferromagnetic core.
摘要翻译：通过在半导体衬底上形成多个平行的第一金属流道，形成具有铁磁芯并跨越至少三个金属层的薄膜多层高Q电感器。多个第一和第二垂直导电通孔形成为与多个金属流道的每个端部电连接。在多个第一和第二导电通孔之上形成多个第三和第四导电通孔，并且形成互连多个第三和第四导电通孔的多个第二金属流道。第一金属流道和第二金属流道被定向成使得第一金属流道的一端通过第一和第三垂直导电通孔连接到第二金属流道的上覆端。第二金属流道的另一端通过第二和第四垂直导电通孔连接到下一个金属一个流道，形成具有大致螺旋形状的连续导电结构。通过首先在多个第一金属流道中的每一个之间形成硅层来形成电感器芯。在其上形成锗层，结构退火，形成锗量子点。然后在量子点上形成钴层，另一个退火工艺将钴驱动到量子点中，在其中被捕获以形成铁磁芯。

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