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1. 发明申请

US20140063958A1 N-Channel Multi-Time Programmable Memory Devices 有权
标题翻译： N通道多时间可编程存储器件
公开(公告)号：US20140063958A1
公开(公告)日：2014-03-06
申请号：US13600792
申请日：2012-08-31
申请人： Yi He , Xiang Lu , Albert Bergemont
发明人： Yi He , Xiang Lu , Albert Bergemont
IPC分类号： G11C16/10
CPC分类号： G11C16/0408 , G11C2216/10
摘要： N-channel multi-time programmable memory devices having an N-conductivity type substrate, first and second P-conductivity type wells in the N-conductivity type substrate, N-conductivity type source and drain regions formed in the first P-conductivity type well, the source and drain regions being separated by a channel region, an oxide layer over the N-conductivity type substrate; and a floating gate extending over the channel region and over the second P-conductivity type well in the N-conductivity type substrate, the multi-time programmable memory cell being programmable by hot electron injection and erasable by hot hole injection.
摘要翻译：具有N-导电类型衬底，N导电类型衬底中的第一和第二P导电类型阱的N沟道多时间可编程存储器件，形成在第一P导电型阱中的N导电型源极和漏极区源极和漏极区域被沟道区域分隔，N导电型衬底上的氧化物层; 以及在N导电类型衬底中在沟道区域上延伸超过第二P导电类型的浮栅，多时间可编程存储单元可通过热电子注入进行编程，并可通过热空穴注入进行擦除。

2. 发明授权

US08975685B2 N-channel multi-time programmable memory devices 有权
标题翻译： N通道多时间可编程存储器件
公开(公告)号：US08975685B2
公开(公告)日：2015-03-10
申请号：US13600792
申请日：2012-08-31
申请人： Yi He , Xiang Lu , Albert Bergemont
发明人： Yi He , Xiang Lu , Albert Bergemont
IPC分类号： H01L29/788
CPC分类号： G11C16/0408 , G11C2216/10
摘要： N-channel multi-time programmable memory devices having an N-conductivity type substrate, first and second P-conductivity type wells in the N-conductivity type substrate, N-conductivity type source and drain regions formed in the first P-conductivity type well, the source and drain regions being separated by a channel region, an oxide layer over the N-conductivity type substrate; and a floating gate extending over the channel region and over the second P-conductivity type well in the N-conductivity type substrate, the multi-time programmable memory cell being programmable by hot electron injection and erasable by hot hole injection.
摘要翻译：具有N-导电类型衬底，N导电类型衬底中的第一和第二P导电类型阱的N沟道多时间可编程存储器件，形成在第一P导电型阱中的N导电型源极和漏极区源极和漏极区域被沟道区域分隔，N导电型衬底上的氧化物层; 以及在N导电类型衬底中在沟道区域上延伸超过第二P导电类型的浮栅，多时间可编程存储单元可通过热电子注入进行编程，并可通过热空穴注入进行擦除。

3. 发明授权

US08796767B1 Low-noise, high-gain semiconductor device incorporating BCD (bipolar-CMOS-DMOS) technology 有权
标题翻译：采用BCD（双极CMOS-DMOS）技术的低噪声，高增益半导体器件
公开(公告)号：US08796767B1
公开(公告)日：2014-08-05
申请号：US13153932
申请日：2011-06-06
申请人： Xiang Lu , Albert Bergemont
发明人： Xiang Lu , Albert Bergemont
IPC分类号： H01L21/70
CPC分类号： H01L21/28035 , H01L21/28105 , H01L21/70 , H01L27/0623 , H01L27/0705 , H01L29/4983
摘要： Techniques are described to form a low-noise, high-gain semiconductor device. In one or more implementations, the device includes a substrate including a first dopant material having a concentration ranging from about 1×1010/cm3 to about 1×1019/cm3. The substrate also includes at least two active regions formed proximate to a surface of the substrate. The at least two active regions include a second dopant material, which is different than the first dopant material. The device further includes a gate structure formed over the surface of the substrate between the active regions. The gate structure includes a doped polycrystalline layer and an oxide layer formed over the surface between the surface and the doped polycrystalline layer. The doped polycrystalline layer includes the first dopant material having a concentration ranging from about 1×1019/cm3 to about 1×1021/cm3.
摘要翻译：描述技术以形成低噪声，高增益半导体器件。在一个或多个实施方式中，该器件包括包含浓度范围为约1×10 10 / cm 3至约1×10 19 / cm 3的第一掺杂剂材料的衬底。衬底还包括靠近衬底的表面形成的至少两个有源区。所述至少两个有源区包括与第一掺杂剂材料不同的第二掺杂剂材料。该器件还包括形成在有源区域之间的衬底表面上的栅极结构。栅极结构包括掺杂多晶层和在表面和掺杂多晶层之间的表面上形成的氧化物层。掺杂多晶层包括浓度范围为约1×1019 / cm3至约1×1021 / cm3的第一掺杂剂材料。

4. 发明授权

US08630137B1 Dynamic trim method for non-volatile memory products 有权
标题翻译：非易失性存储器产品的动态修剪方法
公开(公告)号：US08630137B1
公开(公告)日：2014-01-14
申请号：US13028131
申请日：2011-02-15
申请人： Yi He , Larry Wang , Sean Lynch , Che-Ping Chen , Wei Zhao , Albert Bergemont
发明人： Yi He , Larry Wang , Sean Lynch , Che-Ping Chen , Wei Zhao , Albert Bergemont
IPC分类号： G11C29/00
CPC分类号： G11C29/00 , G11C29/006 , G11C29/028 , G11C29/50
摘要： A dynamic trim method includes testing a selected number of cells on a die with predetermined testing margins. Data from this testing is used to determine dynamic reference margins for improving yield. Advantageously, yield is improved by allowing functioning fast or slow units to pass wafer sort by applying the dynamic reference margins for varying processes.
摘要翻译：动态修剪方法包括以预定的测试余量测试在模具上的选定数量的单元。来自该测试的数据用于确定用于提高产量的动态参考余量。有利地，通过允许功能快速或慢速单元通过应用用于变化过程的动态参考边缘来通过晶片排序来提高产量。

5. 发明授权

US08940631B1 Methods of forming coaxial feedthroughs for 3D integrated circuits 有权
公开(公告)号：US08940631B1
公开(公告)日：2015-01-27
申请号：US13843608
申请日：2013-03-15
申请人： Uppili Sridhar , Albert Bergemont
发明人： Uppili Sridhar , Albert Bergemont
IPC分类号： H01L21/4763 , H01L21/48
CPC分类号： H01L23/481 , H01L21/486 , H01L23/49827 , H01L23/50 , H01L2224/16225
摘要： Methods of forming coaxial feedthroughs for 3d integrated circuits that provide excellent isolation of signal paths from the substrate and from adjacent feedthroughs. One method is to form a recess in a substrate and deposit alternate layers of insulation and conductive layers and then thin the substrate to make the layers available from both sides of the substrate, with the first metal layer forming the coaxial conductor and the second metal layer forming the central conductor. Alternatively the coaxial feedthroughs may be formed using a modified pillar process to form the coaxial conductor at the same time as the center conductor is formed so that the coaxial feedthrough is formed without requiring extra steps. Both processes are low temperature processes.

6. 发明申请

US20100178747A1 Minimum Cost Method for Forming High Density Passive Capacitors for Replacement of Discrete Board Capacitors Using a Minimum Cost 3D Wafer-to-Wafer Modular Integration Scheme 有权
标题翻译：使用最小成本的3D晶片到晶片模块化集成方案形成高密度无源电容器来替代离散电路板电容器的最小成本方法
公开(公告)号：US20100178747A1
公开(公告)日：2010-07-15
申请号：US12352679
申请日：2009-01-13
申请人： Joseph Paul Ellul , Khanh Tran , Albert Bergemont
发明人： Joseph Paul Ellul , Khanh Tran , Albert Bergemont
IPC分类号： H01L21/02
CPC分类号： H01L25/50 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/81 , H01L25/0657 , H01L27/0805 , H01L28/91 , H01L29/66181 , H01L29/945 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/81203 , H01L2224/81801 , H01L2224/81894 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2224/05552 , H01L2924/00
摘要： Passive, high density, 3d IC capacitor stacks and methods that provide the integration of capacitors and integrated circuits in a wafer to wafer bonding process that provides for the integration of capacitors formed on one wafer, alone or with active devices, with one or more integrated circuits on one or more additional wafers that may be stacked in accordance with the process. Wafer to wafer bonding is preferably by thermo-compression, with grinding and chemical mechanical polishing being used to simply aspects of the process of fabrication. Various features and alternate embodiments are disclosed.
摘要翻译：被动的，高密度的3d IC电容器堆叠和方法，其提供电容器和集成电路在晶片到晶片接合工艺中的集成，其提供了在一个晶片上单独或与有源器件形成的电容集成，其中一个或多个集成可以根据该过程堆叠的一个或多个另外的晶片上的电路。晶圆接合的晶片优选通过热压缩，通过研磨和化学机械抛光仅用于制造工艺的方面。公开了各种特征和替代实施例。

7. 发明授权

US06509606B1 Single poly EPROM cell having smaller size and improved data retention compatible with advanced CMOS process 失效
标题翻译：单个聚EPROM单元具有较小的尺寸和改进的数据保留，与先进的CMOS工艺兼容
公开(公告)号：US06509606B1
公开(公告)日：2003-01-21
申请号：US09053199
申请日：1998-04-01
申请人： Richard B. Merrill , Albert Bergemont , Min-hwa Chi
发明人： Richard B. Merrill , Albert Bergemont , Min-hwa Chi
IPC分类号： H01L29788
CPC分类号： H01L29/7883 , G11C2216/10 , H01L27/115
摘要： Leakage of a single-poly EPROM cell is prevented by eliminating field oxide isolating the source, channel, and drain from the control gate n-well, and by replacing field oxide surrounding the cell with a heavily doped surface isolation region. The EPROM cell also utilizes a floating gate having an open-rectangular floating gate portion over the control gate region, and a narrow floating gate portion over the channel and intervening silicon substrate. The surface area of the open-rectangular floating gate portion ensures a high coupling ratio with the control gate region. The small width of the narrow floating gate portion prevents formation of a sizeable leakage path between the n-well and the source, channel, and drain. To conserve surface area, the EPROM cell also eliminates the p+ contact region and the PLDD region in the control gate well of the conventional EPROM design. This is permitted because the VTp implant step is masked, permitting the control gate region to operate in accumulation mode during application of 5V programming voltages.
摘要翻译：通过消除从控制栅极n阱分离源极，沟道和漏极的场氧化物，并且通过用重掺杂的表面隔离区域代替围绕电池的场氧化物来防止单聚EPROM单元的泄漏。 EPROM单元还利用在控制栅极区域上具有开放矩形浮动栅极部分的浮动栅极，以及在沟道上方的窄浮动栅极部分和中间的硅衬底。开放式矩形浮动栅极部分的表面积确保与控制栅极区域的高耦合率。窄浮动栅极部分的小宽度防止在n阱和源极，沟道和漏极之间形成相当大的泄漏路径。为了节省表面积，EPROM单元还消除了常规EPROM设计中控制栅极中的p +接触区域和PLDD区域。这是允许的，因为VTp注入步骤被屏蔽，允许控制栅极区域在施加5V编程电压期间以累积模式工作。

8. 发明授权

US06507516B1 EEPROM memory cell embedded on core CMOS for analog applications 有权
标题翻译：嵌入在芯片CMOS上的EEPROM存储单元用于模拟应用
公开(公告)号：US06507516B1
公开(公告)日：2003-01-14
申请号：US09599145
申请日：2000-06-21
申请人： Albert Bergemont
发明人： Albert Bergemont
IPC分类号： G11C1134
CPC分类号： H01L27/11521 , G11C27/005 , G11C2216/10 , H01L27/115 , H01L27/11558 , H01L29/7883
摘要： A low-cost, novel electrically erasable programmable read only memory cell embedded on core complementary metal oxide silicon for analog applications. The EEPROM memory cell includes a first well of P-type conductivity. An N-well coupler region is formed within the first well of P-type conductivity. An N-well window region is formed within the first well of P-type conductivity and spaced apart from the N-well coupler region. A first P+type region formed within the N-well window region. A second P+type region formed within the N-well window region and spaced apart from the first P+type region. A first contact is used to couple a first bit line to the first P+type region. A second contact which is used to couple a second bit line to the second P+type region. A single polysilicon layer is disposed over the N-well coupler region and the N-well window region. This single polysilicon layer defines a floating gate of the electrically erasable programmable read only memory cell.
摘要翻译：一种低成本，新颖的电可擦除可编程只读存储器单元，嵌入在用于模拟应用的核心互补金属氧化物硅上。 EEPROM存储单元包括P型导电性的第一阱。在P型导电性的第一阱内形成N阱耦合器区域。在P型导电性的第一阱内形成N阱窗口区域，并且与N阱耦合器区域间隔开。形成在N阱窗口区域内的第一P +型区域。形成在N阱窗口区域内并与第一P +型区域间隔开的第二P +型区域。第一个触点用于将第一个位线耦合到第一个P +型区域。用于将第二位线耦合到第二P +型区域的第二触点。单个多晶硅层设置在N阱耦合器区域和N阱窗口区域上。该单个多晶硅层限定电可擦除可编程只读存储器单元的浮置栅极。

9. 发明授权

US06498084B2 Method of forming high density EEPROM cell 有权
标题翻译：形成高密度EEPROM单元的方法
公开(公告)号：US06498084B2
公开(公告)日：2002-12-24
申请号：US09855869
申请日：2001-05-14
申请人： Albert Bergemont
发明人： Albert Bergemont
IPC分类号： H01L213205
CPC分类号： H01L29/66825 , H01L21/28273 , H01L29/42324
摘要： A memory cell formed on a substrate with a well having drain and source regions and a channel therebetween, a control gate with a first portion overlying a first region of the channel proximate the drain region and a second portion overlying a second region of the channel proximate the source region, and a floating gate with a first portion overlying the first control gate portion, a second portion overlying a third region of the channel between the first and second regions, and a third portion overlying the second control gate portion. The floating gate also includes a fourth portion that extends generally vertical from the first portion to the second portion of the floating gate, and a fifth portion that extends generally vertical from the second portion to the third portion of the floating gate. Dielectrics separate the control and floating gate from each other and the substrate.
摘要翻译：存储单元，其形成在具有漏极和源极区域以及沟道之间的阱的衬底上，控制栅极，第一部分覆盖靠近漏极区域的沟道的第一区域，第二部分覆盖在通道的第二区域附近源极区域和浮置栅极，第一部分覆盖第一控制栅极部分，第二部分覆盖第一和第二区域之间的沟道的第三区域，以及覆盖第二控制栅极部分的第三部分。浮动栅极还包括从浮动栅极的第一部分延伸到第二部分大致垂直的第四部分，以及从浮动栅极的第二部分至第三部分大致垂直延伸的第五部分。电介质将控制和浮动栅极彼此和衬底分开。

10. 发明授权

US06380571B1 CMOS compatible pixel cell that utilizes a gated diode to reset the cell 有权
标题翻译： CMOS兼容像素单元，利用门控二极管复位单元
公开(公告)号：US06380571B1
公开(公告)日：2002-04-30
申请号：US09173276
申请日：1998-10-14
申请人： Alexander Kalnitsky , Albert Bergemont , Pavel Poplevine
发明人： Alexander Kalnitsky , Albert Bergemont , Pavel Poplevine
IPC分类号： H01L31113
CPC分类号： H01L27/14654 , H01L27/14609 , H01L27/1463
摘要： The potential on a pixel cell having a gated diode and a read out transistor is set to an initial level prior to an image integration period. During the image integration period, absorbed photons cause the potential on the pixel cell to change. After the image integration period, the pixel cell is then reset and read out by applying a number of pulses to the gated diode. Each of the pulses causes a fixed amount of charge to be injected into the cell. When the potential on the cell has again returned to the initial level, the number of absorbed photons is determined by counting the number of pulses that were required to return the potential to the initial level. The read out transistor is used to determine when the potential is at the initial level by biasing the transistor to output a current that corresponds to the potential on the pixel cell.
摘要翻译：具有门控二极管和读出晶体管的像素单元上的电位在图像积分周期之前被设置为初始电平。在图像积分期间，吸收的光子导致像素单元的电位发生变化。在图像积分周期之后，通过向门控二极管施加多个脉冲来复位和读出像素单元。每个脉冲导致固定量的电荷注入到电池中。当电池上的电位再次恢复到初始电平时，通过计算将电位恢复到初始电平所需的脉冲数来确定吸收光子的数量。读出晶体管用于通过偏置晶体管来输出对应于像素单元上的电位的电流来确定电位何时处于初始电平。

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