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1. 发明申请

US20190189464A1 METHODS AND APPARATUS FOR GETTERING IMPURITIES IN SEMICONDUCTORS 审中-公开
公开(公告)号：US20190189464A1
公开(公告)日：2019-06-20
申请号：US16327713
申请日：2016-09-30
申请人： Intel Corporation
发明人： Aaron D. Lilak , Harold W. Kennel , Patrick Morrow , Rishabh Mehandru , Stephen M. Cea
IPC分类号： H01L21/322 , H01L21/265 , H01L21/768 , H01L23/26
CPC分类号： H01L21/3226 , H01L21/26506 , H01L21/3221 , H01L21/38 , H01L21/70 , H01L21/768 , H01L23/26
摘要： Methods and apparatus for gettering impurities in semiconductors are disclosed. A disclosed example multilayered die includes a substrate material, a component layer below the substrate material, and an impurity attractant region disposed in the substrate material.

2. 发明授权

US10083933B2 Method for permanent bonding of wafers 有权
公开(公告)号：US10083933B2
公开(公告)日：2018-09-25
申请号：US14976484
申请日：2015-12-21
申请人： EV GROUP E. THALLNER GMBH
发明人： Thomas Plach , Kurt Hingerl , Markus Wimplinger , Christoph Flotgen
IPC分类号： H01L23/00 , H01L21/18 , H01L21/20 , H01L21/762 , H01L21/70
CPC分类号： H01L24/83 , H01L21/187 , H01L21/2007 , H01L21/70 , H01L21/76251 , H01L24/80 , H01L2224/80907 , H01L2224/83009 , H01L2224/83894 , H01L2224/83907 , H01L2924/01001 , H01L2924/01007 , H01L2924/01008 , H01L2924/01018 , H01L2924/20102 , H01L2924/20103 , H01L2924/20104 , H01L2924/20105 , H01L2924/20106
摘要： A method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate according to the following steps: forming a reservoir in a surface layer on the first contact surface, at least partially filling the reservoir with a first educt or a first group of educts, contacting the first contact surface with the second contact surface for formation of a prebond connection, and forming a permanent bond between the first and second contact surface, at least partially strengthened by the reaction of the first educt with a second educt contained in a reaction layer of the second substrate.

3. 发明授权

US09640421B2 Monolithic integration techniques for fabricating photodetectors with transistors on same substrate 有权
公开(公告)号：US09640421B2
公开(公告)日：2017-05-02
申请号：US14950902
申请日：2015-11-24
申请人： Artilux, Inc
发明人： Szu-Lin Cheng , Shu-Lu Chen
IPC分类号： H01L31/18 , H01L31/113 , H01L31/062 , H01L21/70 , H01L27/144 , H01L21/8234 , H01L31/0216 , H01L29/78 , H01L31/105 , H01L31/028 , H01L21/77 , H01L31/02 , H01L31/0232
CPC分类号： H01L31/02019 , H01L21/70 , H01L21/77 , H01L21/823475 , H01L23/5226 , H01L23/53271 , H01L27/1443 , H01L27/14632 , H01L27/14636 , H01L27/14687 , H01L27/14689 , H01L29/0657 , H01L29/78 , H01L31/02005 , H01L31/02161 , H01L31/022408 , H01L31/02327 , H01L31/028 , H01L31/0352 , H01L31/105 , H01L31/18 , H01L31/1808 , H01L31/1868 , H01L31/1876
摘要： Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.

4. 发明授权

US09583584B2 Methods for producing integrated circuits using long and short regions and integrated circuits produced from such methods 有权
标题翻译：使用长和短区域制造集成电路的方法和由这些方法制造的集成电路
公开(公告)号：US09583584B2
公开(公告)日：2017-02-28
申请号：US14795984
申请日：2015-07-10
申请人： GLOBALFOUNDRIES, INC. , International Business Machines Corporation
发明人： Chanro Park , Injo Ok
IPC分类号： H01L21/70 , H01L29/49 , H01L29/66 , H01L21/82
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/70 , H01L21/82 , H01L21/82345 , H01L21/823456 , H01L29/66545
摘要： Integrated circuits and methods for producing the same are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a work function layer overlying a substrate and a plurality of dielectric columns. The dielectric columns and the substrate define a short region having a short region width and a long region having a long region width greater than the short region width. The work function layer is recessed in the long region to a long region work function height that is between a dielectric column top surface and a substrate top surface. The work function layer is also recessed in the short region to a short region work function height that is between the dielectric column top surface and the substrate top surface. Recessing the work function layer in the long and short regions is conducted in the absence of lithography techniques.
摘要翻译：提供了集成电路及其制造方法。在示例性实施例中，用于制造集成电路的方法包括形成覆盖在基板和多个电介质柱上的功函数层。电介质柱和衬底限定具有短区域宽度的短区域和具有大于短区域宽度的长区域宽度的长区域。工作功能层在长区域中凹陷到介电柱顶表面和基板顶表面之间的长区域功函数高度。工作功能层也在短区域中凹陷到介电柱顶表面和衬底顶表面之间的短区域功函数高度。在没有光刻技术的情况下，在长和短区域内嵌入功函数层。

5. 发明申请

US20160174367A1 CONTROLLED TRANSFORMATION OF NON-TRANSIENT ELECTRONICS 有权
标题翻译：非瞬态电子控制变换
公开(公告)号：US20160174367A1
公开(公告)日：2016-06-16
申请号：US14893049
申请日：2014-05-21
申请人： TRANSIENT ELECTRONICS, INC.
发明人： Christopher Poirier , Anthony Campbell , John A. Rogers , Winston E. Henderson
IPC分类号： H05K1/02 , H05K13/00
CPC分类号： H05K1/0275 , B02C23/00 , H01L21/70 , H01L23/04 , H01L23/57 , H01L2924/0002 , H05B3/06 , H05K1/02 , H05K13/00 , H05K2203/178 , Y10T29/49002 , H01L2924/00
摘要： Systems and methods of the invention generally relate to altering the functionality of a non-transient electronic device. A container holding an agent is located proximal to a non-tansient electronic device capable of performing at least one function. The agent is capable of rendering the device incapable of performing the at least one function. The container is configured to controllably release the agent to the electronic device in a variety of passive and active eventualities.
摘要翻译：本发明的系统和方法通常涉及改变非瞬态电子设备的功能。容纳药剂的容器位于能够执行至少一种功能的非调味电子设备的近侧。代理能够使设备不能执行至少一个功能。容器被配置为以各种被动和主动的可能性可控地将代理释放到电子设备。

6. 发明申请

US20160148959A1 Monolithic Integration Techniques for Fabricating Photodetectors with Transistors on Same Substrate 有权
标题翻译：用于在相同基板上制造具有晶体管的光电探测器的单片集成技术
公开(公告)号：US20160148959A1
公开(公告)日：2016-05-26
申请号：US14950902
申请日：2015-11-24
申请人： Artilux, Inc
发明人： Szu-Lin Cheng , Shu-Lu Chen
IPC分类号： H01L27/144 , H01L21/8234 , H01L23/535 , H01L31/028 , H01L31/0216 , H01L29/78 , H01L31/105 , H01L31/18 , H01L21/02
CPC分类号： H01L31/02019 , H01L21/70 , H01L21/77 , H01L21/823475 , H01L23/5226 , H01L23/53271 , H01L27/1443 , H01L27/14632 , H01L27/14636 , H01L27/14687 , H01L27/14689 , H01L29/0657 , H01L29/78 , H01L31/02005 , H01L31/02161 , H01L31/022408 , H01L31/02327 , H01L31/028 , H01L31/0352 , H01L31/105 , H01L31/18 , H01L31/1808 , H01L31/1868 , H01L31/1876
摘要： Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.
摘要翻译：这里介绍的各种技术的示例包括但不限于在浅沟槽隔离形成期间的台面高度调节方法，通过第一种方法的晶体管和多吸收层方法。如下面进一步描述的，本文介绍的技术包括可以单独地和/或共同地解决或减轻在相同衬底上制造PD和晶体管所涉及的一个或多个传统限制的各种方面，例如上述可靠性，性能和过程温度问题。

7. 发明申请

US20150054065A1 Vertical Tunneling Field-Effect Transistor Cell and Fabricating the Same 有权
标题翻译：垂直隧道场效应晶体管电池及其制造
公开(公告)号：US20150054065A1
公开(公告)日：2015-02-26
申请号：US14532571
申请日：2014-11-04
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Harry-Hak-Lay Chuang , Cheng-Cheng Kuo , Ming Zhu
IPC分类号： H01L27/088 , H01L29/66 , H01L29/417 , H01L29/78 , H01L29/06
CPC分类号： H01L27/088 , H01L21/70 , H01L21/823487 , H01L29/0657 , H01L29/41783 , H01L29/66356 , H01L29/66666 , H01L29/66977 , H01L29/7391 , H01L29/7827
摘要： A method of making a tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. Isolation features are formed on the substrate. A drain region is disposed over the substrate adjacent to the frustoconical protrusion structure and extends to a bottom portion of the frustoconical protrusion structure as a raised drain region. A source region is formed as a top portion of the frustoconical protrusion structure. A series connection and a parallel connection are made among TFET devices units.
摘要翻译：公开了一种制造隧道场效应晶体管（TFET）器件的方法。截头圆锥形突起结构设置在衬底上并突出到衬底平面之外。在基板上形成隔离特征。漏极区域设置在与截头圆锥形突起结构相邻的衬底上，并延伸到截头圆锥形突起结构的底部作为升高的漏极区域。源区域形成为截头圆锥形突起结构的顶部。在TFET器件单元之间进行串联和并联连接。

8. 发明授权

US08963253B2 Bi-directional bipolar junction transistor for high voltage electrostatic discharge protection 有权
标题翻译：用于高压静电放电保护的双向双极结型晶体管
公开(公告)号：US08963253B2
公开(公告)日：2015-02-24
申请号：US13658295
申请日：2012-10-23
申请人： Macronix International Co., Ltd.
发明人： Hsin-Liang Chen , Shuo-Lun Tu
IPC分类号： H01L23/62 , H01L21/70
CPC分类号： H01L23/62 , H01L21/70 , H01L27/0262 , H01L29/7436 , H01L2924/0002 , H02H9/046 , H01L2924/00
摘要： A bi-directional electrostatic discharge (ESD) protection device may include a substrate, an N+ doped buried layer, an N-type well region and two P-type well regions. The N+ doped buried layer may be disposed proximate to the substrate. The N-type well region may encompass the two P-type well regions such that a portion of the N-type well region is interposed between the two P-type well regions. The P-type well regions may be disposed proximate to the N+ doped buried layer and comprise one or more N+ doped plates, one or more P+ doped plates, one or more field oxide (FOX) portions, and one or more field plates. A multi-emitter structure is also provided.
摘要翻译：双向静电放电（ESD）保护装置可以包括衬底，N +掺杂掩埋层，N型阱区和两个P型阱区。 N +掺杂掩埋层可以靠近衬底设置。 N型阱区可以包围两个P型阱区，使得N型阱区的一部分插入在两个P型阱区之间。 P型阱区可以靠近N +掺杂掩埋层设置并且包括一个或多个N +掺杂板，一个或多个P +掺杂板，一个或多个场氧化物（FOX）部分和一个或多个场板。还提供了多发射器结构。

9. 发明申请

US20140306357A1 DICING DIE-BONDING FILM AND METHOD OF FORMING A CUT ON THE DICING DIE-BONDING FILM 有权
标题翻译：定影胶带和切割成型胶带的切割方法
公开(公告)号：US20140306357A1
公开(公告)日：2014-10-16
申请号：US14315495
申请日：2014-06-26
申请人： Baek Soung PARK , Jae Won CHOI , Sung Min KIM , In Hwan KIM , Jun Woo LEE , Su MI IM
发明人： Baek Soung PARK , Jae Won CHOI , Sung Min KIM , In Hwan KIM , Jun Woo LEE , Su MI IM
IPC分类号： H01L23/544 , H01L21/70
CPC分类号： H01L23/544 , C09J7/20 , C09J2201/28 , C09J2201/36 , C09J2203/326 , H01L21/6836 , H01L21/70 , H01L24/27 , H01L2221/68327 , H01L2224/83191
摘要： A dicing die-bonding film and a method of forming a groove in a dicing die-bonding film, the film including a base film; a pressure-sensitive adhesive layer stacked on the base film; and a bonding layer stacked on the pressure-sensitive adhesive layer, wherein the pressure-sensitive adhesive layer includes a first region overlapping with the bonding layer, and a second region not overlapping with the bonding layer, the second region including a third region adjacent to the first region, and a fourth region adjacent to the third region and having a groove formed therein.
摘要翻译：一种切割芯片接合薄膜和一种在切割芯片接合薄膜中形成凹槽的方法，该薄膜包括一个基膜; 叠层在基膜上的压敏粘合剂层; 以及层叠在所述粘合剂层上的接合层，其中，所述压敏粘合剂层包括与所述接合层重叠的第一区域和与所述接合层不重叠的第二区域，所述第二区域包括与所述接合层相邻的第三区域所述第一区域和与所述第三区域相邻并且在其中形成有凹槽的第四区域。

10. 发明授权

US08698227B2 Mesa-type bidirectional Shockley diode 有权
标题翻译： Mesa型双向Shockley二极管
公开(公告)号：US08698227B2
公开(公告)日：2014-04-15
申请号：US13332395
申请日：2011-12-21
申请人： Yannick Hague , Samuel Menard
发明人： Yannick Hague , Samuel Menard
IPC分类号： H01L29/788
CPC分类号： H01L29/0638 , H01L21/70 , H01L29/0615 , H01L29/0626 , H01L29/0661 , H01L29/0834 , H01L29/747 , H01L29/87
摘要： A mesa-type bidirectional Shockley diode delimited on its two surfaces by a peripheral groove filled with a glassivation including a substrate of a first conductivity type; a layer of the second conductivity type on each side of the substrate; a region of the first conductivity type in each of the layers of the second conductivity type; a buried region of the first conductivity type under each of the regions of the first conductivity type, at the interface between the substrate and the corresponding layer of the second conductivity type, each buried region being complementary in projection with the other; and a peripheral ring under the external periphery of each of the glassivations, of same doping profile as the buried regions.
摘要翻译：台面型双向Shockley二极管在其两个表面上由填充有玻璃化的外围槽限定，包括第一导电类型的衬底; 在基板的每一侧上具有第二导电类型的层; 在第二导电类型的每个层中的第一导电类型的区域; 在第一导电类型的每个区域下的第一导电类型的掩埋区域，在基板和第二导电类型的相应层之间的界面处，每个掩埋区域与另一个的突出互补; 以及在每个玻璃化的外围的外周环上，具有与掩埋区相同的掺杂分布。

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