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1. 发明授权

US08772102B2 Methods of forming self-aligned contacts for a semiconductor device formed using replacement gate techniques 有权
标题翻译：使用替代栅极技术形成的半导体器件的自对准触点的形成方法
公开(公告)号：US08772102B2
公开(公告)日：2014-07-08
申请号：US13455616
申请日：2012-04-25
申请人： Min-Hwa Chi
发明人： Min-Hwa Chi
IPC分类号： H01L21/265
CPC分类号： H01L21/823431 , H01L21/265 , H01L21/823437 , H01L21/823468 , H01L21/823475 , H01L21/823821 , H01L21/823828 , H01L21/823864 , H01L21/823871 , H01L29/665 , H01L29/66545
摘要： One illustrative method disclosed herein involves forming an etch stop layer above a plurality of sacrificial gate structures, performing an angled ion implant process to implant an etch-inhibiting species into less than an entirety of the etch stop layer, and forming a layer of insulating material above the etch stop layer. The method further includes removing the sacrificial gate structures, forming replacement gate structures, forming a hard mask layer above the replacement gate structures and layer of insulating material, forming a patterned hard mask layer, performing another etching process through the patterned hard mask layer to define an opening in the layer of insulating material to expose a portion of the etch stop layer, performing another etching process on the exposed portion to define a contact opening therethrough that exposes a doped region and forming a conductive contact in the opening that is conductively coupled to the doped region.
摘要翻译：本文公开的一种说明性方法涉及在多个牺牲栅极结构之上形成蚀刻停止层，执行成角度的离子注入工艺以将蚀刻抑制物质注入少于整个蚀刻停止层，以及形成绝缘材料层在蚀刻停止层之上。该方法还包括去除牺牲栅极结构，形成替代栅极结构，在替代栅极结构和绝缘材料层之上形成硬掩模层，形成图案化硬掩模层，通过图案化硬掩模层进行另一蚀刻工艺以界定绝缘材料层中的开口以暴露蚀刻停止层的一部分，对暴露部分执行另一蚀刻工艺以限定通过其的接触开口，其暴露掺杂区域并在导电耦合到开口中的导电接触掺杂区域。

2. 发明申请

US20130288471A1 METHODS OF FORMING SELF-ALIGNED CONTACTS FOR A SEMICONDUCTOR DEVICE 有权
标题翻译：形成半导体器件的自对准接触的方法
公开(公告)号：US20130288471A1
公开(公告)日：2013-10-31
申请号：US13455579
申请日：2012-04-25
申请人： Min-Hwa Chi
发明人： Min-Hwa Chi
IPC分类号： H01L21/265
CPC分类号： H01L21/3115 , H01L21/823437 , H01L21/823468 , H01L21/823475 , H01L21/823828 , H01L21/823864 , H01L21/823871 , H01L29/665 , H01L29/66545
摘要： One illustrative method disclosed herein involves forming gate structures for first and second spaced-apart transistors above a semiconducting substrate, forming an etch stop layer above the substrate and the gate structures, performing at least one angled ion implant process to implant at least one etch-inhibiting species into less than an entirety of the etch stop layer, after performing at least one angled ion implant process, forming a layer of insulating material above the etch stop layer, performing at least one first etching process to define an opening in the layer of insulating material and thereby expose a portion of the etch stop layer, performing at least one etching process on the exposed portion of the etch stop layer to define a contact opening therethrough that exposes a doped region formed in the substrate, and forming a conductive contact in the opening that is conductively coupled to the doped region.
摘要翻译：本文公开的一种说明性方法包括在半导体衬底上形成用于第一和第二间隔开的晶体管的栅极结构，在衬底和栅极结构之上形成蚀刻停止层，执行至少一个成角度的离子注入工艺以植入至少一个蚀刻 - 在进行至少一个成角度的离子注入工艺之后，在蚀刻停止层上方形成绝缘材料层，进行至少一个第一蚀刻工艺以在所述蚀刻停止层中形成一个开口从而暴露一部分蚀刻停止层，在蚀刻停止层的暴露部分上执行至少一个蚀刻工艺以限定通过其中的接触开口，其暴露形成在衬底中的掺杂区域，并形成导电接触导电耦合到掺杂区的开口。

3. 发明申请

US20130288468A1 METHODS OF FORMING SELF-ALIGNED CONTACTS FOR A SEMICONDUCTOR DEVICE FORMED USING REPLACEMENT GATE TECHNIQUES 有权
标题翻译：使用替换门技术形成的半导体器件形成自对准接触的方法
公开(公告)号：US20130288468A1
公开(公告)日：2013-10-31
申请号：US13455616
申请日：2012-04-25
申请人： Min-Hwa Chi
发明人： Min-Hwa Chi
IPC分类号： H01L21/425
CPC分类号： H01L21/823431 , H01L21/265 , H01L21/823437 , H01L21/823468 , H01L21/823475 , H01L21/823821 , H01L21/823828 , H01L21/823864 , H01L21/823871 , H01L29/665 , H01L29/66545
摘要： One illustrative method disclosed herein involves forming an etch stop layer above a plurality of sacrificial gate structures, performing an angled ion implant process to implant an etch-inhibiting species into less than an entirety of the etch stop layer, and forming a layer of insulating material above the etch stop layer. The method further includes removing the sacrificial gate structures, forming replacement gate structures, forming a hard mask layer above the replacement gate structures and layer of insulating material, forming a patterned hard mask layer, performing another etching process through the patterned hard mask layer to define an opening in the layer of insulating material to expose a portion of the etch stop layer, performing another etching process on the exposed portion to define a contact opening therethrough that exposes a doped region and forming a conductive contact in the opening that is conductively coupled to the doped region.
摘要翻译：本文公开的一种说明性方法涉及在多个牺牲栅极结构之上形成蚀刻停止层，执行成角度的离子注入工艺以将蚀刻抑制物质注入少于整个蚀刻停止层，以及形成绝缘材料层在蚀刻停止层之上。该方法还包括去除牺牲栅极结构，形成替代栅极结构，在替代栅极结构和绝缘材料层之上形成硬掩模层，形成图案化硬掩模层，通过图案化硬掩模层进行另一蚀刻工艺以界定绝缘材料层中的开口以暴露蚀刻停止层的一部分，对暴露部分执行另一蚀刻工艺以限定通过其的接触开口，其暴露掺杂区域并在导电耦合到开口中的导电接触掺杂区域。

4. 发明授权

US08421166B2 Semiconductor device and fabrication thereof 有权
标题翻译：半导体器件及其制造
公开(公告)号：US08421166B2
公开(公告)日：2013-04-16
申请号：US13175443
申请日：2011-07-01
申请人： Min-Hwa Chi , Wen-Chuan Chiang , Mu-Chi Chiang , Cheng-Ku Chen
发明人： Min-Hwa Chi , Wen-Chuan Chiang , Mu-Chi Chiang , Cheng-Ku Chen
IPC分类号： H01L21/02 , H01L27/118 , H01L21/76
CPC分类号： H01L29/665 , H01L29/4991 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833 , Y02P80/30
摘要： A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer. The opening is sealed by a sealing layer to form an air gap.
摘要翻译：公开了一种用于形成半导体器件的方法。提供了包括顺序地形成在其上的栅介电层和栅极电极层的基板。在栅极电介质层和栅极电极层的侧壁上形成偏移间隔物。在间隔物的侧壁上形成碳隔离物，然后除去碳隔离物。使用栅极电极层和偏移间隔物作为掩模，注入衬底以形成轻掺杂区域。该方法还可以包括提供具有顺序地形成在其上的栅极电介质层和栅极电极层的衬底。衬底层形成在栅电极层的侧壁和衬底上。在衬垫层的与栅电极层的侧壁相邻的部分上形成碳隔离物。主间隔件形成在碳隔离件的侧壁上。去除碳间隔物以在衬垫层和主间隔物之间形成开口。开口由密封层密封以形成气隙。

5. 发明申请

US20110090731A1 GREEN TRANSISTOR FOR NANO-SI FERRO-ELECTRIC RAM AND METHOD OF OPERATING THE SAME 有权
标题翻译：用于纳米电动RAM的绿色晶体管及其操作方法
公开(公告)号：US20110090731A1
公开(公告)日：2011-04-21
申请号：US12869941
申请日：2010-08-27
申请人： Min-hwa Chi , Deyuan Xiao
发明人： Min-hwa Chi , Deyuan Xiao
IPC分类号： G11C11/22 , H01L27/12
CPC分类号： H01L27/1203 , B82Y10/00 , G11C11/22 , G11C11/223 , H01L21/28291 , H01L27/1159 , H01L29/6684 , H01L29/78391
摘要： The present disclosure provides a green transistor for nano-Si Ferro-electric random access memory (FeRAM) and method of operating the same. The nano-Si FeRAM includes a plurality of memory cells arranged in an array with bit-lines and word-lines, and each memory cell includes a MOSFET including a gate, a source, a drain, a substrate, and a data storage element formed on the drain spacer of the gate and made of nano-Si in porous SiO2; a word-line connected to the gate; a first bit-line connected to the drain; a second bit-line connected to the source; and an substrate bias supply connected to the substrate, and the gate induced drain leakage current of the MOSFET serves as the read current of the memory cell.
摘要翻译：本公开提供了一种用于纳米Si铁电随机存取存储器（FeRAM）的绿色晶体管及其操作方法。纳米SiFeRAM包括以位线和字线布置成阵列的多个存储单元，并且每个存储单元包括MOSFET，其包括栅极，源极，漏极，衬底和形成的数据存储元件在栅极的漏极间隔，并由多孔SiO2中的纳米Si制成; 连接到门的字线; 连接到漏极的第一位线; 连接到源的第二位线; 以及连接到衬底的衬底偏置电源，并且MOSFET的栅极感应漏极漏电流用作存储器单元的读取电流。

6. 发明申请

US20110051496A1 Resistive Random Access Memory and the Method of Operating the Same 有权
标题翻译：电阻随机存取存储器及其操作方法
公开(公告)号：US20110051496A1
公开(公告)日：2011-03-03
申请号：US12854491
申请日：2010-08-11
申请人： Min-hwa CHI , Xiaohui HUANG , Lijun SONG , Jingang WU , Deyuan XIAO
发明人： Min-hwa CHI , Xiaohui HUANG , Lijun SONG , Jingang WU , Deyuan XIAO
IPC分类号： G11C11/21 , G11C7/12
CPC分类号： G11C13/0007 , G11C13/003 , G11C2013/0071 , G11C2013/0078 , G11C2013/0083 , G11C2213/78 , G11C2213/79
摘要： A resistive random access memory utilizing gate induced drain leakage current as the read operation current and the write operation current and a method of operation the same, wherein the resistive random access memory including a plurality of arrayed memory cells, a plurality of bit-lines and a plurality word-lines, each memory cell including: a switching resistor having a first terminal and a second terminal, the first terminal of the switching resistor being connected to one bit-line; and a MOSFET being connected to the second terminal and having a gate, a source, a drain and a substrate, the gate being connected to one word-line, the read operation current and the write operation current of the memory cell being gate induced drain leakage current of the MOSFET. The RRAM array presented in this invention has superior scalability for resistors as well as transistors, which leads to a memory array with higher density.
摘要翻译：一种利用栅极感应漏极漏电流作为读操作电流和写操作电流的电阻随机存取存储器及其操作方法，其中所述电阻随机存取存储器包括多个阵列存储单元，多个位线和多个字线，每个存储单元包括：具有第一端子和第二端子的开关电阻器，所述开关电阻器的第一端子连接到一个位线; 以及连接到第二端子并且具有栅极，源极，漏极和衬底的MOSFET，栅极连接到一个字线，存储器单元的读取操作电流和写入操作电流是栅极感应漏极 MOSFET的漏电流。在本发明中呈现的RRAM阵列对于电阻器和晶体管具有优异的可扩展性，这导致具有更高密度的存储器阵列。

7. 发明申请

US20090160024A1 VERTICAL RESISTORS AND BAND-GAP VOLTAGE REFERENCE CIRCUITS 有权
标题翻译：垂直电阻和带隙电压参考电路
公开(公告)号：US20090160024A1
公开(公告)日：2009-06-25
申请号：US12358347
申请日：2009-01-23
申请人： Min-Hwa Chi
发明人： Min-Hwa Chi
IPC分类号： H01L29/66
CPC分类号： H01L27/0802 , H01L29/7722 , H01L29/8083 , H01L29/8605
摘要： A vertical resistor. A substrate includes a trench filled by an isolation layer. A first doped-type region and a second doped-type region are formed on both sides of the trench. The first doped-type region receives a control bias, the second doped-type region receives a reference bias, and a resistance between the second doped-type region and the substrate is adjusted in response to a voltage difference between the control bias and the reference bias.
摘要翻译：一个垂直电阻。衬底包括由隔离层填充的沟槽。第一掺杂型区域和第二掺杂型区域形成在沟槽的两侧。第一掺杂型区域接收控制偏压，第二掺杂型区域接收参考偏置，并且响应于控制偏压和参考电压之间的电压差来调整第二掺杂型区域和衬底之间的电阻偏压。

8. 发明申请

US20080315295A1 Atomic Layer Deposition Method and Semiconductor Device Formed by the Same 有权
标题翻译：原子层沉积法和由其形成的半导体器件
公开(公告)号：US20080315295A1
公开(公告)日：2008-12-25
申请号：US12132459
申请日：2008-06-03
申请人： Hua Ji , Min-Hwa Chi , Fumitake Mieno
发明人： Hua Ji , Min-Hwa Chi , Fumitake Mieno
IPC分类号： H01L29/792 , H01L21/311
CPC分类号： C23C16/04 , C23C16/45527 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02181 , H01L21/0228 , H01L21/28282 , H01L21/3141 , H01L21/31616 , H01L21/3185
摘要： Disclosed are atomic layer deposition method and a semiconductor device including the atomic layer, including the steps: placing a semiconductor substrate in an atomic layer deposition chamber; feeding a first precursor gas to the semiconductor substrate within the chamber to form a first discrete monolayer on the semiconductor substrate; feeding an inert purge gas to the semiconductor substrate within the chamber to remove the first precursor gas which has not formed the first discrete monolayer on the semiconductor substrate; feeding a second precursor gas to the chamber to react with the first precursor gas which has formed the first discrete monolayer, forming a discrete atomic size islands; and feeding an inert purge gas to the semiconductor substrate within the chamber to remove the second precursor gas which has not reacted with the first precursor gas and byproducts produced by the reaction between the first and the second precursor gases.
摘要翻译：公开了原子层沉积方法和包括原子层的半导体器件，包括以下步骤：将半导体衬底放置在原子层沉积室中; 将第一前体气体供给到腔室内的半导体衬底，以在半导体衬底上形成第一离散单层; 向腔室内的半导体衬底供给惰性清洗气体以去除在半导体衬底上未形成第一离散单层的第一前体气体; 将第二前体气体供给到所述室中以与形成所述第一离散单层的所述第一前体气体反应，形成离散的原子尺寸岛; 以及将惰性吹扫气体供给到室内的半导体衬底以除去未与第一前体气体反应的第二前体气体和由第一和第二前体气体之间的反应产生的副产物。

9. 发明申请

US20080315292A1 Atomic Layer Deposition Method and Semiconductor Device Formed by the Same 有权
标题翻译：原子层沉积法和由其形成的半导体器件
公开(公告)号：US20080315292A1
公开(公告)日：2008-12-25
申请号：US12141040
申请日：2008-06-17
申请人： Hua Ji , Min-Hwa Chi , Fumitake Mieno , Seanfuxiong Zhang
发明人： Hua Ji , Min-Hwa Chi , Fumitake Mieno , Seanfuxiong Zhang
IPC分类号： H01L21/28 , H01L29/792
CPC分类号： C23C16/45529 , H01L21/28282 , H01L29/1608 , H01L29/42348 , H01L29/792
摘要： There is provided a method of manufacturing a semiconductor device, including the following steps: flowing a first precursor gas to the semiconductor substrate within a ALD chamber to form a first discrete monolayer on the semiconductor substrate; flowing an inert purge gas to the semiconductor substrate within the ALD chamber; flowing a second precursor gas to the ALD chamber to react with the first precursor gas which has formed the first monolayer, thereby forming a first discrete compound monolayer; and flowing an inert purge gas; forming a first dielectric layer to cover the discrete compound monolayer; forming a second third monolayer above first dielectric layer; and forming a second discrete compound monolayer; and forming a second dielectric layer to cover the second discrete compound monolayer above the first dielectric layer. There is also provided a semiconductor device formed by the ALD method.
摘要翻译：提供一种制造半导体器件的方法，包括以下步骤：在ALD室内使第一前体气体流到半导体衬底，以在半导体衬底上形成第一离散单层; 将惰性吹扫气体流入ALD室内的半导体衬底; 使第二前体气体流到ALD室以与形成第一单层的第一前体气体反应，从而形成第一离散化合物单层; 并流动惰性吹扫气体; 形成第一电介质层以覆盖离散化合物单层; 在第一介电层上形成第二第三单层; 并形成第二离散化合物单层; 以及形成第二电介质层以覆盖所述第一电介质层上方的所述第二离散化合物单层。还提供了通过ALD方法形成的半导体器件。

10. 发明申请

US20070269907A1 Novel conductor layout technique to reduce stress-induced void formations 有权
标题翻译：新型导体布置技术，以减少应力引起的空隙形成
公开(公告)号：US20070269907A1
公开(公告)日：2007-11-22
申请号：US11438127
申请日：2006-05-22
申请人： Min-Hwa Chi , Tai-Chun Huang , Chih-Hsiang Yao
发明人： Min-Hwa Chi , Tai-Chun Huang , Chih-Hsiang Yao
IPC分类号： H01L21/00
CPC分类号： H01L21/76898 , H01L21/768 , H01L23/528 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. A notch is designed in the layout on a selective portion of the mask for patterning conductor line. The existence of a shape of notch on the selective portion generates extra stress components within the conductor line than if without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device.
摘要翻译：通过退火工艺制备半导体器件，通过由绝缘体材料包围的导体线来互连器件的至少两个部件。退火过程导致在导线和绝缘体材料内形成残余应力。在掩模的选择性部分上的布局中设计凹口，用于图案化导体线。选择部分上的凹口形状的存在在不存在凹口的情况下，在导线内产生额外的应力分量。选择凹口的位置使得额外的应力分量基本上抵消残余应力，从而导致残余应力的净减小。残余应力的减小导致相应的机械应力迁移，从而提高了装置的可靠性。

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