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1. 发明申请

US20100178747A1 Minimum Cost Method for Forming High Density Passive Capacitors for Replacement of Discrete Board Capacitors Using a Minimum Cost 3D Wafer-to-Wafer Modular Integration Scheme 有权
标题翻译：使用最小成本的3D晶片到晶片模块化集成方案形成高密度无源电容器来替代离散电路板电容器的最小成本方法
公开(公告)号：US20100178747A1
公开(公告)日：2010-07-15
申请号：US12352679
申请日：2009-01-13
申请人： Joseph Paul Ellul , Khanh Tran , Albert Bergemont
发明人： Joseph Paul Ellul , Khanh Tran , Albert Bergemont
IPC分类号： H01L21/02
CPC分类号： H01L25/50 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/81 , H01L25/0657 , H01L27/0805 , H01L28/91 , H01L29/66181 , H01L29/945 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/81203 , H01L2224/81801 , H01L2224/81894 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2224/05552 , H01L2924/00
摘要： Passive, high density, 3d IC capacitor stacks and methods that provide the integration of capacitors and integrated circuits in a wafer to wafer bonding process that provides for the integration of capacitors formed on one wafer, alone or with active devices, with one or more integrated circuits on one or more additional wafers that may be stacked in accordance with the process. Wafer to wafer bonding is preferably by thermo-compression, with grinding and chemical mechanical polishing being used to simply aspects of the process of fabrication. Various features and alternate embodiments are disclosed.
摘要翻译：被动的，高密度的3d IC电容器堆叠和方法，其提供电容器和集成电路在晶片到晶片接合工艺中的集成，其提供了在一个晶片上单独或与有源器件形成的电容集成，其中一个或多个集成可以根据该过程堆叠的一个或多个另外的晶片上的电路。晶圆接合的晶片优选通过热压缩，通过研磨和化学机械抛光仅用于制造工艺的方面。公开了各种特征和替代实施例。

2. 发明授权

US09023422B1 High rate deposition method of magnetic nanocomposites 有权
标题翻译：磁性纳米复合材料的高速沉积方法
公开(公告)号：US09023422B1
公开(公告)日：2015-05-05
申请号：US13596983
申请日：2012-08-28
申请人： Uppili Sridhar , Joseph Paul Ellul
发明人： Uppili Sridhar , Joseph Paul Ellul
IPC分类号： G11B5/66 , H01L39/24 , H01L21/316
CPC分类号： H01L21/3165 , C23C14/22 , C23C14/30 , H01F41/20
摘要： A method of deposition of magnetic nanocomposites. The method comprises providing an electron beam evaporation system having at least two independent hearths with independently controllable electron beams, each to melt and evaporate materials in the respective hearth, each hearth having a respective shutter for selectively controlling the deposition of the respective material in the respective hearth, placing a ferromagnetic material in a first hearth, placing an oxide in a second hearth which, when evaporated and deposited, will form an insulator, maintaining an oxygen environment in the electron beam evaporation system while evaporating the materials in the first hearth and second hearth, and depositing the magnetic nanocomposite on at least one wafer in the electron beam evaporation system. Various aspects of the method are disclosed.
摘要翻译：磁性纳米复合材料的沉积方法。该方法包括提供电子束蒸发系统，其具有至少两个具有可独立控制的电子束的独立炉膛，每个独立炉膛各自熔化和蒸发各个炉膛中的材料，每个炉膛都具有相应的闸门，用于选择性地控制相应材料在各自炉膛中的沉积将铁磁材料放置在第一炉床中，将氧化物放置在第二炉床中，当蒸发并沉积时，其将形成绝缘体，在蒸发第一炉床中的材料的同时保持电子束蒸发系统中的氧气环境，并且第二炉并且在所述电子束蒸发系统中的至少一个晶片上沉积所述磁性纳米复合材料。公开了该方法的各个方面。

3. 发明授权

US07943473B2 Minimum cost method for forming high density passive capacitors for replacement of discrete board capacitors using a minimum cost 3D wafer-to-wafer modular integration scheme 有权
标题翻译：使用最小成本的3D晶圆到晶片模块化集成方案形成高密度无源电容器来替代分立板电容器的最低成本方法
公开(公告)号：US07943473B2
公开(公告)日：2011-05-17
申请号：US12352679
申请日：2009-01-13
申请人： Joseph Paul Ellul , Khanh Tran , Albert Bergemont
发明人： Joseph Paul Ellul , Khanh Tran , Albert Bergemont
IPC分类号： H01L21/20
CPC分类号： H01L25/50 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/81 , H01L25/0657 , H01L27/0805 , H01L28/91 , H01L29/66181 , H01L29/945 , H01L2224/0401 , H01L2224/0557 , H01L2224/13009 , H01L2224/81203 , H01L2224/81801 , H01L2224/81894 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2224/05552 , H01L2924/00
摘要： Passive, high density, 3d IC capacitor stacks and methods that provide the integration of capacitors and integrated circuits in a wafer to wafer bonding process that provides for the integration of capacitors formed on one wafer, alone or with active devices, with one or more integrated circuits on one or more additional wafers that may be stacked in accordance with the process. Wafer to wafer bonding is preferably by thermo-compression, with grinding and chemical mechanical polishing being used to simply aspects of the process of fabrication. Various features and alternate embodiments are disclosed.
摘要翻译：被动的，高密度的3d IC电容器堆叠和方法，其提供电容器和集成电路在晶片到晶片接合工艺中的集成，其提供了在一个晶片上单独或与有源器件形成的电容集成，其中一个或多个集成可以根据该过程堆叠的一个或多个另外的晶片上的电路。晶圆接合的晶片优选通过热压缩，通过研磨和化学机械抛光仅用于制造工艺的方面。公开了各种特征和替代实施例。

4. 发明申请

US20080296143A1 Plasma Systems with Magnetic Filter Devices to Alter Film Deposition/Etching Characteristics 审中-公开
标题翻译：具有磁性过滤装置的等离子体系统以改变膜沉积/蚀刻特性
公开(公告)号：US20080296143A1
公开(公告)日：2008-12-04
申请号：US12191505
申请日：2008-08-14
申请人： Joseph Paul Ellul , Melvin C. Schmidt , Viktor Zekeriya , Rajiv L. Patel , Jack Kelly
发明人： Joseph Paul Ellul , Melvin C. Schmidt , Viktor Zekeriya , Rajiv L. Patel , Jack Kelly
IPC分类号： C23C14/34 , H05H1/46
CPC分类号： C23C14/35 , H01J37/32431 , H01J37/32623 , H01J37/3266 , H01J37/3408
摘要： Plasma systems with magnetic filter devices to alter film deposition/etching characteristics by altering the effective magnetic field distribution. The magnetic filter devices are placed between the magnet or magnets and a target, typically a semiconductor wafer, and selected and configured to alter the magnetic field to obtain the desired processing results. For deposition, the magnetic filter may be chosen to provide more uniform deposition, to provide increased deposition rates at or adjacent the edges of a wafer to compensate for increased etching rates at the edges of a wafer in a subsequent etching or polishing process. For annealing and doping, the magnetic field may be altered to provide more uniform equivalent annealing or doping across the wafer. Various applications are disclosed.
摘要翻译：具有磁性过滤装置的等离子体系统，通过改变有效磁场分布来改变成膜/蚀刻特性。磁性过滤器装置被放置在磁体或磁体与目标（通常为半导体晶片）之间，并被选择和配置成改变磁场以获得所需的处理结果。为了沉积，可以选择磁性过滤器以提供更均匀的沉积，以在晶片的边缘处或附近提供增加的沉积速率，以补偿随后的蚀刻或抛光工艺中在晶片边缘处的增加的蚀刻速率。对于退火和掺杂，可以改变磁场以提供跨晶片更均匀的等效退火或掺杂。公开了各种应用。

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