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1. 发明授权

US06573134B2 Dual metal gate CMOS devices and method for making the same 失效
公开(公告)号：US06573134B2
公开(公告)日：2003-06-03
申请号：US09817834
申请日：2001-03-27
申请人： Yanjun Ma , Yoshi Ono , David R. Evans , Sheng Teng Hsu
发明人： Yanjun Ma , Yoshi Ono , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L218238
CPC分类号： H01L21/823842 , H01L27/092
摘要： A method of fabricating a dual metal gate CMOS includes forming a gate oxide in a gate region and depositing a place-holder gate in each of a n-well and p-well; removing the place-holder gate and gate oxide; depositing a high-k dielectric in the gate region; depositing a first metal in the gate region of the p-well; depositing a second metal in the gate region of each of the n-well and p-well; and insulating and metallizing the structure. A dual metal gate CMOS of the invention includes PMOS transistor and a NMOS transistor. In the NMOS, a gate includes a high-k cup, a first metal cup formed in the high-k cup, and a second metal gate formed in the first metal cup. In the PMOS, a gate includes a high-k cup and a second metal gate formed in the high-k cup.

2. 发明授权

US07364989B2 Strain control of epitaxial oxide films using virtual substrates 有权
标题翻译：使用虚拟衬底的外延氧化膜的应变控制
公开(公告)号：US07364989B2
公开(公告)日：2008-04-29
申请号：US11174350
申请日：2005-07-01
申请人： Douglas J. Tweet , Yoshi Ono , David R. Evans , Sheng Teng Hsu
发明人： Douglas J. Tweet , Yoshi Ono , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L21/20
CPC分类号： H01L21/02192 , H01L21/02197 , H01L21/0228 , H01L21/3147
摘要： A method of controlling strain in a single-crystal, epitaxial oxide film, includes preparing a silicon substrate; forming a silicon alloy layer taken from the group of silicon alloy layer consisting of Si1-xGex and Si1-yCy on the silicon substrate; adjusting the lattice constant of the silicon alloy layer by selecting the alloy material content to adjust and to select a type of strain for the silicon alloy layer; depositing a single-crystal, epitaxial oxide film, by atomic layer deposition, taken from the group of oxide films consisting of perovskite manganite materials, single crystal rare-earth oxides and perovskite oxides, not containing manganese; and rare earth binary and ternary oxides, on the silicon alloy layer; and completing a desired device.
摘要翻译：一种控制单晶外延氧化膜中的应变的方法包括制备硅衬底; 从由Si 1-x Ge x Si和Si 1-y C C组成的硅合金层组形成硅合金层 > y ; 通过选择合金材料含量来调整硅合金层的晶格常数，并选择一种用于硅合金层的应变; 从由不含锰的钙钛矿亚锰酸盐材料，单晶稀土氧化物和钙钛矿氧化物组成的氧化膜组中，通过原子层沉积法沉积单晶外延氧化膜; 和稀土二元和三元氧化物，在硅合金层上; 并完成所需的设备。

3. 发明授权

US08264081B2 Multilayered barrier metal thin-films 有权
标题翻译：多层阻隔金属薄膜
公开(公告)号：US08264081B2
公开(公告)日：2012-09-11
申请号：US11311546
申请日：2005-12-19
申请人： Wei Pan , Yoshi Ono , David R. Evans , Sheng Teng Hsu
发明人： Wei Pan , Yoshi Ono , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L21/28562 , H01L21/76841 , H01L2221/1078
摘要： A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film comprises a Tantalum Nitride layer on a substrate, with a Titanium Nitride layer deposited thereon. The thickness of the entire multi-layer film may be approximately fifty Angstroms. The film has superior film characteristics, such as anti-diffusion capability, low resistivity, high density, and step coverage, when compared to films deposited by conventional chemical vapor deposition (CVD). The multi-layered barrier metal thin film of the present invention has improved adhesion characteristics and is particularly suited for metallization of a Copper film thereon.
摘要翻译：通过原子层化学气相沉积（ALCVD）将多层阻挡金属薄膜沉积在衬底上。多层膜可以包括单个化学物质的几个不同层，或者各个不同的或交替的化学物质的几个层。在优选实施例中，多层阻挡薄膜包括在衬底上的氮化钽层，其上沉积有氮化钛层。整个多层膜的厚度可以是大约50埃。当与通过常规化学气相沉积（CVD）沉积的膜相比时，该膜具有优异的膜特性，例如抗扩散能力，低电阻率，高密度和台阶覆盖。本发明的多层阻挡金属薄膜具有改善的粘合特性，特别适用于其上的铜膜的金属化。

4. 发明授权

US07015138B2 Multi-layered barrier metal thin films for Cu interconnect by ALCVD 有权
公开(公告)号：US07015138B2
公开(公告)日：2006-03-21
申请号：US09819296
申请日：2001-03-27
申请人： Wei Pan , Yoshi Ono , David R. Evans , Sheng Teng Hsu
发明人： Wei Pan , Yoshi Ono , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L21/44
CPC分类号： H01L21/28562 , H01L21/76841 , H01L2221/1078
摘要： A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film comprises a Tantalum Nitride layer on a substrate, with a Titanium Nitride layer deposited thereon. The thickness of the entire multi-layer film may be approximately fifty Angstroms. The film has superior film characteristics, such as anti-diffusion capability, low resistivity, high density, and step coverage, when compared to films deposited by conventional chemical vapor deposition (CVD). The multi-layered barrier metal thin film of the present invention has improved adhesion characteristics and is particularly suited for metallization of a Copper film thereon.

5. 发明授权

US06184157B2 Stress-loaded film and method for same 失效
标题翻译：应力负荷膜及其方法
公开(公告)号：US06184157B2
公开(公告)日：2001-02-06
申请号：US09088456
申请日：1998-06-01
申请人： Sheng Teng Hsu , Hongning Yang , David R. Evans , Tue Nguyen , Yanjun Ma
发明人： Sheng Teng Hsu , Hongning Yang , David R. Evans , Tue Nguyen , Yanjun Ma
IPC分类号： B05D306
CPC分类号： C23C14/50 , C23C14/06 , C23C14/22 , C23C16/30 , C23C16/44 , C23C16/4582
摘要： A method has been provided to counteract the inherent tension in a deposited film. A wafer substrate is fixed to a wafer chuck having a curved surface. When the chuck surface is convex, a tensile stress is implanted in a deposited film. Upon release from the chuck, the deposited film develops a compressive stress. When the chuck surface is concave, a compressive stress is implanted in the deposited film. Upon release from the chuck, the deposited film develops a tensile stress. Loading a film with a compressive stress is helpful in making films having an inherently tensile stress become thermal stable. Stress loading is also used to improve adhesion between films, and to prevent warping of a film during annealing. A product-by-process using the above-described method is also provided.
摘要翻译：已经提供了一种抵消沉积膜中的固有张力的方法。将晶片基板固定到具有弯曲表面的晶片卡盘。当卡盘表面凸出时，在沉积膜中注入拉伸应力。当从卡盘释放时，沉积的膜产生压缩应力。当卡盘表面凹陷时，在沉积膜中注入压应力。当从卡盘释放时，沉积的膜产生拉伸应力。加载具有压应力的薄膜有助于使具有固有拉伸应力的薄膜变得热稳定。应力负荷也用于提高膜之间的粘附性，并且防止退火期间膜的翘曲。还提供了使用上述方法的逐个方法。

6. 发明授权

US06200866B1 Use of silicon germanium and other alloys as the replacement gate for the fabrication of MOSFET 有权
标题翻译：使用硅锗等合金作为制造MOSFET的替代栅极
公开(公告)号：US06200866B1
公开(公告)日：2001-03-13
申请号：US09410346
申请日：1999-09-30
申请人： Yanjun Ma , Douglas J. Tweet , David R. Evans , Yoshi Ono
发明人： Yanjun Ma , Douglas J. Tweet , David R. Evans , Yoshi Ono
IPC分类号： H01L21338
CPC分类号： H01L21/31053 , H01L21/2807 , H01L21/28194 , H01L21/28202 , H01L21/76801 , H01L21/76804 , H01L21/76834 , H01L29/41733 , H01L29/41775 , H01L29/41783 , H01L29/4908 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66545 , H01L29/66575 , H01L29/66772 , H01L29/78684
摘要： A method of fabricating a MOSFET is provided, including: depositing an oxide layer on a silicon substrate for device isolation; forming a silicon based alloy island above a gate region in the substrate, wherein the silicon based alloy comprises a silicon germanium alloy or a silicon tin alloy or another alloy of Group IV-B elements; building a sidewall about the silicon based alloy island; forming a source region and a drain region in the substrate; removing the silicon based alloy island, thereby leaving a void over the gate region; filing the void and the areas over the source region and the drain region; and planarizing the upper surface of the structure by chemical mechanical polishing. Alternative embodiments providing conventional and raised source/drain structures are disclosed.
摘要翻译：提供一种制造MOSFET的方法，包括：在硅衬底上沉积氧化层用于器件隔离; 在所述基板的栅极区域的上方形成硅基合金岛，其中所述硅基合金包含硅锗合金或硅锡合金或第IV-B族元素的另一种合金; 围绕硅基合金岛构建侧壁; 在衬底中形成源区和漏区; 去除硅基合金岛，从而在栅极区域上留下空隙; 填充空隙和源区域和漏区域上的区域; 并通过化学机械抛光对结构的上表面进行平面化。公开了提供常规和凸起的源极/漏极结构的替代实施例。

7. 发明授权

US07968419B2 Back-to-back metal/semiconductor/metal (MSM) Schottky diode 有权
标题翻译：背对背金属/半导体/金属（MSM）肖特基二极管
公开(公告)号：US07968419B2
公开(公告)日：2011-06-28
申请号：US12234663
申请日：2008-09-21
申请人： Tingkai Li , Sheng Teng Hsu , David R. Evans
发明人： Tingkai Li , Sheng Teng Hsu , David R. Evans
IPC分类号： H01L21/20
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.
摘要翻译：提供了用于从硅（Si）半导体形成金属/半导体/金属（MSM）背对背肖特基二极管的方法。该方法在底电极和顶电极之间沉积Si半导体层，并形成具有阈值电压，击穿电压和开/关电流比的MSM二极管。响应于控制Si半导体层厚度，该方法能够修改MSM二极管的阈值电压，击穿电压和导通/截止电流比。通常，响应于Si厚度的增加，阈值和击穿电压都增加。关于开/关电流比，存在最佳厚度。该方法能够使用化学气相沉积（CVD）或DC溅射形成非晶Si（a-Si）和多晶硅（polySi）半导体层。 Si半导体可以掺杂有V族施主材料，其降低阈值电压并增加击穿电压。

8. 发明授权

US07029982B1 Method of affecting RRAM characteristics by doping PCMO thin films 有权
标题翻译：通过掺杂PCMO薄膜影响RRAM特性的方法
公开(公告)号：US07029982B1
公开(公告)日：2006-04-18
申请号：US10971387
申请日：2004-10-21
申请人： Wei-Wei Zhuang , David R. Evans , Fengyan Zhang , Sheng Teng Hsu
发明人： Wei-Wei Zhuang , David R. Evans , Fengyan Zhang , Sheng Teng Hsu
IPC分类号： H01L21/20
CPC分类号： H01L45/1608 , C23C18/1216 , C23C18/1225 , C23C18/1283 , C23C18/1295 , H01L21/31691 , H01L28/20 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method of fabricating a doped-PCMO thin film layer includes preparing a PCMO precursor solution having a transition metal additive therein; and spin-coating the doped-PCMO spin-coating solution onto a wafer.
摘要翻译：制造掺杂PCMO薄膜层的方法包括制备其中具有过渡金属添加剂的PCMO前体溶液; 并将掺杂的PCMO旋涂溶液旋涂到晶片上。

9. 发明授权

US06951825B2 Method of etching a SiN/Ir/TaN or SiN/Ir/Ti stack using an aluminum hard mask 失效
标题翻译：使用铝硬掩模蚀刻SiN / Ir / TaN或SiN / Ir / Ti叠层的方法
公开(公告)号：US06951825B2
公开(公告)日：2005-10-04
申请号：US10391294
申请日：2003-03-17
申请人： Tingkai Li , Bruce D. Ulrich , David R. Evans , Sheng Teng Hsu
发明人： Tingkai Li , Bruce D. Ulrich , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L21/3065 , H01L21/02 , H01L21/311 , H01L21/3213 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L29/788 , H01L29/792 , H01L21/302
CPC分类号： H01L21/32136 , H01L21/31116 , H01L21/32139 , H01L28/65
摘要： A method of etching includes preparing a substrate; depositing a first etch stop layer; forming an iridium bottom electrode layer; depositing a SiN layer; depositing and patterning an aluminum hard mask; etching a non-patterned SiN layer with a SiN selective etchant, stopping at the level of the iridium bottom electrode layer; etching the first etch stop layer with a second selective etchant; depositing an oxide layer and CMP the oxide layer to the level of the remaining SiN layer; wet etching the SiN layer to form a trench; depositing a layer of ferroelectric material in the trench formed by removal of the SiN layer; depositing a layer of high-k oxide; and completing the device, including metallization.
摘要翻译：蚀刻方法包括准备基板; 沉积第一蚀刻停止层; 形成铱底电极层; 沉积SiN层; 沉积和图案化铝硬掩模; 用SiN选择性蚀刻剂蚀刻未图案化的SiN层，停止在铱底部电极层的水平面上; 用第二选择性蚀刻剂蚀刻第一蚀刻停止层; 将氧化物层沉积并将所述氧化物层CMP沉积到剩余SiN层的水平; 湿式蚀刻SiN层以形成沟槽; 在通过去除SiN层形成的沟槽中沉积一层铁电材料; 沉积一层高K氧化物; 并完成设备，包括金属化。

10. 发明授权

US06627510B1 Method of making self-aligned shallow trench isolation 有权
标题翻译：自对准浅沟槽隔离方法
公开(公告)号：US06627510B1
公开(公告)日：2003-09-30
申请号：US10112014
申请日：2002-03-29
申请人： David R. Evans , Sheng Teng Hsu , Bruce D. Ulrich , Douglas J. Tweet , Lisa H. Stecker
发明人： David R. Evans , Sheng Teng Hsu , Bruce D. Ulrich , Douglas J. Tweet , Lisa H. Stecker
IPC分类号： H01L21762
CPC分类号： H01L21/28194 , H01L21/76224 , H01L21/823481 , H01L29/517 , H01L29/518 , Y10S438/975
摘要： A modified STI process is provided comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. An alignment key may be formed by selectively etching the oxide layer. A third polysilicon layer may then be deposited and patterned using photoresist to form a gate structure. During patterning, exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer. A thin layer of the first polysilicon layer remains, to be carefully removed using a subsequent selective etch process.
摘要翻译：提供了一种改进的STI工艺，包括在衬底上形成第一多晶硅层。通过第一多晶硅层形成沟槽并进入衬底，并用氧化物层填充沟槽。在氧化物上沉积第二多晶硅层，使得沟槽内的第二多晶硅层的底部高于第一多晶硅层的底部，并且沟槽内的第二多晶硅层的顶部低于第一多晶硅的顶部层。然后可以使用CMP工艺将得到的结构平坦化。可以通过选择性地蚀刻氧化物层来形成对准键。然后可以使用光致抗蚀剂沉积和图案化第三多晶硅层以形成栅极结构。在图案化期间，蚀刻暴露的第二多晶硅层。在完成去除第二多晶硅层时检测到蚀刻停止。保留第一多晶硅层的薄层，使用随后的选择性蚀刻工艺小心地去除。

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