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1. 发明授权

US06627510B1 Method of making self-aligned shallow trench isolation 有权
标题翻译：自对准浅沟槽隔离方法
公开(公告)号：US06627510B1
公开(公告)日：2003-09-30
申请号：US10112014
申请日：2002-03-29
申请人： David R. Evans , Sheng Teng Hsu , Bruce D. Ulrich , Douglas J. Tweet , Lisa H. Stecker
发明人： David R. Evans , Sheng Teng Hsu , Bruce D. Ulrich , Douglas J. Tweet , Lisa H. Stecker
IPC分类号： H01L21762
CPC分类号： H01L21/28194 , H01L21/76224 , H01L21/823481 , H01L29/517 , H01L29/518 , Y10S438/975
摘要： A modified STI process is provided comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. An alignment key may be formed by selectively etching the oxide layer. A third polysilicon layer may then be deposited and patterned using photoresist to form a gate structure. During patterning, exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer. A thin layer of the first polysilicon layer remains, to be carefully removed using a subsequent selective etch process.
摘要翻译：提供了一种改进的STI工艺，包括在衬底上形成第一多晶硅层。通过第一多晶硅层形成沟槽并进入衬底，并用氧化物层填充沟槽。在氧化物上沉积第二多晶硅层，使得沟槽内的第二多晶硅层的底部高于第一多晶硅层的底部，并且沟槽内的第二多晶硅层的顶部低于第一多晶硅的顶部层。然后可以使用CMP工艺将得到的结构平坦化。可以通过选择性地蚀刻氧化物层来形成对准键。然后可以使用光致抗蚀剂沉积和图案化第三多晶硅层以形成栅极结构。在图案化期间，蚀刻暴露的第二多晶硅层。在完成去除第二多晶硅层时检测到蚀刻停止。保留第一多晶硅层的薄层，使用随后的选择性蚀刻工艺小心地去除。

2. 发明授权

US06716691B1 Self-aligned shallow trench isolation process having improved polysilicon gate thickness control 有权
标题翻译：具有改进的多晶硅栅极厚度控制的自对准浅沟槽隔离工艺
公开(公告)号：US06716691B1
公开(公告)日：2004-04-06
申请号：US10606105
申请日：2003-06-25
申请人： David R. Evans , Sheng Teng Hsu , Bruce D. Ulrich , Douglas J. Tweet , Lisa H. Stecker
发明人： David R. Evans , Sheng Teng Hsu , Bruce D. Ulrich , Douglas J. Tweet , Lisa H. Stecker
IPC分类号： H01L218238
CPC分类号： H01L21/76224 , H01L21/28123 , H01L21/823878
摘要： A method of fabricating a CMOS have self-aligned shallow trench isolation, includes preparing a silicon substrate; forming a gate stack; depositing a layer of first polysilicon; trenching the substrate by shallow trench isolation to form a trench; filling the trench with oxide; depositing a second layer of polysilicon wherein the top surface of the second polysilicon layer is above the top surface of the first polysilicon layer; depositing a sacrificial oxide layer having a thickness of at least 1.5× that of the first polysilicon layer; CMP the sacrificial oxide layer to the level of the upper surface of the second polysilicon layer; depositing a third layer of polysilicon; patterning and etching the gate stack; implanting ions to form a source region, a drain region and the polysilicon gate; and completing the CMOS structure.
摘要翻译：制造CMOS的方法具有自对准浅沟槽隔离，包括制备硅衬底; 形成栅极叠层; 沉积第一多晶硅层; 通过浅沟槽隔离对衬底进行沟槽以形成沟槽; 用氧化物填充沟槽; 沉积第二多晶硅层，其中第二多晶硅层的顶表面在第一多晶硅层的顶表面之上; 沉积厚度至少为第一多晶硅层的1.5倍的牺牲氧化物层; 将牺牲氧化物层CMP CMP化为第二多晶硅层的上表面的水平; 沉积第三层多晶硅; 图案化和蚀刻栅极堆叠; 注入离子以形成源极区，漏极区和多晶硅栅; 并完成CMOS结构。

3. 发明授权

US07169637B2 One mask Pt/PCMO/Pt stack etching process for RRAM applications 有权
标题翻译：用于RRAM应用的一个掩模Pt / PCMO / Pt堆叠蚀刻工艺
公开(公告)号：US07169637B2
公开(公告)日：2007-01-30
申请号：US10883228
申请日：2004-07-01
申请人： Fengyan Zhang , Lisa H. Stecker , Bruce D. Ulrich , Sheng Teng Hsu
发明人： Fengyan Zhang , Lisa H. Stecker , Bruce D. Ulrich , Sheng Teng Hsu
IPC分类号： H01L21/06 , H01L21/461
CPC分类号： H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1675
摘要： A one-mask etching method for use with a PCMO-containing RRAM to reduce stack side-wall residuals, includes preparing a substrate, taken from the group of substrates consisting of silicon, silicon dioxide and polysilicon; depositing a bottom electrode on the substrate; depositing a PCMO layer on the bottom electrode; depositing a top electrode on the PCMO layer; depositing a hard mask on the top electrode; depositing and patterning a photoresist layer on the hard mask; etching the hard mask; etching the top electrode using a first etching process having an etching atmosphere consisting of Ar, O2, and Cl2; etching the PCMO layer using an etching process taken from the group of etching processes consisting of the first etching process and a second etching process having an etching atmosphere consisting of Ar and O2. etching the bottom electrode using the first etching process; and completing the RRAM device.
摘要翻译：包含含PCMO的RRAM以减少堆叠侧壁残留物的单掩模蚀刻方法包括制备从由硅，二氧化硅和多晶硅组成的一组衬底取得的衬底; 在底物上沉积底部电极; 在底部电极上沉积PCMO层; 在PCMO层上沉积顶部电极; 在顶部电极上沉积硬掩模; 在硬掩模上沉积和图案化光致抗蚀剂层; 蚀刻硬掩模; 使用具有由Ar，O 2和Cl 2组成的蚀刻气氛的第一蚀刻工艺蚀刻顶部电极; 使用从由第一蚀刻工艺和由Ar和O 2组成的蚀刻气氛的第二蚀刻工艺组成的蚀刻工艺组中的蚀刻工艺来蚀刻PCMO层。使用第一蚀刻工艺蚀刻底部电极; 并完成RRAM设备。

4. 发明授权

US07727897B2 Method of etching a TE/PCMO stack using an etch stop layer 有权
标题翻译：使用蚀刻停止层蚀刻TE / PCMO堆叠的方法
公开(公告)号：US07727897B2
公开(公告)日：2010-06-01
申请号：US11215519
申请日：2005-08-30
申请人： Bruce D. Ulrich , Lisa H. Stecker , Fengyan Zhang , Sheng Teng Hsu
发明人： Bruce D. Ulrich , Lisa H. Stecker , Fengyan Zhang , Sheng Teng Hsu
IPC分类号： H01L21/302
CPC分类号： H01L28/55 , H01L21/31122
摘要： A method of etching a top electrode/ferroelectric stack using an etch stop layer includes forming a first layer of a first dielectric material on a substrate; forming a bottom electrode in the first layer of a first dielectric material; depositing an etch stop layer on the first layer of the first dielectric material and the bottom electrode, including forming a hole therein; depositing a layer of ferroelectric material and depositing top electrode material on the ferroelectric material to form a top electrode/ferroelectric stack; stack etching the top electrode and ferroelectric material; depositing a layer of a second dielectric material encapsulating the top electrode and ferroelectric material; etching the layer of the second dielectric material to form a sidewall about the top electrode and ferroelectric material; and depositing a second and third layers of the first dielectric material.
摘要翻译：使用蚀刻停止层蚀刻顶部电极/铁电体堆叠的方法包括在衬底上形成第一电介质材料的第一层; 在第一介电材料的第一层中形成底电极; 在所述第一电介质材料和所述底电极的所述第一层上沉积蚀刻停止层，包括在其中形成孔; 沉积一层铁电材料层并在铁电材料上沉积顶部电极材料以形成顶部电极/铁电堆叠; 堆叠蚀刻顶部电极和铁电材料; 沉积封装上电极和铁电材料的第二电介质材料层; 蚀刻第二介电材料的层以形成围绕顶电极和铁电材料的侧壁; 以及沉积所述第一介电材料的第二和第三层。

5. 发明授权

US07041511B2 Pt/PGO etching process for FeRAM applications 失效
标题翻译： FeRAM应用的Pt / PGO蚀刻工艺
公开(公告)号：US07041511B2
公开(公告)日：2006-05-09
申请号：US10923381
申请日：2004-08-20
申请人： Fengyan Zhang , Bruce D. Ulrich , Lisa H. Stecker , Sheng Teng Hsu
发明人： Fengyan Zhang , Bruce D. Ulrich , Lisa H. Stecker , Sheng Teng Hsu
IPC分类号： H01L21/00 , H01L21/20
CPC分类号： H01L21/32139 , H01L21/32136 , H01L27/1085 , H01L27/11502 , H01L27/11507 , H01L28/65
摘要： A method of etching a noble metal top electrode on a ferroelectric layer while preserving the ferroelectric properties of the ferroelectric layer and removing etching residue includes preparing a substrate; depositing a barrier layer on the substrate; depositing a bottom electrode layer on the barrier layer; depositing a ferroelectric layer on the bottom electrode layer; depositing a noble metal top electrode layer on the ferroelectric layer; depositing an adhesion layer on the top electrode layer; depositing a hard mask layer on the adhesion layer; patterning the hard mask; etching the noble metal top electrode layer in an initial etching step at a predetermined RF bias power, which produces etching residue; and over etching the noble metal top electrode layer and ferroelectric layer at an RF bias power lower than that of the predetermined RF bias power to remove etching residue from the initial etching step.
摘要翻译：同时保留铁电层的铁电性能和除去蚀刻残渣的方法是在铁电体层上蚀刻贵金属顶电极的方法包括：制备衬底; 在衬底上沉积阻挡层; 在阻挡层上沉积底部电极层; 在底部电极层上沉积铁电层; 在所述铁电层上沉积贵金属顶电极层; 在所述顶部电极层上沉积粘附层; 在粘合层上沉积硬掩模层; 图案化硬掩模; 在初始蚀刻步骤中以预定的RF偏置功率蚀刻贵金属顶电极层，产生蚀刻残留物; 并以比预定的RF偏压功率低的RF偏压功率对贵金属顶电极层和铁电层进行过蚀刻，以从初始蚀刻步骤去除蚀刻残留物。

6. 发明授权

US07364989B2 Strain control of epitaxial oxide films using virtual substrates 有权
标题翻译：使用虚拟衬底的外延氧化膜的应变控制
公开(公告)号：US07364989B2
公开(公告)日：2008-04-29
申请号：US11174350
申请日：2005-07-01
申请人： Douglas J. Tweet , Yoshi Ono , David R. Evans , Sheng Teng Hsu
发明人： Douglas J. Tweet , Yoshi Ono , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L21/20
CPC分类号： H01L21/02192 , H01L21/02197 , H01L21/0228 , H01L21/3147
摘要： A method of controlling strain in a single-crystal, epitaxial oxide film, includes preparing a silicon substrate; forming a silicon alloy layer taken from the group of silicon alloy layer consisting of Si1-xGex and Si1-yCy on the silicon substrate; adjusting the lattice constant of the silicon alloy layer by selecting the alloy material content to adjust and to select a type of strain for the silicon alloy layer; depositing a single-crystal, epitaxial oxide film, by atomic layer deposition, taken from the group of oxide films consisting of perovskite manganite materials, single crystal rare-earth oxides and perovskite oxides, not containing manganese; and rare earth binary and ternary oxides, on the silicon alloy layer; and completing a desired device.
摘要翻译：一种控制单晶外延氧化膜中的应变的方法包括制备硅衬底; 从由Si 1-x Ge x Si和Si 1-y C C组成的硅合金层组形成硅合金层 > y ; 通过选择合金材料含量来调整硅合金层的晶格常数，并选择一种用于硅合金层的应变; 从由不含锰的钙钛矿亚锰酸盐材料，单晶稀土氧化物和钙钛矿氧化物组成的氧化膜组中，通过原子层沉积法沉积单晶外延氧化膜; 和稀土二元和三元氧化物，在硅合金层上; 并完成所需的设备。

7. 发明授权

US06992025B2 Strained silicon on insulator from film transfer and relaxation by hydrogen implantation 有权
标题翻译：绝缘体上的应变硅通过氢注入从膜转移和弛豫
公开(公告)号：US06992025B2
公开(公告)日：2006-01-31
申请号：US10755615
申请日：2004-01-12
申请人： Jer-shen Maa , Jong-Jan Lee , Douglas J. Tweet , David R. Evans , Allen W. Burmaster , Sheng Teng Hsu
发明人： Jer-shen Maa , Jong-Jan Lee , Douglas J. Tweet , David R. Evans , Allen W. Burmaster , Sheng Teng Hsu
IPC分类号： H01L21/26 , H01L21/42 , H01L21/324
CPC分类号： H01L21/76254
摘要： Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses a SSOI substrate fabrication process comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is the two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.
摘要翻译：包含直接设置在绝缘体层上的应变硅层的SSOI（应变绝缘体硅）基板上制造的晶体管由于应变诱导的应变硅器件通道的带隙修改而增加了器件性能，并且由于绝缘体层。本发明公开了一种包含各种新颖方法的SSOI衬底制造工艺。一个是使用薄的松弛SiGe层作为应变诱导的种子层，以促进整合并降低加工成本。另一个是在硅衬底深部形成分裂的植入物微裂纹，以减少到达应变硅层的穿透位错的数量。最后是对应变硅/ SiGe多层膜转移的两步退火/变薄处理，没有起泡或剥落形成。

8. 发明授权

US07390725B2 Strained silicon on insulator from film transfer and relaxation by hydrogen implantation 有权
标题翻译：绝缘体上的应变硅通过氢注入从膜转移和弛豫
公开(公告)号：US07390725B2
公开(公告)日：2008-06-24
申请号：US11284326
申请日：2005-11-21
申请人： Jer-shen Maa , Jong-Jan Lee , Douglas J. Tweet , David R. Evans , Allen W. Burmaster , Sheng Teng Hsu
发明人： Jer-shen Maa , Jong-Jan Lee , Douglas J. Tweet , David R. Evans , Allen W. Burmaster , Sheng Teng Hsu
IPC分类号： H01L21/46 , H01L21/30
CPC分类号： H01L21/76254
摘要： Transistors fabricated on SSOI (Strained Silicon On Insulator) substrate, which comprises a strained silicon layer disposed directly on an insulator layer, have enhanced device performance due to the strain-induced band modification of the strained silicon device channel and the limited silicon volume because of the insulator layer. The present invention discloses SSOI substrate fabrication processes comprising various novel approaches. One is the use of a thin relaxed SiGe layer as the strain-induced seed layer to facilitate integration and reduce processing cost. Another is the formation of split implant microcracks deep in the silicon substrate to reduce the number of threading dislocations reaching the strained silicon layer. And lastly is a two step annealing/thinning process for the strained silicon/SiGe multilayer film transfer without blister or flaking formation.
摘要翻译：包含直接设置在绝缘体层上的应变硅层的SSOI（应变绝缘体硅）基板上制造的晶体管由于应变诱导的应变硅器件通道的带隙修改而增加了器件性能，并且由于绝缘体层。本发明公开了包含各种新颖方法的SSOI衬底制造工艺。一个是使用薄的松弛SiGe层作为应变诱导的种子层，以促进整合并降低加工成本。另一个是在硅衬底深部形成分裂的植入物微裂纹，以减少到达应变硅层的穿透位错的数量。最后是对应变硅/ SiGe多层膜转移进行两步退火/变薄处理，无需起泡或剥落形成。

9. 发明授权

US07361574B1 Single-crystal silicon-on-glass from film transfer 有权
标题翻译：单晶硅玻璃从膜转移
公开(公告)号：US07361574B1
公开(公告)日：2008-04-22
申请号：US11601173
申请日：2006-11-17
申请人： Jer-Shen Maa , David R. Evans , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jer-Shen Maa , David R. Evans , Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L21/30 , H01L21/461
CPC分类号： H01L21/76251 , H01L21/84 , Y10S438/926 , Y10S438/933
摘要： A method is provided for transferring a single-crystal silicon (Si) film to a glass substrate. The method deposits a germanium (Ge)-containing material overlying a Si wafer, forming a sacrificial Ge-containing film. A single-crystal Si film is formed overlying the sacrificial Ge-containing film. The Si film surface is bonded to a transparent substrate, forming a bonded substrate. The bonded substrate is immersed in a Ge etching solution to remove the sacrificial Ge-containing film, which separates the transparent substrate from the Si wafer. The result is a transparent substrate with an overlying single crystal Si film. Optionally, channels can be formed to distribute the Ge etching solution, and promote the removal of the Ge-containing film.
摘要翻译：提供了将单晶硅（Si）膜转印到玻璃基板上的方法。该方法沉积覆盖Si晶片的含锗（Ge）的材料，形成牺牲含Ge膜。形成覆盖牺牲的含Ge膜的单晶Si膜。将Si膜表面粘合到透明基板上，形成键合衬底。将键合衬底浸入Ge蚀刻溶液中以除去将透明衬底与Si晶片分离的牺牲Ge含量膜。结果是具有上覆单晶Si膜的透明衬底。可选地，可以形成通道以分布Ge蚀刻溶液，并促进除去含Ge膜。

10. 发明授权

US07241670B2 Method to form relaxed SiGe layer with high Ge content using co-implantation of silicon with boron or helium and hydrogen 失效
标题翻译：使用硅与硼或氦和氢的共同注入形成具有高Ge含量的弛豫SiGe层的方法
公开(公告)号：US07241670B2
公开(公告)日：2007-07-10
申请号：US10936400
申请日：2004-09-07
申请人： Douglas J. Tweet , David R. Evans , Sheng Teng Hsu , Jer-Shen Maa
发明人： Douglas J. Tweet , David R. Evans , Sheng Teng Hsu , Jer-Shen Maa
IPC分类号： H01L21/26 , H01L21/42
CPC分类号： H01L21/02694 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L29/1054 , Y10S438/933
摘要： A method of forming a relaxed SiGe layer having a high germanium content in a semiconductor device includes preparing a silicon substrate; depositing a strained SiGe layer; implanting ions into the strained SiGe layer, wherein the ions include silicon ions and ions selected from the group of ions consisting of boron and helium, and which further includes implanting H+ ions; annealing to relax the strained SiGe layer, thereby forming a first relaxed SiGe layer; and completing the semiconductor device.
摘要翻译：在半导体器件中形成具有高锗含量的弛豫SiGe层的方法包括制备硅衬底; 沉积应变SiGe层; 将离子注入到应变SiGe层中，其中离子包括选自由硼和氦构成的离子组的硅离子和离子，并且还包括注入H +离子; 退火以使应变SiGe层松弛，从而形成第一弛豫SiGe层; 并完成半导体器件。

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