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1. 发明申请

US20180350603A1 SEMICONDUCTOR DEVICE WITH SELF-ALIGNED CARBON NANOTUBE GATE 审中-公开
公开(公告)号：US20180350603A1
公开(公告)日：2018-12-06
申请号：US16042405
申请日：2018-07-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： QING CAO , SHU-JEN HAN , NING LI , JIANSHI TANG
IPC分类号： H01L21/28 , H01L29/49 , H01L29/78 , H01L29/08 , H01L21/265 , H01L29/51 , H01L29/66
CPC分类号： H01L21/2807 , B82Y10/00 , H01L21/26513 , H01L21/28088 , H01L21/32056 , H01L29/0673 , H01L29/0847 , H01L29/401 , H01L29/4966 , H01L29/517 , H01L29/6653 , H01L29/6656 , H01L29/66568 , H01L29/775 , H01L29/78
摘要： A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.

2. 发明授权

US10079149B2 Semiconductor device with self-aligned carbon nanotube gate 有权
公开(公告)号：US10079149B2
公开(公告)日：2018-09-18
申请号：US15588976
申请日：2017-05-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Qing Cao , Shu-Jen Han , Ning Li , Jianshi Tang
IPC分类号： H01L21/28 , H01L29/40 , H01L29/49 , H01L29/66
CPC分类号： H01L21/2807 , B82Y10/00 , H01L21/26513 , H01L21/28088 , H01L21/32056 , H01L29/0673 , H01L29/0847 , H01L29/401 , H01L29/4966 , H01L29/517 , H01L29/6653 , H01L29/6656 , H01L29/66568 , H01L29/775 , H01L29/78
摘要： A method of forming a semiconductor device includes forming a channel layer on a substrate. A gate dielectric is deposited on the channel layer, and a mask is patterned on the gate dielectric. An exposed portion of the gate dielectric is removed to expose a first source/drain region and a second source/drain region of the channel layer. A first source/drain contact is formed on the first source/drain region and a second source/drain contact is formed on the second source/drain region. A cap layer is formed over the first source/drain contact and the second source/drain contact, and the mask is removed. Spacers are formed adjacent to sidewalls of the first source/drain contact and the second source/drain contact. An oxide region is formed in the cap layer and a carbon material is deposited on an exposed portion of the gate dielectric.

3. 发明申请

US20180053852A1 Reacted Conductive Gate Electrodes and Methods of Making the Same 审中-公开
公开(公告)号：US20180053852A1
公开(公告)日：2018-02-22
申请号：US15784925
申请日：2017-10-16
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Matthew T. Currie , Richard Hammond
IPC分类号： H01L29/78 , H01L29/161 , H01L29/66 , H01L29/49 , H01L29/45 , H01L29/165 , H01L21/28 , H01L29/10 , H01L29/08 , H01L21/324 , H01L21/285
CPC分类号： H01L29/7848 , H01L21/28052 , H01L21/2807 , H01L21/28255 , H01L21/28518 , H01L21/324 , H01L29/0847 , H01L29/1054 , H01L29/161 , H01L29/165 , H01L29/45 , H01L29/49 , H01L29/665 , H01L29/6659 , H01L29/7842
摘要： A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal to the semiconductor layer and a portion distal to the semiconductor layer. The distal portion includes the first material and the second material. A metal layer formed adjacent to the relaxed semiconductor layer and adjacent to the distal portion of the contact is simultaneously reacted with the relaxed semiconductor layer and with the distal portion of the contact to provide metallic contact material.

4. 发明申请

US20180025918A1 METHOD FOR MANUFACTURING TRANSISTOR AND DISPLAY DEVICE 审中-公开
公开(公告)号：US20180025918A1
公开(公告)日：2018-01-25
申请号：US15654089
申请日：2017-07-19
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shunpei YAMAZAKI , Takashi HAMOCHI , Yasuharu HOSAKA , Toshimitsu OBONAI
IPC分类号： H01L21/3213 , H01L21/18 , H01L29/49 , H01L29/812 , H01L21/28
CPC分类号： H01L21/32137 , H01L21/0214 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/02326 , H01L21/0234 , H01L21/02488 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/18 , H01L21/28035 , H01L21/2807 , H01L21/28079 , H01L29/495 , H01L29/4966 , H01L29/66969 , H01L29/78648 , H01L29/7869 , H01L29/78696 , H01L29/812
摘要： A transistor with high productivity and a method for manufacturing the transistor are provided. In the formation of a bottom-gate transistor using a metal oxide layer as a semiconductor layer where a channel is formed, a gate insulating layer including silicon nitride is formed, and then plasma treatment is successively performed in the same treatment chamber under an atmosphere containing oxygen. After that, the metal oxide layer is formed.

5. 发明授权

US09379213B2 Method for forming doped areas under transistor spacers 有权
标题翻译：在晶体管间隔物下形成掺杂区域的方法
公开(公告)号：US09379213B2
公开(公告)日：2016-06-28
申请号：US14450385
申请日：2014-08-04
申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT , STMICROELECTRONICS SA
发明人： Perrine Batude , Jean-Michel Hartmann , Benoit Sklenard , Maud Vinet
IPC分类号： H01L21/336 , H01L29/78 , H01L29/66 , H01L21/02 , H01L29/16 , H01L29/417 , H01L29/786 , H01L29/161 , H01L21/265 , H01L21/28
CPC分类号： H01L29/66568 , H01L21/02532 , H01L21/02592 , H01L21/02667 , H01L21/26506 , H01L21/26586 , H01L21/2807 , H01L21/28088 , H01L29/16 , H01L29/161 , H01L29/41766 , H01L29/6653 , H01L29/6656 , H01L29/66628 , H01L29/66636 , H01L29/66772 , H01L29/7848 , H01L29/78654
摘要： Method for fabricating a transistor comprising the steps consisting of: forming sacrificial zones in a semi-conductor layer, either side of a transistor channel zone, forming insulating spacers on said sacrificial zones against the sides of the gate of said transistor, removing said sacrificial zones so as to form cavities, with the cavities extending on either side of said channel zone and penetrating under said spacers, forming doped semi-conductor material in said cavities, with said semi-conductor material penetrating under said spacers.
摘要翻译：晶体管的制造方法，包括以下步骤：在晶体管沟道区的任一侧的半导体层中形成牺牲区，在所述牺牲区上形成抵靠所述晶体管的栅极的侧面的绝缘间隔物，去除所述牺牲区以便形成空腔，其中所述空腔在所述通道区域的任一侧上延伸并且穿过所述间隔件，在所述空腔中形成掺杂的半导体材料，所述半导体材料穿透在所述间隔件下方。

6. 发明授权

US09362123B2 Structure and method for integrated devices on different substartes with interfacial engineering 有权
标题翻译：用于界面工程的不同子系统上集成器件的结构和方法
公开(公告)号：US09362123B2
公开(公告)日：2016-06-07
申请号：US13725330
申请日：2012-12-21
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Liang-Gi Yao , I-Ming Chang , Yasutoshi Okuno , Chih-Hao Chang , Shou Zen Chang , Clement Hsingjen Wann
IPC分类号： H01L21/20 , H01L29/78 , H01L27/12 , H01L21/28 , H01L29/66 , H01L29/10 , H01L21/02 , H01L29/51
CPC分类号： H01L21/2807 , H01L21/02381 , H01L21/02532 , H01L29/1054 , H01L29/513 , H01L29/517 , H01L29/66545 , H01L29/66651 , H01L29/785
摘要： The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first semiconductor material and a first reactivity; and a low reactivity capping layer of disposed on the semiconductor substrate, wherein the low reactivity capping layer includes a second semiconductor material and a second reactivity less than the first reactivity, the low reactivity capping layer includes silicon germanium Si1-xGex and x is less than about 30%.
摘要翻译：本公开提供了半导体结构的一个实施例。半导体结构包括具有第一半导体材料和第一反应性的半导体衬底; 以及设置在所述半导体衬底上的低反应性覆盖层，其中所述低反应性覆盖层包括第二半导体材料和小于所述第一反应性的第二反应性，所述低反应性覆盖层包括硅锗Si1-xGex，并且x小于约30％。

7. 发明授权

US09196700B2 Multi-plasma nitridation process for a gate dielectric 有权
标题翻译：用于栅极电介质的多等离子体氮化工艺
公开(公告)号：US09196700B2
公开(公告)日：2015-11-24
申请号：US14640698
申请日：2015-03-06
申请人： GLOBALFOUNDRIES INC.
发明人： Michael P. Chudzik , Barry P. Linder , Shahab Siddiqui
IPC分类号： H01L21/02 , H01L29/51 , H01L27/088 , H01L27/12 , H01L21/28 , H01L21/324 , H01L29/06 , H01L29/10 , H01L29/16 , H01L29/161 , H01L29/423 , H01L21/8234
CPC分类号： H01L29/513 , H01L21/0214 , H01L21/02164 , H01L21/022 , H01L21/02236 , H01L21/02238 , H01L21/02247 , H01L21/02249 , H01L21/02252 , H01L21/02255 , H01L21/0228 , H01L21/02318 , H01L21/02326 , H01L21/02329 , H01L21/0234 , H01L21/2807 , H01L21/28185 , H01L21/28202 , H01L21/324 , H01L21/823412 , H01L27/088 , H01L27/1203 , H01L29/0649 , H01L29/1033 , H01L29/16 , H01L29/161 , H01L29/42364 , H01L29/518
摘要： A gate dielectric can be formed by depositing a first silicon oxide material by a first atomic layer deposition process. The thickness of the first silicon oxide material is selected to correspond to at least 10 deposition cycles of the first atomic layer deposition process. The first silicon oxide material is converted into a first silicon oxynitride material by a first plasma nitridation process. A second silicon oxide material is subsequently deposited by a second atomic layer deposition process. The second silicon oxide material is converted into a second silicon oxynitride material by a second plasma nitridation process. Multiple repetitions of the atomic layer deposition process and the plasma nitridation process provides a silicon oxynitride material having a ratio of nitrogen atoms to oxygen atoms greater than 1/3, which can be advantageously employed to reduce the leakage current through a gate dielectric.
摘要翻译：可以通过利用第一原子层沉积工艺沉积第一氧化硅材料来形成栅极电介质。选择第一氧化硅材料的厚度以对应于第一原子层沉积工艺的至少10个沉积循环。通过第一等离子体氮化工艺将第一氧化硅材料转化为第一氮氧化硅材料。随后通过第二原子层沉积工艺沉积第二氧化硅材料。通过第二等离子体氮化处理将第二氧化硅材料转化为第二氮氧化硅材料。原子层沉积工艺和等离子体氮化处理的多次重复提供氮氮原子与氧原子的比率大于1/3的氮氧化硅材料，其可以有利地用于减少通过栅极电介质的漏电流。

8. 发明授权

US09070738B2 SCR component with temperature-stable characteristics 有权
标题翻译： SCR组件具有温度稳定特性
公开(公告)号：US09070738B2
公开(公告)日：2015-06-30
申请号：US14494692
申请日：2014-09-24
申请人： STMicroelectronics (Tours) SAS
发明人： Samuel Menard
IPC分类号： H01L29/74 , H01L29/16 , H01L29/66 , H01L21/02 , H01L21/322 , H01L29/08 , H01L21/306
CPC分类号： H01L29/74 , H01L21/2807 , H01L21/306 , H01L29/0692 , H01L29/0834 , H01L29/0839 , H01L29/102 , H01L29/32 , H01L29/513 , H01L29/517 , H01L29/66363 , H01L29/66545 , H01L29/7408
摘要： An SCR-type component of vertical structure has a main upper electrode formed on a silicon region of a first conductivity type which is formed in a silicon layer of a second conductivity type. The silicon region is interrupted in first areas where the material of the silicon layer comes into contact with the upper electrode, and is further interrupted in second areas filled with resistive porous silicon extending between the silicon layer and the main upper electrode.
摘要翻译：垂直结构的SCR型分量具有形成在第二导电类型的硅层中的形成在第一导电类型的硅区上的主上电极。在硅层的材料与上电极接触的第一区域中，硅区被中断，并且在硅层和主上电极之间延伸的第二区填充有电阻性多孔硅，进一步中断。

9. 发明申请

US20150099353A1 Non-Volatile Memory Devices and Methods of Manufacturing the Same 审中-公开
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20150099353A1
公开(公告)日：2015-04-09
申请号：US14568653
申请日：2014-12-12
申请人： Jung-Geun JEE , Seok-Hoon KIM , Su-Jin SHIN , Woo-Sung LEE , Tae-Ouk KWON
发明人： Jung-Geun JEE , Seok-Hoon KIM , Su-Jin SHIN , Woo-Sung LEE , Tae-Ouk KWON
IPC分类号： H01L27/115 , H01L21/28
CPC分类号： H01L27/11558 , H01L21/2807 , H01L21/28273 , H01L21/28556 , H01L27/115 , H01L27/11521 , H01L29/42336 , H01L29/66825 , H01L29/7881
摘要： A non-volatile memory device includes a field region that defines an active region in a semiconductor substrate, a floating gate pattern on the active region, a dielectric layer on the floating gate pattern and a control gate on the dielectric layer. The control gate includes a first conductive pattern that has a first composition that crystallizes in a first temperature range, and a second conductive pattern that has a second composition that is different from the first composition and that crystallizes in a second temperature range that is lower than the first temperature range, the first conductive pattern being between the dielectric layer and the second conductive pattern.
摘要翻译：非易失性存储器件包括限定半导体衬底中的有源区域的场区域，有源区域上的浮置栅极图案，浮置栅极图案上的介电层和介电层上的控制栅极。控制栅极包括具有在第一温度范围内结晶的第一组成的第一导电图案和具有与第一组成不同的第二组成的第二导电图案，并且在低于第一组成的第二温度范围内结晶第一温度范围，第一导电图案在介电层和第二导电图案之间。

10. 发明申请

US20140329378A1 GATE ELECTRODE WITH DEPLETION SUPPRESSION AND TUNABLE WORKFUNCTION 有权
标题翻译：门电极具有抑制抑制和可调节功能
公开(公告)号：US20140329378A1
公开(公告)日：2014-11-06
申请号：US14286529
申请日：2014-05-23
申请人： The Board of Trustees of the Leland Stanford Junior University
发明人： Steven Hung , Judy L. Hoyt , James F. Gibbons
IPC分类号： H01L21/28
CPC分类号： H01L21/823828 , H01L21/2807 , H01L21/28079 , H01L21/28088 , H01L21/28562 , H01L21/823842 , H01L29/1054 , H01L29/49 , H01L29/4958
摘要： Semiconductor device performance is improved via a gate structure having a tunable effective workfunction and reduced gate depletion effects. According to an example embodiment, the design threshold voltage of a semiconductor device is adjusted in a manner that includes providing a gate having a workfunction that enables operation of the semiconductor device at a selected voltage. The gate is formed having two different conductive materials with different electric workfunctions that both significantly contribute to the overall workfunction of the gate. The relative composition, thickness, and arrangement of each of the two conductive materials is selected to attain a gate electrode workfunction that is different than the workfunctions of each of the two layers and that sets the threshold voltage of the semiconductor device. The adjustability of the effective workfunction of the gate electrode can be applied to a variety of semiconductor devices. The ability to reduce gate depletion effects also provides enhanced device current drive.
摘要翻译：通过具有可调谐的有效功函数和减少的栅极耗尽效应的栅极结构来提高半导体器件的性能。根据示例性实施例，半导体器件的设计阈值电压被调整为包括提供具有能够使半导体器件处于选定电压的功能的功能门的方式。栅极形成为具有不同电功能的两种不同的导电材料，这两种导电材料都显着地有助于栅极的整体功能。选择两种导电材料中的每一种的相对组成，厚度和布置，以获得不同于两层中的每一层的功函数的栅电极功函数，并设定半导体器件的阈值电压。栅电极的有效功函数的可调性可应用于各种半导体器件。降低栅极耗尽效应的能力还提供增强的器件电流驱动。

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