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1. 发明授权

US06368988B1 Combined gate cap or digit line and spacer deposition using HDP 失效
公开(公告)号：US06368988B1
公开(公告)日：2002-04-09
申请号：US09354572
申请日：1999-07-16
申请人： Weimin Li , Sujit Sharan , Gurtej Sandhu
发明人： Weimin Li , Sujit Sharan , Gurtej Sandhu
IPC分类号： H01L21318
CPC分类号： H01L29/6656 , C23C16/345 , C23C16/402 , H01L21/02164 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/31612 , H01L21/3185 , H01L21/76832 , H01L21/76834 , H01L21/76885
摘要： A method for fabricating gate electrodes and gate interconnects with a protective silicon oxide or silicon nitride cap and spacer formed by high density plasma chemical vapor deposition (HDPCVD). Silicon oxide or silicon nitride is deposited in a reaction zone of a HDPCVD reactor while providing two or more selected substrate bias powers, source powers and/or selected gas mixtures to tailor the shape and thickness of the film for desired applications. In one embodiment, a low bias power of below 500 Watts is provided in a first stage HDPCVD and the bias power is then increased to between 500 and 3000 Watts for a second stage to produce a protective film having thin sidewall spacers for enhanced semiconductor device density and a relatively thick cap.

2. 发明授权

US06524975B2 Combined gate cap or digit line and spacer deposition using HDP 失效
公开(公告)号：US06524975B2
公开(公告)日：2003-02-25
申请号：US09989036
申请日：2001-11-21
申请人： Weimin Li , Sujit Sharan , Gurtej Sandhu
发明人： Weimin Li , Sujit Sharan , Gurtej Sandhu
IPC分类号： H01L21318
CPC分类号： H01L29/6656 , C23C16/345 , C23C16/402 , H01L21/02164 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/31612 , H01L21/3185 , H01L21/76832 , H01L21/76834 , H01L21/76885
摘要： A method for fabricating gate electrodes and gate interconnects with a protective silicon oxide or silicon nitride cap and spacer formed by high density plasma chemical vapor deposition (HDPCVD). Silicon oxide or silicon nitride is deposited in a reaction zone of a HDPCVD reactor while providing two or more selected substrate bias powers, source powers and/or selected gas mixtures to tailor the shape and thickness of the film for desired applications. In one embodiment, a low bias power of below 500 Watts is provided in a first stage HDPCVD and the bias power is then increased to between 500 and 3000 Watts for a second stage to produce a protective film having thin sidewall spacers for enhanced semiconductor device density and a relatively thick cap.

3. 发明授权

US06756293B2 Combined gate cap or digit line and spacer deposition using HDP 失效
标题翻译：使用HDP组合门帽或数字线和间隔层沉积
公开(公告)号：US06756293B2
公开(公告)日：2004-06-29
申请号：US10319694
申请日：2002-12-16
申请人： Weimin Li , Sujit Sharan , Gurtej Sandhu
发明人： Weimin Li , Sujit Sharan , Gurtej Sandhu
IPC分类号： H01L214763
CPC分类号： H01L29/6656 , C23C16/345 , C23C16/402 , H01L21/02164 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/31612 , H01L21/3185 , H01L21/76832 , H01L21/76834 , H01L21/76885
摘要： A method for fabricating gate electrodes and gate interconnects with a protective silicon oxide or silicon nitride cap and spacer formed by high density plasma chemical vapor deposition (HDPCVD). Silicon oxide or silicon nitride is deposited in a reaction zone of a HDPCVD reactor while providing two or more selected substrate bias powers, source powers and/or selected gas mixtures to tailor the shape and thickness of the film for desired applications. In one embodiment, a low bias power of below 500 Watts is provided in a first stage HDPCVD and the bias power is then increased to between 500 and 3000 Watts for a second stage to produce a protective film having thin sidewall spacers for enhanced semiconductor device density and a relatively thick cap.
摘要翻译：一种通过高密度等离子体化学气相沉积（HDPCVD）形成的具有保护性氧化硅或氮化硅帽和间隔物的栅电极和栅极互连的方法。氧化硅或氮化硅沉积在HDPCVD反应器的反应区中，同时提供两种或更多种选择的底物偏压功率，源功率和/或选定的气体混合物以根据期望的应用来定制膜的形状和厚度。在一个实施例中，在第一级HDPCVD中提供低于500瓦的低偏置功率，然后将偏置功率增加到500至3000瓦之间，用于第二级，以产生具有薄侧壁间隔件的保护膜，用于增强半导体器件密度和一个相对较厚的帽子。

4. 发明申请

US20060218762A1 SYSTEM AND METHOD FOR DETECTING FLOW IN A MASS FLOW CONTROLLER 审中-公开
公开(公告)号：US20060218762A1
公开(公告)日：2006-10-05
申请号：US11421701
申请日：2006-06-01
申请人： Gurtej Sandhu , Sujit Sharan , Neal Rueger , Allen Mardian
发明人： Gurtej Sandhu , Sujit Sharan , Neal Rueger , Allen Mardian
IPC分类号： H01L21/00 , H01L21/306 , C23C16/00
CPC分类号： G01F1/40 , G01F1/42 , G01P13/0006 , G01P13/0013 , G01P13/0033 , G05D7/0635 , Y10T137/0396 , Y10T137/7722 , Y10T137/775 , Y10T137/8242
摘要： Systems and methods are provided for detecting flow in a mass flow controller (MFC). The position of a gate in the MFC is sensed or otherwise determined to monitor flow through the MFC and to immediately or nearly immediately detect a flow failure. In one embodiment of the present invention, a novel MFC is provided. The MFC includes an orifice, a mass flow control gate, an actuator and a gate position sensor. The actuator moves the control gate to control flow through the orifice. The gate position sensor determines the gate position and/or gate movement to monitor flow and immediately or nearly immediately detect a flow failure. According to one embodiment of the present invention, the gate position sensor includes a transmitter for transmitting a signal and a receiver for receiving the signal such that the receiver provides an indication of the position of the gate based on the signal received. Other embodiments of the gate position sensor are described herein, as well as systems and methods that incorporate the novel MFC within a semiconductor manufacturing process.

5. 发明申请

US20060205175A1 Methods of forming silicon dioxide layers, and methods of forming trench isolation regions 有权
标题翻译：形成二氧化硅层的方法以及形成沟槽隔离区的方法
公开(公告)号：US20060205175A1
公开(公告)日：2006-09-14
申请号：US11362455
申请日：2006-02-23
申请人： Sujit Sharan , Gurtej Sandhu
发明人： Sujit Sharan , Gurtej Sandhu
IPC分类号： H01L21/76 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02164 , C23C16/045 , C23C16/402 , H01L21/02211 , H01L21/02274 , H01L21/31612 , H01L21/76224
摘要： A method of forming a silicon dioxide layer includes forming a high density plasma proximate a substrate, the plasma comprising silicon dioxide precursors; forming silicon dioxide from the precursors, the silicon dioxide being deposited over the substrate at a deposition rate; and while depositing, etching the deposited silicon dioxide with the plasma at an etch rate; a ratio of the deposition rate to the etch rate being at least about 4:1. Another method includes forming a high density plasma proximate a substrate; flowing gases into the plasma, at least some of the gases forming silicon dioxide; depositing the silicon dioxide formed from the gases over the substrate; and while depositing the silicon dioxide, maintaining a temperature of the substrate at greater than or equal to about 500° C. As an alternative, the method may include not cooling the substrate with a coolant gas while depositing the silicon dioxide.
摘要翻译：形成二氧化硅层的方法包括在基底附近形成高密度等离子体，所述等离子体包含二氧化硅前体; 从前体形成二氧化硅，二氧化硅以沉积速率沉积在衬底上; 并且在沉积时以蚀刻速率用等离子体蚀刻沉积的二氧化硅; 沉积速率与蚀刻速率的比率为至少约4:1。另一种方法包括在基底附近形成高密度等离子体; 流入气体进入等离子体，形成二氧化硅的至少一些气体; 将由气体形成的二氧化硅沉积在衬底上; 并且同时沉积二氧化硅，将基底的温度保持在大于或等于约500℃。作为替代方案，该方法可以包括在沉积二氧化硅的同时不用冷却剂气体冷却基底。

6. 发明申请

US20050020067A1 Chemistry for chemical vapor deposition of titanium containing films 有权
标题翻译：含钛膜的化学气相沉积化学
公开(公告)号：US20050020067A1
公开(公告)日：2005-01-27
申请号：US10913556
申请日：2004-08-06
申请人： Sujit Sharan , Howard Rhodes , Philip Ireland , Gurtej Sandhu
发明人： Sujit Sharan , Howard Rhodes , Philip Ireland , Gurtej Sandhu
IPC分类号： C23C16/14 , C23C16/34 , C23C16/42 , H01L21/285 , H01L21/768 , H01L21/3205 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76843 , C23C16/14 , C23C16/34 , C23C16/42 , H01L21/28568
摘要： Titanium-containing films exhibiting excellent uniformity and step coverage are deposited on semiconductor wafers in a cold wall reactor which has been modified to discharge plasma into the reaction chamber. Titanium tetrabromide, titanium tetraiodide, or titanium tetrachloride, along with hydrogen, enter the reaction chamber and come in contact with a heated semiconductor wafer, thereby depositing a thin titanium-containing film on the wafer's surface. Step coverage and deposition rate are enhanced by the presence of the plasma. The use of titanium tetrabromide or titanium tetraiodide instead of titanium tetrachloride also increases the deposition rate and allows for a lower reaction temperature. Titanium silicide and titanium nitride can also be deposited by this method by varying the gas incorporated with the titanium precursors.
摘要翻译：表现出优异的均匀性和阶梯覆盖率的含钛膜沉积在冷壁反应器中的半导体晶片上，该冷壁反应器已被修改以将等离子体排放到反应室中。四溴化钛，四碘化钛或四氯化钛与氢一起进入反应室并与加热的半导体晶片接触，从而在晶片的表面上沉积薄的含钛膜。通过等离子体的存在增强了步骤覆盖和沉积速率。使用四溴化钛或四碘化钛代替四氯化钛也增加了沉积速率并允许较低的反应温度。也可以通过这种方法通过改变掺入钛前体的气体来沉积硅化钛和氮化钛。

7. 发明申请

US20060223204A1 SYSTEM AND METHOD FOR DETECTING FLOW IN A MASS FLOW CONTROLLER 审中-公开
公开(公告)号：US20060223204A1
公开(公告)日：2006-10-05
申请号：US11421704
申请日：2006-06-01
申请人： Gurtej Sandhu , Sujit Sharan , Neal Rueger , Allen Mardian
发明人： Gurtej Sandhu , Sujit Sharan , Neal Rueger , Allen Mardian
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： G01F1/40 , G01F1/42 , G01P13/0006 , G01P13/0013 , G01P13/0033 , G05D7/0635 , Y10T137/0396 , Y10T137/7722 , Y10T137/775 , Y10T137/8242
摘要： Systems and methods are provided for detecting flow in a mass flow controller (MFC). The position of a gate in the MFC is sensed or otherwise determined to monitor flow through the MFC and to immediately or nearly immediately detect a flow failure. In one embodiment of the present invention, a novel MFC is provided. The MFC includes an orifice, a mass flow control gate, an actuator and a gate position sensor. The actuator moves the control gate to control flow through the orifice. The gate position sensor determines the gate position and/or gate movement to monitor flow and immediately or nearly immediately detect a flow failure. According to one embodiment of the present invention, the gate position sensor includes a transmitter for transmitting a signal and a receiver for receiving the signal such that the receiver provides an indication of the position of the gate based on the signal received. Other embodiments of the gate position sensor are described herein, as well as systems and methods that incorporate the novel MFC within a semiconductor manufacturing process.

8. 发明申请

US20050079731A1 Plasma enhanced chemical vapor deposition methods and semiconductor processing methods of forming layers and shallow trench isolation regions 审中-公开
标题翻译：等离子体增强化学气相沉积方法和形成层和浅沟槽隔离区的半导体加工方法
公开(公告)号：US20050079731A1
公开(公告)日：2005-04-14
申请号：US10620426
申请日：2003-07-17
申请人： Sujit Sharan , Gurtej Sandhu
发明人： Sujit Sharan , Gurtej Sandhu
IPC分类号： C23C16/04 , C23C16/40 , H01L21/316 , H01L21/762 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02164 , C23C16/045 , C23C16/402 , H01L21/02274 , H01L21/31612 , H01L21/76224
摘要： In accordance with an aspect of the invention, a substrate is placed within a plasma enhanced chemical vapor deposition reactor. A plurality of reactant gases are provided within the reactor proximate the substrate under high density plasma conditions effective to form a layer on the substrate. The conditions result in etching portions of the layer during its formation and thereby include a deposition to etch ratio of forming the layer. During the forming, the conditions are changed to change the deposition to etch ratio. In another aspect of the invention, the invention includes a semiconductor processing method of forming shallow trench isolation regions within a semiconductive substrate. Isolation trenches are formed within the semiconductive substrate. The substrate is provided within a plasma enhanced chemical vapor deposition reactor. A silane containing gas, an oxygen containing gas and an inert gas are injected into the reactor under high density plasma conditions effective to form a predominate SiO2 comprising layer on the substrate to overfill the trenches. The conditions result in etching of portions of the layer during its formation and thereby includes a deposition to etch ratio of the forming SiO2 comprising layer. During the forming, the conditions are changed to change the deposition to etch ratio.
摘要翻译：根据本发明的一个方面，将衬底放置在等离子体增强化学气相沉积反应器内。在高密度等离子体条件下，靠近基板的反应器内提供多个反应气体，以有效地在基板上形成一层。条件导致在其形成期间蚀刻该层的部分，从而包括形成该层的沉积 - 蚀刻比。在成形期间，改变条件以改变沉积到蚀刻比。在本发明的另一方面，本发明包括在半导体衬底内形成浅沟槽隔离区的半导体处理方法。绝缘沟槽形成在半导体衬底内。衬底设置在等离子体增强化学气相沉积反应器内。将含硅烷的气体，含氧气体和惰性气体在高密度等离子体条件下注入到反应器中，在等离子体条件下有效地在衬底上形成主要的含SiO 2的层，以使填充沟槽。条件导致在其形成期间蚀刻该层的部分，从而包括形成SiO 2的层的沉积蚀刻比。在成形期间，改变条件以改变沉积到蚀刻比。

9. 发明授权

US5985767A Facet etch for improved step coverage of integrated circuit contacts 有权
标题翻译：方面蚀刻，以改善集成电路触点的台阶覆盖
公开(公告)号：US5985767A
公开(公告)日：1999-11-16
申请号：US228725
申请日：1999-01-12
申请人： Ceredig Roberts , Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
发明人： Ceredig Roberts , Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/768 , H01L23/485 , H01L23/532 , H01L21/00
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76862 , H01L21/76877 , H01L23/485 , H01L23/53223 , H01L21/76844 , H01L2924/0002
摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. A conductive layer is deposited over an insulating layer, either before or after contact opening formation. After both conductive layer deposition and contact formation, a facet etch is performed to slope the conductive layer overlying the contact lip while depositing material from the conductive layer into the lower corner of the contact, where coverage has traditionally been poor. A second conductive layer may then be deposited into the contact to supplement coverage provided by the first conductive layer and the facet etch.
摘要翻译：公开了一种用于提供与导电材料，特别是金属的接触的改进的台阶覆盖的方法。在接触开口形成之前或之后，在绝缘层上沉积导电层。在导电层沉积和接触形成之后，进行小面蚀刻以使覆盖接触唇的导电层倾斜，同时将材料从导电层沉积到接触的下角，其中覆盖传统上较差。然后可以将第二导电层沉积到接触中以补充由第一导电层提供的覆盖层和小面蚀刻。

10. 发明授权

US5963832A Removal of metal cusp for improved contact fill 有权
公开(公告)号：US5963832A
公开(公告)日：1999-10-05
申请号：US184489
申请日：1998-11-02
申请人： Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
发明人： Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
IPC分类号： H01L21/768 , H01L23/485 , H01L21/285
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76844 , H01L21/76855 , H01L21/76862 , H01L21/76864 , H01L21/76877 , H01L23/485 , H01L2924/0002
摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. An initial conductive layer is deposited over an insulating layer either before or after contact opening formation. The deposition process tends to block the contact mouth with a metal overhang, or cusp. After both conductive layer deposition and contact formation a portion of the initial conductive layer is removed, thus removing at least a portion of the metal cusp and opening the contact mouth for further depositions. The invention has particular utility in connection with formation of metal plugs in high-aspect ratio contacts. Embodiments are disclosed wherein the cusp removal comprises mechanical planarization, etching with high viscosity chemicals, and facet etching.

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