专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5985767A Facet etch for improved step coverage of integrated circuit contacts 有权
标题翻译：方面蚀刻，以改善集成电路触点的台阶覆盖
公开(公告)号：US5985767A
公开(公告)日：1999-11-16
申请号：US228725
申请日：1999-01-12
申请人： Ceredig Roberts , Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
发明人： Ceredig Roberts , Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/768 , H01L23/485 , H01L23/532 , H01L21/00
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76862 , H01L21/76877 , H01L23/485 , H01L23/53223 , H01L21/76844 , H01L2924/0002
摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. A conductive layer is deposited over an insulating layer, either before or after contact opening formation. After both conductive layer deposition and contact formation, a facet etch is performed to slope the conductive layer overlying the contact lip while depositing material from the conductive layer into the lower corner of the contact, where coverage has traditionally been poor. A second conductive layer may then be deposited into the contact to supplement coverage provided by the first conductive layer and the facet etch.
摘要翻译：公开了一种用于提供与导电材料，特别是金属的接触的改进的台阶覆盖的方法。在接触开口形成之前或之后，在绝缘层上沉积导电层。在导电层沉积和接触形成之后，进行小面蚀刻以使覆盖接触唇的导电层倾斜，同时将材料从导电层沉积到接触的下角，其中覆盖传统上较差。然后可以将第二导电层沉积到接触中以补充由第一导电层提供的覆盖层和小面蚀刻。

2. 发明授权

US5963832A Removal of metal cusp for improved contact fill 有权
公开(公告)号：US5963832A
公开(公告)日：1999-10-05
申请号：US184489
申请日：1998-11-02
申请人： Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
发明人： Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
IPC分类号： H01L21/768 , H01L23/485 , H01L21/285
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76844 , H01L21/76855 , H01L21/76862 , H01L21/76864 , H01L21/76877 , H01L23/485 , H01L2924/0002
摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. An initial conductive layer is deposited over an insulating layer either before or after contact opening formation. The deposition process tends to block the contact mouth with a metal overhang, or cusp. After both conductive layer deposition and contact formation a portion of the initial conductive layer is removed, thus removing at least a portion of the metal cusp and opening the contact mouth for further depositions. The invention has particular utility in connection with formation of metal plugs in high-aspect ratio contacts. Embodiments are disclosed wherein the cusp removal comprises mechanical planarization, etching with high viscosity chemicals, and facet etching.

3. 发明授权

US5929526A Removal of metal cusp for improved contact fill 失效
公开(公告)号：US5929526A
公开(公告)日：1999-07-27
申请号：US870105
申请日：1997-06-05
申请人： Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
发明人： Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
IPC分类号： H01L21/768 , H01L23/485 , H01L23/48
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76844 , H01L21/76855 , H01L21/76862 , H01L21/76864 , H01L21/76877 , H01L23/485 , H01L2924/0002
摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. An initial conductive layer is deposited over an insulating layer either before or after contact opening formation. The deposition process tends to block the contact mouth with a metal overhang, or cusp. After both conductive layer deposition and contact formation a portion of the initial conductive layer is removed, thus removing at least a portion of the metal cusp and opening the contact mouth for further depositions. The invention has particular utility in connection with formation of metal plugs in high-aspect ratio contacts. Embodiments are disclosed wherein the cusp removal comprises mechanical planarization, etching with high viscosity chemicals, and facet etching.

4. 发明授权

US5861344A Facet etch for improved step coverage of integrated circuit contacts 失效
公开(公告)号：US5861344A
公开(公告)日：1999-01-19
申请号：US958655
申请日：1997-10-27
申请人： Ceredig Roberts , Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
发明人： Ceredig Roberts , Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/768 , H01L23/485 , H01L23/532 , H01L21/00
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76862 , H01L21/76877 , H01L23/485 , H01L23/53223 , H01L21/76844 , H01L2924/0002
摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. A conductive layer is deposited over an insulating layer, either before or after contact opening formation. After both conductive layer deposition and contact formation, a facet etch is performed to slope the conductive layer overlying the contact lip while depositing material from the conductive layer into the lower corner of the contact, where coverage has traditionally been poor. A second conductive layer may then be deposited into the contact to supplement coverage provided by the first conductive layer and the facet etch.

5. 发明授权

US5730835A Facet etch for improved step coverage of integrated circuit contacts 失效
公开(公告)号：US5730835A
公开(公告)日：1998-03-24
申请号：US594842
申请日：1996-01-31
申请人： Ceredig Roberts , Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
发明人： Ceredig Roberts , Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/768 , H01L23/485 , H01L23/532 , H01L21/00 , C23F1/00
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76862 , H01L21/76877 , H01L23/485 , H01L23/53223 , H01L21/76844 , H01L2924/0002
摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. A conductive layer is deposited over an insulating layer, either before or after contact opening formation. After both conductive layer deposition and contact formation, a facet etch is performed to slope the conductive layer overlying the contact lip while depositing material from the conductive layer into the lower corner of the contact, where coverage has traditionally been poor. A second conductive layer may then be deposited into the contact to supplement coverage provided by the first conductive layer and the facet etch.

6. 发明授权

US06423626B1 Removal of metal cusp for improved contact fill 有权
标题翻译：去除金属尖端以改善接触填充
公开(公告)号：US06423626B1
公开(公告)日：2002-07-23
申请号：US09334753
申请日：1999-06-16
申请人： Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
发明人： Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
IPC分类号： H01L214763
CPC分类号： H01L21/76865 , H01L21/76844 , H01L21/76877 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. An initial conductive layer is deposited over an insulating layer either before or after contact opening formation. The deposition process tends to block the contact mouth with a metal overhang, or cusp. After both conductive layer deposition and contact formation a portion of the initial conductive layer is removed, thus removing at least a portion of the metal cusp and opening the contact mouth for further depositions. The invention has particular utility in connection with formation of metal plugs in high-aspect ratio contacts. Embodiments are disclosed wherein the cusp removal comprises mechanical planarization, etching with high viscosity chemicals, and facet etching.
摘要翻译：公开了一种用于提供与导电材料，特别是金属的接触的改进的台阶覆盖的方法。在接触开口形成之前或之后，在绝缘层上沉积初始导电层。沉积过程倾向于以金属悬垂或尖端阻塞接触嘴。在导电层沉积和接触形成两者之后，去除初始导电层的一部分，从而去除金属尖端的至少一部分并打开接触口以进一步沉积。本发明在高纵横比触点形成金属插头方面具有特殊的用途。公开了其中尖端去除包括机械平面化，用高粘度化学品蚀刻和小面蚀刻的实施例。

7. 发明申请

US20060218762A1 SYSTEM AND METHOD FOR DETECTING FLOW IN A MASS FLOW CONTROLLER 审中-公开
公开(公告)号：US20060218762A1
公开(公告)日：2006-10-05
申请号：US11421701
申请日：2006-06-01
申请人： Gurtej Sandhu , Sujit Sharan , Neal Rueger , Allen Mardian
发明人： Gurtej Sandhu , Sujit Sharan , Neal Rueger , Allen Mardian
IPC分类号： H01L21/00 , H01L21/306 , C23C16/00
CPC分类号： G01F1/40 , G01F1/42 , G01P13/0006 , G01P13/0013 , G01P13/0033 , G05D7/0635 , Y10T137/0396 , Y10T137/7722 , Y10T137/775 , Y10T137/8242
摘要： Systems and methods are provided for detecting flow in a mass flow controller (MFC). The position of a gate in the MFC is sensed or otherwise determined to monitor flow through the MFC and to immediately or nearly immediately detect a flow failure. In one embodiment of the present invention, a novel MFC is provided. The MFC includes an orifice, a mass flow control gate, an actuator and a gate position sensor. The actuator moves the control gate to control flow through the orifice. The gate position sensor determines the gate position and/or gate movement to monitor flow and immediately or nearly immediately detect a flow failure. According to one embodiment of the present invention, the gate position sensor includes a transmitter for transmitting a signal and a receiver for receiving the signal such that the receiver provides an indication of the position of the gate based on the signal received. Other embodiments of the gate position sensor are described herein, as well as systems and methods that incorporate the novel MFC within a semiconductor manufacturing process.

8. 发明申请

US20060205175A1 Methods of forming silicon dioxide layers, and methods of forming trench isolation regions 有权
标题翻译：形成二氧化硅层的方法以及形成沟槽隔离区的方法
公开(公告)号：US20060205175A1
公开(公告)日：2006-09-14
申请号：US11362455
申请日：2006-02-23
申请人： Sujit Sharan , Gurtej Sandhu
发明人： Sujit Sharan , Gurtej Sandhu
IPC分类号： H01L21/76 , H01L21/31 , H01L21/469
CPC分类号： H01L21/02164 , C23C16/045 , C23C16/402 , H01L21/02211 , H01L21/02274 , H01L21/31612 , H01L21/76224
摘要： A method of forming a silicon dioxide layer includes forming a high density plasma proximate a substrate, the plasma comprising silicon dioxide precursors; forming silicon dioxide from the precursors, the silicon dioxide being deposited over the substrate at a deposition rate; and while depositing, etching the deposited silicon dioxide with the plasma at an etch rate; a ratio of the deposition rate to the etch rate being at least about 4:1. Another method includes forming a high density plasma proximate a substrate; flowing gases into the plasma, at least some of the gases forming silicon dioxide; depositing the silicon dioxide formed from the gases over the substrate; and while depositing the silicon dioxide, maintaining a temperature of the substrate at greater than or equal to about 500° C. As an alternative, the method may include not cooling the substrate with a coolant gas while depositing the silicon dioxide.
摘要翻译：形成二氧化硅层的方法包括在基底附近形成高密度等离子体，所述等离子体包含二氧化硅前体; 从前体形成二氧化硅，二氧化硅以沉积速率沉积在衬底上; 并且在沉积时以蚀刻速率用等离子体蚀刻沉积的二氧化硅; 沉积速率与蚀刻速率的比率为至少约4:1。另一种方法包括在基底附近形成高密度等离子体; 流入气体进入等离子体，形成二氧化硅的至少一些气体; 将由气体形成的二氧化硅沉积在衬底上; 并且同时沉积二氧化硅，将基底的温度保持在大于或等于约500℃。作为替代方案，该方法可以包括在沉积二氧化硅的同时不用冷却剂气体冷却基底。

9. 发明申请

US20050020067A1 Chemistry for chemical vapor deposition of titanium containing films 有权
标题翻译：含钛膜的化学气相沉积化学
公开(公告)号：US20050020067A1
公开(公告)日：2005-01-27
申请号：US10913556
申请日：2004-08-06
申请人： Sujit Sharan , Howard Rhodes , Philip Ireland , Gurtej Sandhu
发明人： Sujit Sharan , Howard Rhodes , Philip Ireland , Gurtej Sandhu
IPC分类号： C23C16/14 , C23C16/34 , C23C16/42 , H01L21/285 , H01L21/768 , H01L21/3205 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76843 , C23C16/14 , C23C16/34 , C23C16/42 , H01L21/28568
摘要： Titanium-containing films exhibiting excellent uniformity and step coverage are deposited on semiconductor wafers in a cold wall reactor which has been modified to discharge plasma into the reaction chamber. Titanium tetrabromide, titanium tetraiodide, or titanium tetrachloride, along with hydrogen, enter the reaction chamber and come in contact with a heated semiconductor wafer, thereby depositing a thin titanium-containing film on the wafer's surface. Step coverage and deposition rate are enhanced by the presence of the plasma. The use of titanium tetrabromide or titanium tetraiodide instead of titanium tetrachloride also increases the deposition rate and allows for a lower reaction temperature. Titanium silicide and titanium nitride can also be deposited by this method by varying the gas incorporated with the titanium precursors.
摘要翻译：表现出优异的均匀性和阶梯覆盖率的含钛膜沉积在冷壁反应器中的半导体晶片上，该冷壁反应器已被修改以将等离子体排放到反应室中。四溴化钛，四碘化钛或四氯化钛与氢一起进入反应室并与加热的半导体晶片接触，从而在晶片的表面上沉积薄的含钛膜。通过等离子体的存在增强了步骤覆盖和沉积速率。使用四溴化钛或四碘化钛代替四氯化钛也增加了沉积速率并允许较低的反应温度。也可以通过这种方法通过改变掺入钛前体的气体来沉积硅化钛和氮化钛。

10. 发明申请

US20050109271A1 Method of forming refractory metal silicide 有权
$Method of forming refractory metal silicide$
标题翻译：形成难熔金属硅化物的方法
公开(公告)号：US20050109271A1
公开(公告)日：2005-05-26
申请号：US10975714
申请日：2004-10-27
申请人： Gurtej Sandhu , Sujit Sharan
发明人： Gurtej Sandhu , Sujit Sharan
IPC分类号： H01L21/20 , H01L21/28 , H01L21/285 , H01L21/3205 , C30B23/00 , C30B25/00 , C30B28/12 , C30B28/14
CPC分类号： H01L21/02667 , C30B1/02 , C30B29/34 , H01L21/2022 , H01L21/28061 , H01L21/28247 , H01L21/28518 , H01L21/32053 , H01L29/7842
摘要： A method of forming a crystalline phase material includes, a) providing a stress inducing material within or operatively adjacent a crystalline material of a first crystalline phase; and b) annealing the crystalline material of the first crystalline phase under conditions effective to transform it to a second crystalline phase. The stress inducing material preferably induces compressive stress within the first crystalline phase during the anneal to the second crystalline phase to lower the required activation energy to produce a more dense second crystalline phase. Example compressive stress inducing layers include SiO2 and Si3N4, while example stress inducing materials for providing into layers are Ge, W and Co. Where the compressive stress inducing material is provided on the same side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is less than the first phase crystalline material. Where the compressive stress inducing material is provided on the opposite side of a wafer over which the crystalline phase material is provided, it is provided to have a thermal coefficient of expansion which is greater than the first phase crystalline material. Example and preferred crystalline phase materials having two phases are refractory metal silicides, such as TiSix.
摘要翻译：形成结晶相材料的方法包括：a）在第一结晶相的结晶材料内部或在其中邻近的第一结晶相中提供应力诱导材料; 和b）在有效地将其转变成第二结晶相的条件下退火第一结晶相的结晶材料。应力诱导材料优选在与第二结晶相退火期间在第一结晶相内诱导压应力，以降低所需的活化能以产生更致密的第二结晶相。示例性压缩应力诱导层包括SiO 2和Si 3 N 4，而用于提供层的应力诱导材料是Ge，W和Co 在压应力诱导材料设置在其上提供结晶相材料的晶片的相同侧上时，其被设置为具有小于第一相结晶材料的热膨胀系数。在压应力诱导材料设置在提供结晶相材料的晶片的相对侧上的情况下，其被设置为具有大于第一相结晶材料的热膨胀系数。具有两相的实例和优选结晶相材料是难熔金属硅化物，例如TiSi x x。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式