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1. 发明授权

US5985767A Facet etch for improved step coverage of integrated circuit contacts 有权
标题翻译：方面蚀刻，以改善集成电路触点的台阶覆盖
公开(公告)号：US5985767A
公开(公告)日：1999-11-16
申请号：US228725
申请日：1999-01-12
申请人： Ceredig Roberts , Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
发明人： Ceredig Roberts , Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/768 , H01L23/485 , H01L23/532 , H01L21/00
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76862 , H01L21/76877 , H01L23/485 , H01L23/53223 , H01L21/76844 , H01L2924/0002
摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. A conductive layer is deposited over an insulating layer, either before or after contact opening formation. After both conductive layer deposition and contact formation, a facet etch is performed to slope the conductive layer overlying the contact lip while depositing material from the conductive layer into the lower corner of the contact, where coverage has traditionally been poor. A second conductive layer may then be deposited into the contact to supplement coverage provided by the first conductive layer and the facet etch.
摘要翻译：公开了一种用于提供与导电材料，特别是金属的接触的改进的台阶覆盖的方法。在接触开口形成之前或之后，在绝缘层上沉积导电层。在导电层沉积和接触形成之后，进行小面蚀刻以使覆盖接触唇的导电层倾斜，同时将材料从导电层沉积到接触的下角，其中覆盖传统上较差。然后可以将第二导电层沉积到接触中以补充由第一导电层提供的覆盖层和小面蚀刻。

2. 发明授权

US5963832A Removal of metal cusp for improved contact fill 有权
公开(公告)号：US5963832A
公开(公告)日：1999-10-05
申请号：US184489
申请日：1998-11-02
申请人： Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
发明人： Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
IPC分类号： H01L21/768 , H01L23/485 , H01L21/285
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76844 , H01L21/76855 , H01L21/76862 , H01L21/76864 , H01L21/76877 , H01L23/485 , H01L2924/0002
摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. An initial conductive layer is deposited over an insulating layer either before or after contact opening formation. The deposition process tends to block the contact mouth with a metal overhang, or cusp. After both conductive layer deposition and contact formation a portion of the initial conductive layer is removed, thus removing at least a portion of the metal cusp and opening the contact mouth for further depositions. The invention has particular utility in connection with formation of metal plugs in high-aspect ratio contacts. Embodiments are disclosed wherein the cusp removal comprises mechanical planarization, etching with high viscosity chemicals, and facet etching.

3. 发明授权

US5929526A Removal of metal cusp for improved contact fill 失效
公开(公告)号：US5929526A
公开(公告)日：1999-07-27
申请号：US870105
申请日：1997-06-05
申请人： Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
发明人： Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
IPC分类号： H01L21/768 , H01L23/485 , H01L23/48
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76844 , H01L21/76855 , H01L21/76862 , H01L21/76864 , H01L21/76877 , H01L23/485 , H01L2924/0002
摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. An initial conductive layer is deposited over an insulating layer either before or after contact opening formation. The deposition process tends to block the contact mouth with a metal overhang, or cusp. After both conductive layer deposition and contact formation a portion of the initial conductive layer is removed, thus removing at least a portion of the metal cusp and opening the contact mouth for further depositions. The invention has particular utility in connection with formation of metal plugs in high-aspect ratio contacts. Embodiments are disclosed wherein the cusp removal comprises mechanical planarization, etching with high viscosity chemicals, and facet etching.

4. 发明授权

US5861344A Facet etch for improved step coverage of integrated circuit contacts 失效
公开(公告)号：US5861344A
公开(公告)日：1999-01-19
申请号：US958655
申请日：1997-10-27
申请人： Ceredig Roberts , Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
发明人： Ceredig Roberts , Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/768 , H01L23/485 , H01L23/532 , H01L21/00
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76862 , H01L21/76877 , H01L23/485 , H01L23/53223 , H01L21/76844 , H01L2924/0002
摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. A conductive layer is deposited over an insulating layer, either before or after contact opening formation. After both conductive layer deposition and contact formation, a facet etch is performed to slope the conductive layer overlying the contact lip while depositing material from the conductive layer into the lower corner of the contact, where coverage has traditionally been poor. A second conductive layer may then be deposited into the contact to supplement coverage provided by the first conductive layer and the facet etch.

5. 发明授权

US5730835A Facet etch for improved step coverage of integrated circuit contacts 失效
公开(公告)号：US5730835A
公开(公告)日：1998-03-24
申请号：US594842
申请日：1996-01-31
申请人： Ceredig Roberts , Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
发明人： Ceredig Roberts , Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/768 , H01L23/485 , H01L23/532 , H01L21/00 , C23F1/00
CPC分类号： H01L21/76865 , H01L21/76843 , H01L21/76862 , H01L21/76877 , H01L23/485 , H01L23/53223 , H01L21/76844 , H01L2924/0002
摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. A conductive layer is deposited over an insulating layer, either before or after contact opening formation. After both conductive layer deposition and contact formation, a facet etch is performed to slope the conductive layer overlying the contact lip while depositing material from the conductive layer into the lower corner of the contact, where coverage has traditionally been poor. A second conductive layer may then be deposited into the contact to supplement coverage provided by the first conductive layer and the facet etch.

6. 发明授权

US06423626B1 Removal of metal cusp for improved contact fill 有权
标题翻译：去除金属尖端以改善接触填充
公开(公告)号：US06423626B1
公开(公告)日：2002-07-23
申请号：US09334753
申请日：1999-06-16
申请人： Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
发明人： Anand Srinivasan , Gurtej Sandhu , Sujit Sharan
IPC分类号： H01L214763
CPC分类号： H01L21/76865 , H01L21/76844 , H01L21/76877 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. An initial conductive layer is deposited over an insulating layer either before or after contact opening formation. The deposition process tends to block the contact mouth with a metal overhang, or cusp. After both conductive layer deposition and contact formation a portion of the initial conductive layer is removed, thus removing at least a portion of the metal cusp and opening the contact mouth for further depositions. The invention has particular utility in connection with formation of metal plugs in high-aspect ratio contacts. Embodiments are disclosed wherein the cusp removal comprises mechanical planarization, etching with high viscosity chemicals, and facet etching.
摘要翻译：公开了一种用于提供与导电材料，特别是金属的接触的改进的台阶覆盖的方法。在接触开口形成之前或之后，在绝缘层上沉积初始导电层。沉积过程倾向于以金属悬垂或尖端阻塞接触嘴。在导电层沉积和接触形成两者之后，去除初始导电层的一部分，从而去除金属尖端的至少一部分并打开接触口以进一步沉积。本发明在高纵横比触点形成金属插头方面具有特殊的用途。公开了其中尖端去除包括机械平面化，用高粘度化学品蚀刻和小面蚀刻的实施例。

7. 发明授权

US6027970A Method of increasing capacitance of memory cells incorporating hemispherical grained silicon 失效
公开(公告)号：US6027970A
公开(公告)日：2000-02-22
申请号：US650916
申请日：1996-05-17
申请人： Sujit Sharan , Thomas A. Figura , Anand Srinivasan , Gurtej S. Sandhu
发明人： Sujit Sharan , Thomas A. Figura , Anand Srinivasan , Gurtej S. Sandhu
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L27/1085 , H01L28/82 , Y10S438/964
摘要： Disclosed is a method of increasing capacitance of a memory cell capacitor. A bottom electrode, comprising a hemispherical grained (HSG) silicon layer, is subjected to a dry etch process. The etch tends to separate the individual grains of the HSG silicon, thereby facilitating formation of a uniformly thick capacitor dielectric over the HSG silicon surface. Average thickness of the dielectric may therefore be reduced while maintaining reliability of the memory cell. The described embodiments include HCl/HF vapor etch, and NF.sub.3 plasma etch. Both of the preferred embodiments are configured to operate isotropically. Due to precisely controllable etch rates, the dry etch of the present invention is viable for separating grains of HSG silicon layers incorporated into extremely dense circuits (e.g., 64 Mbit DRAM) and correspondingly scaled down circuit dimensions.

8. 发明授权

US6077754A Methods of forming a silicon nitride film, a capacitor dielectric layer and a capacitor 失效
标题翻译：形成氮化硅膜，电容器电介质层和电容器的方法
公开(公告)号：US6077754A
公开(公告)日：2000-06-20
申请号：US18925
申请日：1998-02-05
申请人： Anand Srinivasan , Sujit Sharan , Gurtej S. Sandhu
发明人： Anand Srinivasan , Sujit Sharan , Gurtej S. Sandhu
IPC分类号： H01L21/02 , H01L21/318
CPC分类号： H01L28/40 , H01L21/3185
摘要： A method of forming silicon nitride includes, a) forming a first layer comprising silicon nitride over a substrate; b) forming a second layer comprising silicon on the first layer; and c) nitridizing silicon of the second layer into silicon nitride to form a silicon nitride comprising layer, said silicon nitride comprising layer comprising silicon nitride of the first and second layers. Further, a method of forming a capacitor dielectric layer of silicon nitride includes, a) forming a first capacitor plate layer; b) forming a first silicon nitride layer over the first capacitor plate layer; c) forming a silicon layer on the silicon nitride layer; d) nitridizing the silicon layer into a second silicon nitride layer; and e) forming a second capacitor plate layer over the second silicon nitride layer. Also, a method of forming a capacitor dielectric layer over a capacitor plate layer includes, a) forming a first layer of dielectric material over a capacitor plate layer; b) conducting a pin-hole widening wet etch of the first layer; and c) after the wet etch, forming a pin-hole plugging second layer of dielectric material on the first layer and within the widened pin-holes.
摘要翻译：一种形成氮化硅的方法包括：a）在衬底上形成包含氮化硅的第一层; b）在第一层上形成包含硅的第二层; 以及c）将所述第二层的硅氮化成氮化硅以形成包含氮化硅的层，所述氮化硅层包括第一层和第二层的氮化硅。此外，形成氮化硅电容器电介质层的方法包括：a）形成第一电容器板层; b）在所述第一电容器板层上形成第一氮化硅层; c）在氮化硅层上形成硅层; d）将硅层氮化成第二氮化硅层; 以及e）在所述第二氮化硅层上方形成第二电容器板层。此外，在电容器板层上形成电容器电介质层的方法包括：a）在电容器板层上形成介电材料的第一层; b）进行第一层的针孔加宽湿蚀刻; 以及c）在湿蚀刻之后，在第一层上和扩宽的针孔内形成针孔堵塞的第二介电材料层。

9. 发明授权

US06429071B1 Method of increasing capacitance of memory cells incorporating hemispherical grained silicon 有权
标题翻译：增加包含半球形晶粒硅的存储单元电容的方法
公开(公告)号：US06429071B1
公开(公告)日：2002-08-06
申请号：US09481276
申请日：2000-01-11
申请人： Sujit Sharan , Thomas A. Figura , Anand Srinivasan , Gurtej S. Sandhu
发明人： Sujit Sharan , Thomas A. Figura , Anand Srinivasan , Gurtej S. Sandhu
IPC分类号： H01L218242
CPC分类号： H01L27/1085 , H01L28/82 , Y10S438/964
摘要： Disclosed is a method of increasing capacitance of a memory cell capacitor. A bottom electrode, comprising a hemispherical grained (HSG) silicon layer, is subjected to a dry etch process. The etch tends to separate the individual grains of the HSG silicon, thereby facilitating formation of a uniformly thick capacitor dielectric over the HSG silicon surface. Average thickness of the dielectric may therefore be reduced while maintaining reliability of the memory cell. The described embodiments include HCl/HF vapor etch, and NF3 plasma etch. Both of the preferred embodiments are configured to operate isotropically. Due to precisely controllable etch rates, the dry etch of the present invention is viable for separating grains of HSG silicon layers incorporated into extremely dense circuits (e.g., 64 Mbit DRAM) and correspondingly scaled down circuit dimensions.
摘要翻译：公开了增加存储单元电容器的电容的方法。包括半球形颗粒（HSG）硅层的底部电极经受干蚀刻工艺。蚀刻倾向于分离HSG硅的各个晶粒，从而有助于在HSG硅表面上形成均匀厚的电容器电介质。因此，可以在保持存储单元的可靠性的同时降低电介质的平均厚度。所描述的实施例包括HCl / HF蒸气蚀刻和NF3等离子体蚀刻。两个优选实施例被配置成各向同性地操作。由于精确可控的蚀刻速率，本发明的干蚀刻对于分离结合到非常密集的电路（例如64Mbit DRAM）中的HSG硅层的晶粒和相应的缩小的电路尺寸是可行的。

10. 发明授权

US5882978A Methods of forming a silicon nitride film, a capacitor dielectric layer and a capacitor 失效
公开(公告)号：US5882978A
公开(公告)日：1999-03-16
申请号：US844771
申请日：1997-04-22
申请人： Anand Srinivasan , Sujit Sharan , Gurtej S. Sandhu
发明人： Anand Srinivasan , Sujit Sharan , Gurtej S. Sandhu
IPC分类号： H01L21/02 , H01L21/318
CPC分类号： H01L28/40 , H01L21/3185
摘要： A method of forming silicon nitride includes, a) forming a first layer comprising silicon nitride over a substrate; b) forming a second layer comprising silicon on the first layer; and c) nitridizing silicon of the second layer into silicon nitride to form a silicon nitride comprising layer, said silicon nitride comprising layer comprising silicon nitride of the first and second layers. Further, a method of forming a capacitor dielectric layer of silicon nitride includes, a) forming a first capacitor plate layer; b) forming a first silicon nitride layer over the first capacitor plate layer; c) forming a silicon layer on the silicon nitride layer; d) nitridizing the silicon layer into a second silicon nitride layer; and e) forming a second capacitor plate layer over the second silicon nitride layer. Also, a method of forming a capacitor dielectric layer over a capacitor plate layer includes, a) forming a first layer of dielectric material over a capacitor plate layer; b) conducting a pin-hole widening wet etch of the first layer; and c) after the wet etch, forming a pin-hole plugging second layer of dielectric material on the first layer and within the widened pin-holes.

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