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1. 发明授权

US06992934B1 Read bitline inhibit method and apparatus for voltage mode sensing 有权
标题翻译：读取位线抑制方法和电压模式检测装置
公开(公告)号：US06992934B1
公开(公告)日：2006-01-31
申请号：US11080595
申请日：2005-03-15
申请人： Vishal Sarin , Hieu Van Tran , Jack Frayer
发明人： Vishal Sarin , Hieu Van Tran , Jack Frayer
IPC分类号： G11C16/08
CPC分类号： G11C11/5642
摘要： A multilevel memory system uses a source line driver circuit and a read bitline inhibit driver circuit to eliminate inhibit offset currents on unselected bitlines before memory operations of selected memory cells to equalize voltages before the operation.
摘要翻译：多电平存储器系统使用源极线驱动电路和读位线禁止驱动器电路来消除在所选择的存储器单元的存储器操作之前对未选位线的禁止偏移电流，以在操作之前对电压进行均衡。

2. 发明授权

US07015537B2 Isolation-less, contact-less array of nonvolatile memory cells each having a floating gate for storage of charges, and methods of manufacturing, and operating therefor 有权
标题翻译：非易失性存储单元的无隔离阵列，每个非易失性存储单元均具有用于存储电荷的浮动栅极，以及制造方法和操作方法
公开(公告)号：US07015537B2
公开(公告)日：2006-03-21
申请号：US10822944
申请日：2004-04-12
申请人： Dana Lee , Hieu Van Tran , Jack Frayer
发明人： Dana Lee , Hieu Van Tran , Jack Frayer
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , G11C16/0433 , G11C16/0458 , G11C16/0491 , G11C16/14 , H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/42328 , H01L29/42336 , H01L29/7887
摘要： An isolation-less, contact-less nonvolatile memory array has a plurality of memory cells each with a floating gate for the storage of charges thereon, arranged in a plurality of rows and columns. Each memory cell can be of a number of different types. All the bit lines and source lines of the various embodiments are buried and are contact-less. In a first embodiment, each cell can be represented by a stacked gate floating gate transistor coupled to a separate assist transistor. The entire array can be planar; or in a preferred embodiment each of the floating gate transistors is in a trench; or each of the assist transistors is in a trench. In a second embodiment, each cell can be represented by a stacked gate floating gate transistor with the transistor in a trench. In a third embodiment, each cell can be represented by two stacked gate floating gate transistors coupled to a separate assist transistor, positioned between the two stacked gate floating gate transistors. The entire array can be planar; or in a preferred embodiment each of the floating gate transistors is in a trench; or each of the assist transistors is in a trench. Novel methods to manufacture the arrays and methods to program, erase, and read each of these embodiments of the memory cells is disclosed.
摘要翻译：无隔离的非接触式非易失性存储器阵列具有多个存储单元，每个存储单元具有用于在其上存储电荷的浮动栅极，其布置成多个行和列。每个存储单元可以是多种不同的类型。各种实施例的所有位线和源极线被掩埋并且是无接触的。在第一实施例中，每个单元可以由耦合到单独的辅助晶体管的堆叠栅极浮栅晶体管表示。整个阵列可以是平面的; 或者在优选实施例中，每个浮栅晶体管处于沟槽中; 或者每个辅助晶体管处于沟槽中。在第二实施例中，每个单元可以由晶体管在沟槽中的层叠栅极浮栅晶体管表示。在第三实施例中，每个单元可以由耦合到位于两个堆叠的栅极浮置栅极晶体管之间的单独的辅助晶体管的两个堆叠的栅极浮栅晶体管表示。整个阵列可以是平面的; 或者在优选实施例中，每个浮栅晶体管处于沟槽中; 或者每个辅助晶体管处于沟槽中。公开了制造阵列的新方法和编程，擦除和读取存储器单元的这些实施例的每一个的方法。

3. 发明申请

US20060072363A1 High speed and high precision sensing for digital multilevel non-volatile memory system 有权
公开(公告)号：US20060072363A1
公开(公告)日：2006-04-06
申请号：US11283195
申请日：2005-11-18
申请人： Hieu Tran , Jack Frayer , William Saiki , Michael Briner
发明人： Hieu Tran , Jack Frayer , William Saiki , Michael Briner
IPC分类号： G11C7/02
CPC分类号： G11C11/5642 , G11C7/06 , G11C16/28
摘要： A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.

4. 发明申请

US20050104116A1 Stacked gate memory cell with erase to gate, array, and method of manufacturing 有权
标题翻译：具有擦除到栅极，阵列和制造方法的堆叠栅极存储单元
公开(公告)号：US20050104116A1
公开(公告)日：2005-05-19
申请号：US10714243
申请日：2003-11-13
申请人： Bomy Chen , Hieu Tran , Dana Lee , Jack Frayer
发明人： Bomy Chen , Hieu Tran , Dana Lee , Jack Frayer
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0491 , H01L27/115 , H01L29/7885
摘要： A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injection from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the floating gate to the control gate. Finally, to increase the density, each cell can be made in a trench.
摘要翻译：堆叠式非易失性存储器浮栅器件具有控制栅极。通过从漏极到浮动栅极的热通道电子注入来实现阵列中的单元的编程。擦除由Fowler-Nordheim发生，电子从浮动栅极隧道到控制门。最后，为了增加密度，可以在沟槽中制造每个单元。

5. 发明授权

US07826267B2 Method and apparatus for reading and programming a non-volatile memory cell in a virtual ground array 有权
标题翻译：用于读取和编程虚拟地阵列中的非易失性存储单元的方法和装置
公开(公告)号：US07826267B2
公开(公告)日：2010-11-02
申请号：US12126853
申请日：2008-05-23
申请人： Jack Frayer , Ya-Fen Lin , Gianfranco Pellegrini , William Saiki , Changyuan Chen , Xiuhong Chen
发明人： Jack Frayer , Ya-Fen Lin , Gianfranco Pellegrini , William Saiki , Changyuan Chen , Xiuhong Chen
IPC分类号： G11C16/06
CPC分类号： G11C16/0475 , G11C11/5642 , G11C11/5671 , G11C16/0458 , G11C16/0491 , G11C2211/5612
摘要： A method and apparatus for dynamic programming and dynamic reading of a select non-volatile memory cell in a virtual grounds array is disclosed. In the dynamic read operation the global bit lines and the associated local bit lines are connected to a precharged voltage. One of the first or second global bit lines is connected to a low voltage such as ground, wherein the one global bit line connected to ground also connects to the local bit line for sensing the select non-volatile memory cell. The state of the select non-volatile memory cell is detected by detecting the sense amplifier connected to the global bit line, other than the one global bit line. In a dynamic programming operation, the first and second global bit lines and their associated local bit lines are precharged to a first voltage. One of the first or second global bit line and its associated local bit lines is connected to a second voltage.
摘要翻译：公开了一种用于虚拟接地阵列中的选择非易失性存储单元的动态编程和动态读取的方法和装置。在动态读取操作中，全局位线和相关联的局部位线连接到预充电电压。第一或第二全局位线中的一个连接到诸如地的低电压，其中连接到地的一个全局位线还连接到本地位线以感测选择的非易失性存储单元。通过检测连接到全局位线的读出放大器来检测选择非易失性存储单元的状态，而不是一个全局位线。在动态编程操作中，第一和第二全局位线及其相关联的局部位线被预充电到第一电压。第一或第二全局位线之一及其相关的局部位线连接到第二电压。

6. 发明申请

US20090290430A1 Method And Apparatus For Reading And Programming A Non-Volatile Memory Cell In A Virtual Ground Array 有权
公开(公告)号：US20090290430A1
公开(公告)日：2009-11-26
申请号：US12126853
申请日：2008-05-23
申请人： Jack Frayer , Ya-Fen Lin , Gianfranco Pellegrini , William Saiki , Changyuan Chen , Xiuhong Chen
发明人： Jack Frayer , Ya-Fen Lin , Gianfranco Pellegrini , William Saiki , Changyuan Chen , Xiuhong Chen
IPC分类号： G11C16/06
CPC分类号： G11C16/0475 , G11C11/5642 , G11C11/5671 , G11C16/0458 , G11C16/0491 , G11C2211/5612
摘要： A method and apparatus for dynamic programming and dynamic reading of a select non-volatile memory cell in a virtual grounds array is disclosed. The array of non-volatile memory cells are arranged in a plurality of rows and columns, wherein each cell in the same column share a first local bit line to one side and share a second local bit line to another side. Alternating local bit lines are connected to a first global bit line and other alternating local bit lines are connected to a second global bit line with the global bit lines connected to a sense amplifier. In the dynamic read operation the global bit lines and the associated local bit lines are connected to a precharged voltage. One of the first or second global bit lines is connected to a low voltage such as ground, wherein the one global bit line connected to ground also connects to the local bit line for sensing the select non-volatile memory cell. The state of the select non-volatile memory cell is detected by detecting the sense amplifier connected to the global bit line, other than the one global bit line. In a dynamic programming operation, the first and second global bit lines and their associated local bit lines are precharged to a first voltage. One of the first or second global bit line and its associated local bit lines is connected to a second voltage, wherein the associated local bit lines of the one global bit line include a select bit line connected to a programming terminal of the select non-volatile memory cell. The voltage differential between the second voltage and the first voltage is insufficient to cause programming of the select non-volatile memory cell. The bit line, other than the select bit line of the select non-volatile memory cell, is connected to a low voltage such as ground. The voltage differential between the second voltage and ground is sufficient to cause programming of the select non-volatile memory cell. In another embodiment of the programming operation, a local bit line connected to a programming terminal of a select non-volatile memory cell is precharged to a first voltage and then boosted to a programming voltage by precharging an adjacent local bit line.

7. 发明申请

US20050138273A1 Nonvolatile memory device capable of simultaneous erase and program of different blocks 失效
标题翻译：非易失性存储器件能够同时擦除和编程不同的块
公开(公告)号：US20050138273A1
公开(公告)日：2005-06-23
申请号：US10744561
申请日：2003-12-22
申请人： Jack Frayer
发明人： Jack Frayer
IPC分类号： G06F13/28 , G11C8/12 , G11C16/10 , G11C16/16
CPC分类号： G11C8/12 , G11C16/10 , G11C16/16 , G11C2216/24
摘要： An integrated circuit memory device has a memory array which is partitioned into a plurality of blocks. Each block has an associated row decoder. Each block has a plurality of local bit lines connecting memory cells arranged in the same column. The row decoder is connected to a plurality of row lines which are connected to memory cells arranged in the same row. A plurality of global column lines traverse across a plurality of blocks with each global column line associated with a local bit line from each of the blocks. A column decoder is connected to the plurality of the global column lines. A switch connects each global column line with its associated local bit line from each of the blocks. A control circuit determines when a particular block is to be programmed and a different block needs to be erased and activates the switches accordingly to cause the erase voltage to apply to one block and the programming voltage to apply to the second block.
摘要翻译：集成电路存储器件具有被划分成多个块的存储器阵列。每个块具有相关联的行解码器。每个块具有连接布置在同一列中的存储单元的多个局部位线。行解码器连接到连接到排列在同一行中的存储单元的多行行。多个全局列线穿过多个块，每个全局列线与来自每个块的局部位线相关联。列解码器连接到多个全局列线。一个开关将每个全局列线与其相关的局部位线连接起来。控制电路确定特定块何时被编程，并且需要擦除不同的块，并且相应地激活开关以使得擦除电压施加到一个块并且编程电压被应用于第二块。

8. 发明申请

US20070076489A1 Word line voltage boosting circuit and a memory array incorporating same 有权
公开(公告)号：US20070076489A1
公开(公告)日：2007-04-05
申请号：US11241582
申请日：2005-09-30
申请人： Ya-Fen Lin , Elbert Lin , Hieu Tran , Jack Frayer , Bomy Chen
发明人： Ya-Fen Lin , Elbert Lin , Hieu Tran , Jack Frayer , Bomy Chen
IPC分类号： G11C11/34
CPC分类号： G11C8/08 , G11C16/08
摘要： A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to a first voltage source. The word line is also connected through a switch to a second source voltage source. A sequencing circuit activates the switch such that the word line is connected to the second voltage source, and the other end of the capacitor is not connected to the first voltage source. Then the sequencing circuit causes the switch to disconnect the word line from the second voltage source, and connect the second end of the capacitor to the first voltage source. The alternate switching of the connection boosts the voltage on the word line. In a second embodiment, a first word line is electrically connected to a first switch to a first voltage source. An adjacent word line, capacitively coupled to the first word line, is electrically connected to a second switch to a second voltage source. A sequencing circuit activates the first switch and the second switch such that the first word line is connected to the first voltage source, and the second word line is disconnected from the second voltage source. Then the sequencing circuit causes the first switch to disconnect the first word line from the first voltage source, and causes the second word line to be electrically connected to the second voltage source. The alternate switching of the connection boosts the voltage on the first word line, caused by its capacitive coupling to the second word line. A boosted voltage on the word line may be used to improve cycling and yield, where the memory cells of the array are of the floating gate type and erase through the mechanism of Fowler-Nordheim tunneling from the floating gate to a control gate which is connected to the word line.

9. 发明授权

US07190018B2 Bi-directional read/program non-volatile floating gate memory cell with independent controllable control gates, and array thereof, and method of formation 有权
标题翻译：具有独立可控制控制栅极的双向读/写非易失性浮栅存储单元及其阵列及其形成方法
公开(公告)号：US07190018B2
公开(公告)日：2007-03-13
申请号：US10409407
申请日：2003-04-07
申请人： Bomy Chen , Sohrab Kianian , Jack Frayer
发明人： Bomy Chen , Sohrab Kianian , Jack Frayer
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0458 , G11C16/0483 , G11C16/0491 , H01L27/115
摘要： A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. An independently controllable control gate is insulated from each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate. The independently controllable control gates permit an array of such memory cells to operate in a NAND configuration.
摘要翻译：双向读/写非易失性存储单元和阵列能够实现高密度。每个存储单元具有两个间隔开的浮动栅极，用于在其上存储电荷。电池具有间隔开的源极/漏极区域，其间具有沟道，沟道具有三个部分。浮动门之一在第一部分之上; 另一个浮栅位于第二部分之上，栅电极控制第一和第二部分之间的第三部分中的沟道的导通。独立可控的控制栅极与源极/漏极区域中的每一个绝缘，并且还电容耦合到浮动栅极。通过热通道电子注入的电池程序，并通过Fowler-Nordheim将电子从浮动栅极隧穿到栅电极而擦除。双向读取允许将单元编程为存储位，每个浮动栅极中有一位。独立可控的控制门允许这种存储器单元的阵列在NAND配置中操作。

10. 发明申请

US20050213386A1 Nonvolatile memory cell having floating gate, control gate and separate erase gate, an array of such memory cells, and method of manufacturing 有权
公开(公告)号：US20050213386A1
公开(公告)日：2005-09-29
申请号：US11078562
申请日：2005-02-28
申请人： Amitay Levi , Pavel Klinger , Bomy Chen , Hieu Tran , Dana Lee , Jack Frayer
发明人： Amitay Levi , Pavel Klinger , Bomy Chen , Hieu Tran , Dana Lee , Jack Frayer
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , G11C16/04
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328 , H01L29/7885
摘要： A nonvolatile memory cell having a floating gate for the storage of charges thereon has a control gate and a separate erase gate. The cell is programmed by hot channel electron injection and is erased by poly to poly Fowler-Nordheim tunneling. A method for making an array of unidirectional cells in a planar substrate, as well as an array of bidirectional cells in a substrate having a trench, is disclosed. An array of such cells and a method of making such an array is also disclosed.

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