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1. 发明授权

US07326614B2 Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby 有权
标题翻译：形成具有掩埋位线和升高源极线的浮动栅极存储器单元的半导体存储器阵列的自对准方法以及由此制成的存储器阵列
公开(公告)号：US07326614B2
公开(公告)日：2008-02-05
申请号：US10997382
申请日：2004-11-23
申请人： Sohrab Kianian
发明人： Sohrab Kianian
IPC分类号： H01L21/336
CPC分类号： H01L29/66825 , G11C16/0425 , H01L21/28273 , H01L27/115 , H01L27/11556
摘要： A method of forming an array of floating gate memory cells, and an array formed thereby, that includes source and drain regions formed in a substrate, and a conductive block of material disposed over the source region. The floating gate is formed as a thin, L-shaped layer of conductive material having a first portion disposed over the channel region and a second portion extending vertically along the conductive block. The control gate includes a first portion disposed adjacent to and insulated from a distal end of the floating gate first portion, and a second portion disposed adjacent to the channel region. A portion of the control gate could extend into a trench formed into the substrate, wherein the drain region is formed underneath the trench, and the channel region has a first portion extending along the trench sidewall and a second portion extending along the substrate surface.
摘要翻译：形成浮置栅极存储单元阵列的方法，以及由其形成的阵列，其包括形成在衬底中的源极和漏极区域，以及设置在源极区域上的材料的导电块。浮栅形成为薄的L形导电材料层，其具有设置在沟道区域上的第一部分和沿导电块垂直延伸的第二部分。所述控制栅极包括与所述浮置栅极第一部分的远端相邻并绝缘的第一部分，以及邻近所述沟道区设置的第二部分。控制栅极的一部分可以延伸到形成到衬底中的沟槽中，其中漏极区形成在沟槽下方，并且沟道区具有沿着沟槽侧壁延伸的第一部分和沿衬底表面延伸的第二部分。

2. 发明申请

US20070007581A1 Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same 有权
标题翻译：具有擦除栅极的非平面非易失性存储单元及其阵列及其制造方法
公开(公告)号：US20070007581A1
公开(公告)日：2007-01-11
申请号：US11520993
申请日：2006-09-14
申请人： Bomy Chen , Sohrab Kianian , Yaw Hu
发明人： Bomy Chen , Sohrab Kianian , Yaw Hu
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328 , H01L29/42336 , H01L29/7885
摘要： A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. An erase gate is disposed in the trench adjacent to and insulated from the floating gate. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the erase gate, and electrically connected to the source region.
摘要翻译：存储单元具有形成在半导体衬底的表面中的沟槽，以及在其间形成沟道区的间隔开的源极和漏极区。源极区形成在沟槽下方，并且沟道区域包括沿着沟槽的侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。导电浮置栅极设置在沟槽中，与沟道区域第一部分相邻并与其绝缘。导电控制栅极设置在沟道区第二部分之上并与沟道区第二部分绝缘。擦除栅极设置在与浮动栅极相邻并与浮栅绝缘的沟槽中。一块导电材料至少有一个下部设置在沟槽中，与沟槽相邻并与擦除栅绝缘，并与源极区电连接。

3. 发明授权

US06917069B2 Semiconductor memory array of floating gate memory cells with buried bit-line and vertical word line transistor 有权
标题翻译：具有埋置位线和垂直字线晶体管的浮动存储单元的半导体存储器阵列
公开(公告)号：US06917069B2
公开(公告)日：2005-07-12
申请号：US09982413
申请日：2001-10-17
申请人： Sohrab Kianian , Chih Hsin Wang
发明人： Sohrab Kianian , Chih Hsin Wang
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42332 , H01L29/7885
摘要： A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, and an array formed thereby, whereby each memory cell includes a trench formed into a surface of a semiconductor substrate, spaced apart source and drain regions with a channel region formed therebetween. The drain region is formed underneath the trench, and the channel region includes a first portion that extends substantially vertically along a sidewall of the trench and a second portion that extends substantially horizontally along the surface of the substrate. An electrically conductive floating gate is formed over and insulated from at least a portion of the channel region and a portion of the source region. An electrically conductive control gate is formed having a first portion disposed in the trench and a second portion formed over but insulated from the floating gate.
摘要翻译：一种在半导体衬底中形成浮置栅极存储单元的半导体存储器阵列的自对准方法，以及由此形成的阵列，由此每个存储单元包括形成在半导体衬底的表面中的沟槽，间隔开的源极和漏极区域具有沟道区域之间形成。漏极区域形成在沟槽下方，并且沟道区域包括沿着沟槽的侧壁基本垂直地延伸的第一部分和沿着衬底的表面基本水平延伸的第二部分。导电浮栅形成在沟道区的至少一部分和源极区的一部分之上并与之绝缘。导电控制栅极形成为具有设置在沟槽中的第一部分和形成在浮动栅极上但与浮动栅极绝缘的第二部分。

4. 发明授权

US07547603B2 Non-planar non-volatile memory cell with an erase gate, an array therefor, and a method of making same 有权
标题翻译：具有擦除栅极的非平面非易失性存储单元及其阵列及其制造方法
公开(公告)号：US07547603B2
公开(公告)日：2009-06-16
申请号：US11520993
申请日：2006-09-14
申请人： Bomy Chen , Sohrab Kianian , Yaw Wen Hu
发明人： Bomy Chen , Sohrab Kianian , Yaw Wen Hu
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42328 , H01L29/42336 , H01L29/7885
摘要： A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. An erase gate is disposed in the trench adjacent to and insulated from the floating gate. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the erase gate, and electrically connected to the source region.
摘要翻译：存储单元具有形成在半导体衬底的表面中的沟槽，以及在其间形成沟道区的间隔开的源极和漏极区。源极区形成在沟槽下方，并且沟道区域包括沿着沟槽的侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。导电浮置栅极设置在沟槽中，与沟道区域第一部分相邻并与其绝缘。导电控制栅极设置在沟道区第二部分之上并与沟道区第二部分绝缘。擦除栅极设置在与浮动栅极相邻并与浮栅绝缘的沟槽中。一块导电材料至少有一个下部设置在沟槽中，与沟槽相邻并与擦除栅绝缘，并与源极区电连接。

5. 发明授权

US07533063B2 Smart memory card wallet 失效
公开(公告)号：US07533063B2
公开(公告)日：2009-05-12
申请号：US09881788
申请日：2001-06-14
申请人： Sohrab Kianian
发明人： Sohrab Kianian
IPC分类号： G06F17/60
CPC分类号： G07F7/1008 , G06Q20/12 , G06Q20/341 , G06Q20/346 , G06Q20/367 , G06Q20/3674 , G06Q20/382 , G06Q20/401 , G06Q20/4014
摘要： A system includes at least one server and at least one host computer coupled to a communication network. A memory card wallet includes a content addressable memory that stores server identifiers, such as URLs, and user information associated with the resource provider, such as user identification numbers and passwords. The user inserts the memory card wallet into the host computer, and instead of entering user identifiers and passwords, the memory card wallet can provide such information to the server. When the user enters a server identifier that matches a server identifier stored in the content addressable memory, the memory card wallet provides the user information associated with the matched sever identifier.

6. 发明授权

US07411246B2 Self aligned method of forming a semiconductor memory array of floating gate memory cells with buried bit-line and raised source line, and a memory array made thereby 有权
公开(公告)号：US07411246B2
公开(公告)日：2008-08-12
申请号：US10358601
申请日：2003-02-04
申请人： Sohrab Kianian
发明人： Sohrab Kianian
IPC分类号： H01L29/788
CPC分类号： H01L29/66825 , G11C16/0425 , H01L21/28273 , H01L27/115 , H01L27/11556
摘要： A method of forming an array of floating gate memory cells, and an array formed thereby, that includes source and drain regions formed in a substrate, and a conductive block of material disposed over the source region. The floating gate is formed as a thin, L-shaped layer of conductive material having a first portion disposed over the channel region and a second portion extending vertically along the conductive block. The control gate includes a first portion disposed adjacent to and insulated from a distal end of the floating gate first portion, and a second portion disposed adjacent to the channel region. A portion of the control gate could extend into a trench formed into the substrate, wherein the drain region is formed underneath the trench, and the channel region has a first portion extending along the trench sidewall and a second portion extending along the substrate surface.

7. 发明授权

US5852577A Electrically erasable and programmable read-only memory having a small unit for program and erase 失效
标题翻译：电可擦除和可编程只读存储器，具有用于编程和擦除的小单元
公开(公告)号：US5852577A
公开(公告)日：1998-12-22
申请号：US73104
申请日：1998-05-05
申请人： Sohrab Kianian , Dana Lee
发明人： Sohrab Kianian , Dana Lee
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C13/00
CPC分类号： G11C16/0416
摘要： A full programmable and erasable non-volatile floating gate memory array uses an array of memory cells arranged in a plurality of rows and columns. Each cell is of the type with a first region, a spaced apart second region and a channel region in between. A floating gate is disposed over and is insulated from a portion of the channel region and the second region. An electrically conductive gate has a first section disposed over and insulated from the first region and is disposed and is adjacent to the floating gate and is insulated therefrom and has a second section disposed over the floating gate and is insulated therefrom. The cells are arranged in rows with the second region for connection to a common line. The control gate of each of the memory cells is for connecting to a word line associated with the row. Each column is connected to the first region of the memory cells arranged in the column. The array has a plurality of first transistors interposed in each row for connecting the second regions of the memory cells arranged in each row to the common line. Each of the plurality of first transistors has an associated first portion of the memory cells in each row. Each of the first transistor can be activated by an activating means to program the memory cells of the associated first portion.
摘要翻译：完全可编程和可擦除非易失性浮动栅极存储器阵列使用排列成多个行和列的存储单元阵列。每个单元是具有第一区域，间隔开的第二区域和其间的通道区域的类型。浮置栅极设置在沟道区域和第二区域的一部分上并与其绝缘。导电栅极具有设置在第一区域之上并与第一区域绝缘的第一部分，并且设置并且与浮动栅极相邻并且与第一区域绝缘，并且具有设置在浮动栅极上并与其隔离的第二部分。单元格排列成行，第二区域用于连接到公共线。每个存储器单元的控制栅极用于连接到与该行相关联的字线。每列连接到排列在列中的存储单元的第一区域。阵列具有插入每行中的多个第一晶体管，用于将布置在每一行中的存储单元的第二区域连接到公共线。多个第一晶体管中的每一个具有每行存储单元的相关联的第一部分。第一晶体管中的每一个可以由激活装置激活以对相关联的第一部分的存储器单元进行编程。

8. 发明授权

US07307308B2 Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation 有权
标题翻译：埋入位线非挥发性浮动栅极存储单元，其具有沟槽中的独立可控制控制栅极及其阵列，以及形成方法
公开(公告)号：US07307308B2
公开(公告)日：2007-12-11
申请号：US10797296
申请日：2004-03-09
申请人： Dana Lee , Bomy Chen , Sohrab Kianian
发明人： Dana Lee , Bomy Chen , Sohrab Kianian
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： G11C16/0458 , G11C16/0483 , G11C16/0491 , H01L27/115 , H01L27/11521 , H01L29/42336
摘要： A buried bit line read/program non-volatile memory cell and array is capable of achieving high density. The cell and array is made in a semiconductor substrate which has a plurality of spaced apart trenches, with a planar surface between the trenches. Each trench has a side wall and a bottom wall. Each memory cell has a floating gate for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having two portions. One of the source/drain regions is in the bottom wall of the trench. The floating gate is in the trench and is is over a first portion of the channel and is spaced apart from the side wall of the trench. A gate electrode controls the conduction of the channel in the second portion, which is in the planar surface of the substrate. The other source/drain region is in the substrate in the planar surface of the substrate. An independently controllable control gate is also in the trench, insulated from the floating gate and is capacitively coupled thereto. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode or from the floating gate to the source/drain region at the bottom wall of the trench. The source, drain and control gates are all substantially parallel to one another, with the gate electrode substantially perpendicular to the source/drain/control gates. The source/drain lines are buried in the substrate, creating a virtual ground array.
摘要翻译：掩埋位线读/程序非易失性存储单元和阵列能够实现高密度。电池和阵列由具有多个间隔开的沟槽的半导体衬底制成，沟槽之间具有平坦表面。每个沟槽都有一个侧壁和一个底壁。每个存储单元具有用于存储其上的电荷的浮动栅极。电池具有间隔开的源极/漏极区域，其间具有沟道，沟道具有两个部分。源/漏区中的一个位于沟槽的底壁。浮动栅极在沟槽中，并且在沟槽的第一部分之上并且与沟槽的侧壁间隔开。栅电极控制在衬底的平面中的第二部分中的沟道的导通。另一个源极/漏极区域位于衬底的平面表面中的衬底中。独立可控的控制栅极也在沟槽中，与浮动栅极绝缘并且与其电容耦合。通过热通道电子注入的电池程序，并且通过Fowler-Nordheim将电子从浮栅隧穿到栅电极或从浮栅到沟槽底壁处的源极/漏极区擦除。源极，漏极和控制栅极都基本上彼此平行，栅电极基本上垂直于源极/漏极/控制栅极。源极/漏极线被埋在衬底中，形成虚拟接地阵列。

9. 发明授权

US07190018B2 Bi-directional read/program non-volatile floating gate memory cell with independent controllable control gates, and array thereof, and method of formation 有权
标题翻译：具有独立可控制控制栅极的双向读/写非易失性浮栅存储单元及其阵列及其形成方法
公开(公告)号：US07190018B2
公开(公告)日：2007-03-13
申请号：US10409407
申请日：2003-04-07
申请人： Bomy Chen , Sohrab Kianian , Jack Frayer
发明人： Bomy Chen , Sohrab Kianian , Jack Frayer
IPC分类号： H01L29/788
CPC分类号： H01L27/11521 , G11C16/0458 , G11C16/0483 , G11C16/0491 , H01L27/115
摘要： A bi-directional read/program non-volatile memory cell and array is capable of achieving high density. Each memory cell has two spaced floating gates for storage of charges thereon. The cell has spaced apart source/drain regions with a channel therebetween, with the channel having three portions. One of the floating gate is over a first portion; another floating gate is over a second portion, and a gate electrode controls the conduction of the channel in the third portion between the first and second portions. An independently controllable control gate is insulated from each of the source/drain regions, and is also capacitively coupled to the floating gate. The cell programs by hot channel electron injection, and erases by Fowler-Nordheim tunneling of electrons from the floating gate to the gate electrode. Bi-directional read permits the cell to be programmed to store bits, with one bit in each floating gate. The independently controllable control gates permit an array of such memory cells to operate in a NAND configuration.
摘要翻译：双向读/写非易失性存储单元和阵列能够实现高密度。每个存储单元具有两个间隔开的浮动栅极，用于在其上存储电荷。电池具有间隔开的源极/漏极区域，其间具有沟道，沟道具有三个部分。浮动门之一在第一部分之上; 另一个浮栅位于第二部分之上，栅电极控制第一和第二部分之间的第三部分中的沟道的导通。独立可控的控制栅极与源极/漏极区域中的每一个绝缘，并且还电容耦合到浮动栅极。通过热通道电子注入的电池程序，并通过Fowler-Nordheim将电子从浮动栅极隧穿到栅电极而擦除。双向读取允许将单元编程为存储位，每个浮动栅极中有一位。独立可控的控制门允许这种存储器单元的阵列在NAND配置中操作。

10. 发明申请

US20050269624A1 Self-aligned method of forming a semiconductor memory array of floating gate memory cells with buried source line and floating gate 有权
标题翻译：形成具有掩埋源极线和浮动栅极的浮动栅极存储器单元的半导体存储器阵列的自对准方法
公开(公告)号：US20050269624A1
公开(公告)日：2005-12-08
申请号：US11166882
申请日：2005-06-24
申请人： Yaw Hu , Sohrab Kianian
发明人： Yaw Hu , Sohrab Kianian
IPC分类号： H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00 , G11C29/00 , H01L21/336
CPC分类号： H01L27/105 , H01L27/11553
摘要： A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the floating gate, and can be electrically connected to the source region.
摘要翻译：一种形成浮栅存储器单元阵列的方法，以及由此形成的阵列，其中每个存储单元包括形成在半导体衬底的表面中的沟槽，以及在其间形成沟道区的间隔开的源极和漏极区。源极区形成在沟槽下方，并且沟道区域包括沿着沟槽的侧壁垂直延伸的第一部分和沿衬底表面水平延伸的第二部分。导电浮置栅极设置在沟槽中，与沟道区域第一部分相邻并与其绝缘。导电控制栅极设置在沟道区第二部分之上并与沟道区第二部分绝缘。一块导电材料至少有一个下部设置在与沟槽相邻并与浮栅隔绝的沟槽中，并且可以与源极区域电连接。

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