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1. 发明授权

US06992934B1 Read bitline inhibit method and apparatus for voltage mode sensing 有权
标题翻译：读取位线抑制方法和电压模式检测装置
公开(公告)号：US06992934B1
公开(公告)日：2006-01-31
申请号：US11080595
申请日：2005-03-15
申请人： Vishal Sarin , Hieu Van Tran , Jack Frayer
发明人： Vishal Sarin , Hieu Van Tran , Jack Frayer
IPC分类号： G11C16/08
CPC分类号： G11C11/5642
摘要： A multilevel memory system uses a source line driver circuit and a read bitline inhibit driver circuit to eliminate inhibit offset currents on unselected bitlines before memory operations of selected memory cells to equalize voltages before the operation.
摘要翻译：多电平存储器系统使用源极线驱动电路和读位线禁止驱动器电路来消除在所选择的存储器单元的存储器操作之前对未选位线的禁止偏移电流，以在操作之前对电压进行均衡。

2. 发明授权

US08674749B2 Fast start charge pump for voltage regulators 有权
标题翻译：用于稳压器的快速启动电荷泵
公开(公告)号：US08674749B2
公开(公告)日：2014-03-18
申请号：US12726249
申请日：2010-03-17
申请人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung Q. Nguyen , Wingfu AAron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
发明人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung Q. Nguyen , Wingfu AAron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H02M3/07 , H02M1/36 , H02M1/44
摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
摘要翻译：数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。之后，升压电路被禁止，使电荷泵产生高电压而不加速。升压电路可以被连续地使能以升高电压。升压电路可以是无负载的。电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

3. 发明授权

US07336516B2 Unified multilevel memory systems and methods 有权
标题翻译：统一的多级内存系统和方法
公开(公告)号：US07336516B2
公开(公告)日：2008-02-26
申请号：US11229191
申请日：2005-09-15
申请人： Hieu Van Tran , Hung Q. Nguyen , Vishal Sarin , Loc B. Hoang , Isao Nojima
发明人： Hieu Van Tran , Hung Q. Nguyen , Vishal Sarin , Loc B. Hoang , Isao Nojima
IPC分类号： G11C15/00
CPC分类号： G11C16/22 , G11C11/5642 , G11C15/00 , G11C15/04 , G11C15/046 , G11C16/26 , G11C2211/5641
摘要： A Unified Memory may store multiple types of content such as data or fast code or slow code. The data or code may be stored in separate arrays or in a common array. In an array, a tag bit may indicate the type of content such as data or fast code or slow code or single level or multilevel content. Tag bit may indicate communication interface or IO driver type. Sense amplifiers may be configurable based on the type of data being read. A Flash Security Measure is used to protect a protected memory area. A Flash Security Key is used for authentication and authorization a particular memory area. A XCAM (e.g., CAM) array is included in the Unified Memory. Unified Memory Concurrency is included.
摘要翻译：统一存储器可以存储多种类型的内容，例如数据或快速代码或慢速代码。数据或代码可以存储在单独的数组或公共数组中。在阵列中，标签位可以指示诸如数据或快速代码或慢代码或单级或多级内容的内容的类型。标记位可能表示通信接口或IO驱动程序类型。感测放大器可以基于正在读取的数据的类型来配置。 Flash安全措施用于保护受保护的内存区域。 Flash安全密钥用于对特定内存区域进行身份验证和授权。统一存储器中包含XCAM（例如，CAM）阵列。包括统一内存并发。

4. 发明授权

US07161844B2 Method and apparatus for compensating for bitline leakage current 有权
标题翻译：用于补偿位线泄漏电流的方法和装置
公开(公告)号：US07161844B2
公开(公告)日：2007-01-09
申请号：US10814443
申请日：2004-03-30
申请人： Vishal Sarin , Hieu Van Tran , Dana Lee
发明人： Vishal Sarin , Hieu Van Tran , Dana Lee
IPC分类号： G11C7/10
CPC分类号： G11C16/0433 , G11C7/12 , G11C16/10
摘要： A bitline leakage current compensation circuit for compensating for leakage current in an operational memory array by measuring the leakage current in a non-operational memory array or a dummy memory array and providing a feedback signal to a current source or providing the compensation current.
摘要翻译：一种位线泄漏电流补偿电路，用于通过测量非操作存储器阵列或虚拟存储器阵列中的漏电流并向电流源提供反馈信号或提供补偿电流来补偿操作存储器阵列中的漏电流。

5. 发明授权

US08497667B2 Fast voltage regulators for charge pumps 有权
标题翻译：快速电压调节器
公开(公告)号：US08497667B2
公开(公告)日：2013-07-30
申请号：US13306950
申请日：2011-11-29
申请人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung Q. Nguyen , Wingfu Aaron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
发明人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung Q. Nguyen , Wingfu Aaron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
IPC分类号： G05F3/16
CPC分类号： H02M3/07 , G11C5/145 , H02M1/36 , H02M1/44 , Y10T307/50
摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
摘要翻译：数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。之后，升压电路被禁止，使电荷泵产生高电压而不加速。升压电路可以被连续地使能以升高电压。升压电路可以是无负载的。电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

6. 发明申请

US20110022905A1 Test Circuit and Method for Multilevel Cell Flash Memory 有权
标题翻译：多电平单元闪存的测试电路和方法
公开(公告)号：US20110022905A1
公开(公告)日：2011-01-27
申请号：US12899120
申请日：2010-10-06
申请人： Hieu Van Tran , Anh Ly , Sang Thanh Nguyen , Vishal Sarin , Hung O. Nguyen , William John Saiki , Loc B. Hoang
发明人： Hieu Van Tran , Anh Ly , Sang Thanh Nguyen , Vishal Sarin , Hung O. Nguyen , William John Saiki , Loc B. Hoang
IPC分类号： G11C29/00
CPC分类号： G11C11/5621 , G11C16/04 , G11C29/50 , G11C29/50004
摘要： A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.
摘要翻译：可以使用测试装置和方法来检测数字多电平存储器单元系统的电压，电流或信号，或者通过将输入的电压，电流或信号施加到存储器单元系统来测试操作或性能。

7. 发明授权

US07868604B2 Fast voltage regulators for charge pumps 有权
标题翻译：快速电压调节器
公开(公告)号：US07868604B2
公开(公告)日：2011-01-11
申请号：US11941964
申请日：2007-11-18
申请人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung Q. Nguyen , Wingfu Aaron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
发明人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung Q. Nguyen , Wingfu Aaron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
IPC分类号： H02M3/18
CPC分类号： H02M3/07 , G11C5/145 , H02M1/36 , H02M1/44 , Y10T307/50
摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
摘要翻译：数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。之后，升压电路被禁止，使电荷泵产生高电压而不加速。升压电路可以被连续地使能以升高电压。升压电路可以是无负载的。电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

8. 发明授权

US07831872B2 Test circuit and method for multilevel cell flash memory 有权
标题翻译：多电平单元闪存的测试电路和方法
公开(公告)号：US07831872B2
公开(公告)日：2010-11-09
申请号：US12637365
申请日：2009-12-14
申请人： Hieu Van Tran , Anh Ly , Sang Thanh Nguyen , Vishal Sarin , Hung Q. Nguyen , William John Saiki , Loc B. Hoang
发明人： Hieu Van Tran , Anh Ly , Sang Thanh Nguyen , Vishal Sarin , Hung Q. Nguyen , William John Saiki , Loc B. Hoang
IPC分类号： G11C29/00
CPC分类号： G11C11/5621 , G11C16/04 , G11C29/50 , G11C29/50004
摘要： A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system.
摘要翻译：可以使用测试装置和方法来检测数字多电平存储器单元系统的电压，电流或信号，或者通过将输入的电压，电流或信号施加到存储器单元系统来测试操作或性能。

9. 发明授权

US07728563B2 Fast voltage regulators for charge pumps 有权
标题翻译：快速电压调节器
公开(公告)号：US07728563B2
公开(公告)日：2010-06-01
申请号：US12340571
申请日：2008-12-19
申请人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung O. Nguyen , Wingfu Aaron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
发明人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung O. Nguyen , Wingfu Aaron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
IPC分类号： G05F1/613
CPC分类号： H02M3/07 , G11C5/145 , H02M1/36 , H02M1/44 , Y10T307/50
摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
摘要翻译：数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。之后，升压电路被禁止，使电荷泵产生高电压而不加速。升压电路可以被连续地使能以升高电压。升压电路可以是无负载的。电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

10. 发明申请

US20080278986A1 High-Speed and Low-Power Differential Non-Volatile Content Addressable Memory Cell and Array 有权
标题翻译：高速和低功耗差分非易失性内容可寻址存储器单元和阵列
公开(公告)号：US20080278986A1
公开(公告)日：2008-11-13
申请号：US12176281
申请日：2008-07-18
申请人： Vishal Sarin , Hieu Van Tran , Isao Nojima
发明人： Vishal Sarin , Hieu Van Tran , Isao Nojima
IPC分类号： G11C15/04
CPC分类号： G11C14/00 , G11C15/046
摘要： A differential non-volatile content addressable memory array has a differential non-volatile content addressable memory cell which uses a pair of non-volatile storage elements. Each of the non-volatile storage elements can be a split-gate floating gate transistor or a stack gate floating gate transistor having a first terminal, a second terminal, a channel therebetween and a floating gate over at least a portion of the channel to control the conduction of electrons in the channel, and a control gate. The floating gate storage transistor can be in one of two states: a first state, such as erase, in which current can flow between the first terminal and the second terminal, and a second state, such as programmed, in which substantially no current flows between the first terminal and the second terminal. A pair of differential compare data lines connects to the control gate of each of the pair of non-volatile floating gate transistors. A match line connects to the first terminal of each of the pair of non-volatile floating gate transistors to a first voltage. Finally, the second terminals of each storage element is connected to a second voltage, different from the first voltage. A current passing through the memory cell is indicative of a mis-match between the contents of the compare data lines and the contents of the storage elements.
摘要翻译：差分非易失性内容可寻址存储器阵列具有使用一对非易失性存储元件的差分非易失性内容可寻址存储器单元。每个非易失性存储元件可以是分离栅极浮栅晶体管或堆叠栅极浮栅晶体管，其具有第一端子，第二端子，其间的沟道以及通道的至少一部分上的浮置栅极以控制通道中的电子传导，以及控制栅极。浮置栅极存储晶体管可以处于以下两种状态之一：电流可以在第一端子和第二端子之间流动的第一状态，例如擦除，以及第二状态，诸如编程的，其中基本上没有电流流动在第一端子和第二端子之间。一对差分比较数据线连接到该对非易失性浮栅晶体管中的每一个的控制栅极。匹配线将一对非易失性浮栅晶体管的每一个的第一端连接到第一电压。最后，每个存储元件的第二端子被连接到与第一电压不同的第二电压。通过存储单元的电流表示比较数据线的内容与存储元件的内容之间的错误匹配。

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