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1. 发明授权

US5579274A Sense circuit for a flash eefprom cell having a negative delta threshold voltage 失效
标题翻译：具有负Δ阈值电压的闪光电池的感测电路
公开(公告)号：US5579274A
公开(公告)日：1996-11-26
申请号：US483038
申请日：1995-06-06
申请人： Michael A. Van Buskirk , Michael Briner
发明人： Michael A. Van Buskirk , Michael Briner
IPC分类号： G11C16/16 , G11C16/28 , G11C16/34 , G11C7/02
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/28 , G11C16/3404
摘要： A flash EEPROM array includes a plurality of flash EEPROM cells and the flash EEPROM array has both a low power supply voltage V.sub.CC and high speed performance. This high speed performance is achieved by utilizing overerasure, a condition that was previously viewed as making a flash EEPROM cell inoperative. Specifically, the integrated circuit of this invention includes a flash EEPROM array wherein each flash EEPROM cell is overerased, and circuit means which erases, reads, and programs the overerased flash EEPROM cells. In each operation, the circuit means isolates all of the flash EEPROM cells in the array except a selected flash EEPROM cell so that leakage currents do not affect the flash EEPROM cell selected for the operation. The ability to perform the read operation on an overerased flash EEPROM cell is the mechanism that maintains the speed performance of the flash EEPROM array with the low power supply voltage.
摘要翻译：闪存EEPROM阵列包括多个快闪EEPROM单元，并且快闪EEPROM阵列具有低电源电压VCC和高速性能。这种高速性能是通过利用过度曝光来实现的，这是先前认为使快闪EEPROM单元不工作的状况。具体来说，本发明的集成电路包括快速EEPROM阵列，其中每个快闪EEPROM单元被过渡，以及电路装置，其擦除，读取和编程过度闪存的快闪EEPROM单元。在每个操作中，电路意味着除了所选择的闪存EEPROM单元之外的阵列中的所有快闪EEPROM单元，使得漏电流不会影响为操作选择的闪存EEPROM单元。在过载的快闪EEPROM单元上执行读操作的能力是以低电源电压保持闪存EEPROM阵列的速度性能的机制。

2. 发明授权

US5477499A Memory architecture for a three volt flash EEPROM 失效
标题翻译：三伏闪存EEPROM的内存架构
公开(公告)号：US5477499A
公开(公告)日：1995-12-19
申请号：US135224
申请日：1993-10-13
申请人： Michael A. Van Buskirk , Michael Briner
发明人： Michael A. Van Buskirk , Michael Briner
IPC分类号： G11C16/16 , G11C16/28 , G11C16/34 , G11C11/34
CPC分类号： G11C16/3409 , G11C16/16 , G11C16/28 , G11C16/3404
摘要： A flash EEPROM array includes a plurality of flash EEPROM cells and the flash EEPROM array has both a low power supply voltage V.sub.CC and high speed performance. This high speed performance is achieved by utilizing overerasure, a condition that was previously viewed as making a flash EEPROM cell inoperative, Specifically, the integrated circuit of this invention includes a flash EEPROM array wherein each flash EEPROM cell is overerased, and circuit means which erases, reads, and programs the overerased flash EEPROM cells. In each operation, the circuit means isolates all of the flash EEPROM cells in the array except a selected flash EEPROM cell so that leakage currents do not affect the flash EEPROM cell selected for the operation. The ability to perform the read operation on an overerased flash EEPROM cell is the mechanism that maintains the speed performance of the flash EEPROM array with the low power supply voltage.
摘要翻译：闪存EEPROM阵列包括多个快闪EEPROM单元，并且快闪EEPROM阵列具有低电源电压VCC和高速性能。这种高速性能是通过利用过去的情况来实现的，这是先前认为使快闪EEPROM单元不工作的条件。具体来说，本发明的集成电路包括快闪EEPROM阵列，其中每个快闪EEPROM单元被过渡，并且电路装置被擦除，读取并编程过高速闪存EEPROM单元。在每个操作中，电路意味着除了所选择的闪存EEPROM单元之外的阵列中的所有快闪EEPROM单元，使得漏电流不会影响为操作选择的闪存EEPROM单元。在过载的快闪EEPROM单元上执行读操作的能力是以低电源电压保持闪存EEPROM阵列的速度性能的机制。

3. 发明申请

US20060072363A1 High speed and high precision sensing for digital multilevel non-volatile memory system 有权
公开(公告)号：US20060072363A1
公开(公告)日：2006-04-06
申请号：US11283195
申请日：2005-11-18
申请人： Hieu Tran , Jack Frayer , William Saiki , Michael Briner
发明人： Hieu Tran , Jack Frayer , William Saiki , Michael Briner
IPC分类号： G11C7/02
CPC分类号： G11C11/5642 , G11C7/06 , G11C16/28
摘要： A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low impedance output driver. The high speed load provides high speed sensing. The wide output range provides a sensing margin at high speed on the comparison node. The low impedance output driver drives a heavy noisy load of a differential comparator. A precharge circuit coupled to the input and output of the sense amplifier increases the speed of sensing. A differential comparator has an architecture that includes analog bootstrap. A reference sense amplifier has the same architecture as the differential amplifier to reduce errors in offset. The reference differential amplifier also includes a signal multiplexing for detecting the contents of redundant cells and reference cells.

4. 发明申请

US20050135153A1 MEMORY UNIT HAVING PROGRAMMABLE DEVICE ID 有权
标题翻译：具有可编程设备ID的存储单元
公开(公告)号：US20050135153A1
公开(公告)日：2005-06-23
申请号：US10744504
申请日：2003-12-22
申请人： Eugene Feng , Michael Briner
发明人： Eugene Feng , Michael Briner
IPC分类号： G11C7/00 , G11C7/20 , G11C7/24 , G11C11/34 , G11C16/20 , G11C16/22
CPC分类号： G11C16/22 , G11C7/20 , G11C7/24 , G11C16/20
摘要： An integrated circuit memory device has a memory array and a non-volatile register for storing a stored signal. A bus is connected to the device for supplying an externally supplied signal to the device. A comparator compares the stored signal and the externally supplied signal and provides access to the memory array in response to the comparison.
摘要翻译：集成电路存储器件具有用于存储存储信号的存储器阵列和非易失性寄存器。总线连接到该设备，用于向设备提供外部提供的信号。比较器比较存储的信号和外部提供的信号，并响应于比较提供对存储器阵列的访问。

5. 发明授权

US06529409B1 Integrated circuit for concurrent flash memory with uneven array architecture 有权
标题翻译：并行闪存集成电路，阵列架构不均匀
公开(公告)号：US06529409B1
公开(公告)日：2003-03-04
申请号：US09954387
申请日：2001-09-10
申请人： Tam Nguyen , Michael Briner
发明人： Tam Nguyen , Michael Briner
IPC分类号： G11C1134
CPC分类号： G11C16/08 , G11C8/12 , G11C2216/22
摘要： An integrated circuit 110 for concurrent flash memory. The circuit 110 has an uneven array architecture including a pair of arrays 112, 114 of a first size, and a pair of arrays 116, 118 of a second size. The arrays 112, 114, 116 and 118 are cooperatively linked in a manner which allows certain arrays to be read while other arrays are concurrently programmed or erased. The uneven array architecture of circuit 110 provides increased flexibility of bank size combinations for concurrent read and program/erase operation.
摘要翻译：用于并发闪存的集成电路110。电路110具有包括第一尺寸的一对阵列112,114和第二尺寸的一对阵列116,118的不均匀阵列架构。阵列112,114,116和118以允许某些阵列被读取的方式协同地链接，而其他阵列被同时编程或擦除。电路110的不均匀阵列结构为并行读取和编程/擦除操作提供了用于组大小组合的增加的灵活性。

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