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1. 发明授权

US5615382A Data transfer system for buffering and selectively manipulating the size of data blocks being transferred between a processor and a system bus of a computer system 失效
标题翻译：用于缓冲和选择性地操纵在计算机系统的处理器和系统总线之间传送的数据块的大小的数据传输系统
公开(公告)号：US5615382A
公开(公告)日：1997-03-25
申请号：US468486
申请日：1995-06-06
申请人： Vincent G. Gavin , Michael J. Seaman , Neal A. Crook , Bipin Mistry
发明人： Vincent G. Gavin , Michael J. Seaman , Neal A. Crook , Bipin Mistry
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4018
摘要： A data transfer device for coupling a processor to a system bus. The data transfer device includes data packers and unpackers for converting between data blocks of a first size and data blocks of a second size, e.g. between bytes or words and longwords. The data transfer device also includes an internal buffer memory system for storing the data being transferred. The processor and system bus are selectively coupled, each one at a time, via a direct data path, to the internal buffer memory system permitting both the processor and the system bus to independently read and write data, each at their normal data transfer rate.
摘要翻译：一种用于将处理器耦合到系统总线的数据传送装置。数据传输设备包括用于在第一大小的数据块和第二大小的数据块之间进行转换的数据打包器和解包器。字节或单词和长词之间。数据传送装置还包括用于存储被传送的数据的内部缓冲存储器系统。处理器和系统总线通过直接数据路径被选择性地耦合到内部缓冲存储器系统，允许处理器和系统总线独立地以其正常数据传输速率读取和写入数据。

2. 发明授权

US5471632A System for transferring data between a processor and a system bus including a device which packs, unpacks, or buffers data blocks being transferred 失效
标题翻译：用于在处理器和系统总线之间传送数据的系统，包括打包，解包或缓冲被传输的数据块的设备
公开(公告)号：US5471632A
公开(公告)日：1995-11-28
申请号：US819468
申请日：1992-01-10
申请人： Vincent G. Gavin , Michael J. Seaman , Neal A. Crook , Bipin Mistry
发明人： Vincent G. Gavin , Michael J. Seaman , Neal A. Crook , Bipin Mistry
IPC分类号： G06F13/40 , G06F13/38
CPC分类号： G06F13/4018
摘要： A data transfer device for coupling a processor to a system bus. The data transfer device includes data packers and unpackers for converting between data blocks of a first size and data blocks of a second size, e.g. between bytes or words and longwords. The data transfer device also includes an internal buffer memory system for storing the data being transferred. The processor and system bus are selectively coupled, each one at a time, via a direct data path, to the internal buffer memory system permitting both the processor and the system bus to independently read and write data, each at their normal data transfer rate.
摘要翻译：一种用于将处理器耦合到系统总线的数据传送装置。数据传输设备包括用于在第一大小的数据块和第二大小的数据块之间进行转换的数据打包器和解包器。字节或单词和长词之间。数据传送装置还包括用于存储被传送的数据的内部缓冲存储器系统。处理器和系统总线通过直接数据路径被选择性地耦合到内部缓冲存储器系统，允许处理器和系统总线独立地以其正常数据传输速率读取和写入数据。

3. 发明授权

US5202999A Access request prioritization and summary device 失效
标题翻译：访问请求优先级和摘要设备
公开(公告)号：US5202999A
公开(公告)日：1993-04-13
申请号：US819186
申请日：1992-01-10
申请人： John M. Lenthall , Neal A. Crook , Helen C. McGreal , Michael J. Seaman
发明人： John M. Lenthall , Neal A. Crook , Helen C. McGreal , Michael J. Seaman
IPC分类号： G06F13/37
CPC分类号： G06F13/37
摘要： An access request prioritization and summary device for determining the current highest priority among n entities. The device includes a bitmap having n bit storage locations. Each one of the n bit storage locations corresponds to one of the entities and is used to store a value which represents when the corresponding entity is available for prioritization. A plurality of combinational logic blocks are connected to the bitmap so that each one of the combinational logic blocks receives a preselected portion of the values stored in the n bit storage locations of the bitmap. Each one of the combinational logic blocks has a token signal input and a token signal output. The token signal inputs and outputs are coupled together to form a series of token signal links between the combinational logic blocks. When certain preselected highest priority determination conditions occur within one of the combinational logic blocks, the combinational logic block generates a token signal which serves as the token signal to the respective succeeding combinational logic block. Each combinational logic block is capable of receiving a token signal from the previous combinational logic block and is responsive to the input of a token signal to determine a current highest priority from the values which it received as input signals.
摘要翻译：用于确定n个实体当前最高优先级的访问请求优先级和摘要设备。该设备包括具有n位存储位置的位图。 n位存储位置中的每一个对应于一个实体，并且用于存储表示当对应实体可用于优先化的时间的值。多个组合逻辑块连接到位图，使得组合逻辑块中的每一个接收存储在位图的n位存储位置中的值的预选部分。组合逻辑块中的每一个具有令牌信号输入和令牌信号输出。令牌信号输入和输出耦合在一起以在组合逻辑块之间形成一系列令牌信号链路。当在组合逻辑块之一内发生某些预选的最高优先级确定条件时，组合逻辑块产生令牌信号，令牌信号用作相应的后续组合逻辑块的令牌信号。每个组合逻辑块能够从先前的组合逻辑块接收令牌信号，并响应于令牌信号的输入，以从作为输入信号接收的值确定当前最高优先级。

4. 发明授权

US5404474A Apparatus and method for addressing a variable sized block of memory 失效
标题翻译：用于寻址可变大小的存储器块的装置和方法
公开(公告)号：US5404474A
公开(公告)日：1995-04-04
申请号：US819393
申请日：1992-01-10
申请人： Neal A. Crook , Stewart F. Bryant , Michael J. Seaman , John M. Lenthall
发明人： Neal A. Crook , Stewart F. Bryant , Michael J. Seaman , John M. Lenthall
IPC分类号： G06F12/02 , G06F12/06
CPC分类号： G06F12/0223
摘要： A method and apparatus for aliasing an address for a location in a memory system. The aliasing permits an address generating unit to access a memory block of variable size based upon an address space of fixed size so that the size of the memory block can be changed without changing the address generating software of the address generating unit. The invention provides an address aliasing device arranged to receive an address from the address generating unit. The address aliasing device includes a register that stores memory block size information. The memory block size information is read by the address aliasing device and decoded to provide bit information representative of the size of the memory block. The address aliasing device logically combines the bit information with appropriate corresponding bits of the input address to provide an alias address that is consistent with the size of the memory block.
摘要翻译：一种用于对存储器系统中的位置进行混叠的地址的方法和装置。混叠允许地址生成单元基于固定大小的地址空间访问可变大小的存储块，使得可以改变存储块的大小而不改变地址生成单元的地址生成软件。本发明提供了一种地址混叠装置，其被布置成从地址生成单元接收地址。地址混叠装置包括存储存储器块大小信息的寄存器。存储器块大小信息由地址混叠器件读取并被解码以提供表示存储块大小的位信息。地址混叠设备逻辑地将位信息与输入地址的适当对应位组合，以提供与存储块大小一致的别名地址。

5. 发明授权

US5386523A Addressing scheme for accessing a portion of a large memory space 失效
标题翻译：用于访问大内存空间的一部分的寻址方案
公开(公告)号：US5386523A
公开(公告)日：1995-01-31
申请号：US818607
申请日：1992-01-10
申请人： Neal A. Crook , Michael J. Seaman , David L. A. Brash
发明人： Neal A. Crook , Michael J. Seaman , David L. A. Brash
IPC分类号： G06F9/30 , G06F9/308 , G06F9/355 , G06F12/02 , G06F12/00 , G06F12/06
CPC分类号： G06F9/30018 , G06F12/0215 , G06F9/30112 , G06F9/342
摘要： A method for generating an address for addressable locations of a computer system where two registers are overlapped. Those bits of the two registers that overlap are logically combined together using a boolean operation when generating the address. Using this method, the higher order register can be used to select a segment of the addressable space of the computer system. Then, all accesses to that portion of the addressable space can be controlled by changing only the lower order register. This results in a saving of time since only one of the registers need be reloaded for each subsequent access.
摘要翻译：一种用于产生其中两个寄存器重叠的计算机系统的可寻址位置的地址的方法。重叠的两个寄存器的那些位在生成地址时使用布尔运算来逻辑地组合在一起。使用这种方法，可以使用高阶寄存器来选择计算机系统的可寻址空间的一段。然后，可以通过仅更改低阶寄存器来控制对可寻址空间的该部分的所有访问。这导致节省时间，因为每次后续访问只需要重新加载一个寄存器。

6. 发明授权

US5592622A Network intermediate system with message passing architecture 失效
标题翻译：具有消息传递架构的网络中间系统
公开(公告)号：US5592622A
公开(公告)日：1997-01-07
申请号：US438897
申请日：1995-05-10
申请人： Mark S. Isfeld , Bruce W. Mitchell , Michael J. Seaman , Tracy D. Mallory , Nagaraj Arunkumar
发明人： Mark S. Isfeld , Bruce W. Mitchell , Michael J. Seaman , Tracy D. Mallory , Nagaraj Arunkumar
IPC分类号： G06F13/38 , H04L12/46 , H04L12/56 , G06F13/00 , G06F15/163
CPC分类号： H04L12/5601 , G06F13/387 , H04L12/4604 , H04L45/00 , H04L49/107 , H04L49/256 , H04L49/309 , H04L49/90 , H04L49/901 , H04L49/9047 , H04L49/9084 , H04L2012/5651 , H04L2012/5665
摘要： A system uses a message passing paradigm for transferring large amounts of input/output data among a plurality of processors, such as a network intermediate system or router. A bus interconnects the plurality of processors with a plurality of bus interface devices. The bus interface device which originates a transfer includes a command list storing lists of commands which characterize transfers of data messages from local memory across the bus and a packing buffer which buffers the data subject of the command being executed between local memory and the bus. A bus interface device which receives a transfer includes a free buffer list storing pointers to free buffers in local memory into which the data may be loaded from the bus, and a receive list storing pointers to buffers in local memory loaded with data from the bus. The command list includes a first high priority command list and a second lower priority command list for managing latency of the higher priority commands in the software of the processor. The bus interface which receives the transfer includes control logic which manages data transfer into and out of an inbound buffer, including receiving burst transfers of message transfer cells from the bus, loading free buffers in local memory from the inbound buffer with message transtar cells, and updating the receive list. The receive list includes a first higher priority receive list and a second lower priority receive list for reliability management, and logic which monitors the free list so that lower priority messages may be dropped to prevent overflow of free buffer resources.
摘要翻译：系统使用消息传递范例来在诸如网络中间系统或路由器的多个处理器之间传送大量输入/输出数据。总线将多个处理器与多个总线接口设备互连。始发传输的总线接口设备包括命令列表，其存储表示通过总线的本地存储器传输数据消息的命令的列表，以及缓冲在本地存储器和总线之间执行的命令的数据对象的打包缓冲器。接收传送的总线接口装置包括存储指向本地存储器中的空闲缓冲器的空闲缓冲器列表，可从该总线加载数据，以及存储指向本地存储器中缓冲器的指针的接收列表，该缓冲器装载有来自总线的数据。命令列表包括用于管理处理器的软件中较高优先级命令的等待时间的第一高优先级命令列表和第二较低优先级命令列表。接收传输的总线接口包括管理进入和离开入站缓冲器的数据传输的控制逻辑，包括从总线接收消息传送单元的突发传送，从具有消息传送信元的入站缓冲器加载本地存储器中的空闲缓冲器，以及更新接收列表。接收列表包括用于可靠性管理的第一较高优先级接收列表和第二较低优先级接收列表，以及监视空闲列表的逻辑，以便可以丢弃较低优先级的消息以防止空闲缓冲器资源的溢出。

7. 发明授权

US5590285A Network station with multiple network addresses 失效
标题翻译：具有多个网络地址的网络站
公开(公告)号：US5590285A
公开(公告)日：1996-12-31
申请号：US513167
申请日：1995-08-09
申请人： Jeffrey Krause , Niles E. Strohl , Michael J. Seaman , Steven P. Russell , John H. Hart
发明人： Jeffrey Krause , Niles E. Strohl , Michael J. Seaman , Steven P. Russell , John H. Hart
IPC分类号： G06F13/374 , G06F13/00 , G06F13/376 , H04L12/46 , H04L29/06
CPC分类号： H04L12/4625 , H04L29/06 , H04L45/742 , H04L69/18
摘要： DLL devices are built with multiple MAC address instead of a single MAC address, and provide a multiple virtual DLL interfaces to the upper layers (3-7) in a computer. This results in a new class of multi-function computers for attachment to a network system which take advantage of the multiple virtual DLL interfaces, to increase performance of the respective functions executed by the computer. Thus, a new network interface control apparatus and a new class of multi-function computer systems for attachments to networks are provided. The memory in the medium access control device stores a plurality of additional network addresses in addition to the assigned network addresses. The address filtering logic includes circuits responsive to the additional network addresses, such as logic for blocking a particular frame on at least one of the plurality of data channels when the source and destination address of a particular frame are found in the additional addresses stored in the memory. The plurality of data channels served by the media access control device may reside on a single physical interface, or in independent physical interfaces as suits the needs of a particular design. A high performance design would include independent buffering and queuing structures for each of the data channels. An alternative design may include shared buffering and queuing structures for a plurality of functional modules in the connected computer which have independent side network addresses.
摘要翻译： DLL设备构建有多个MAC地址而不是单个MAC地址，并且在计算机中向上层（3-7）提供多个虚拟DLL接口。这导致了一类新的多功能计算机，用于连接到利用多个虚拟DLL接口的网络系统，以提高计算机执行的相应功能的性能。因此，提供了一种新的网络接口控制装置和用于附接到网络的新类型的多功能计算机系统。介质访问控制装置中的存储器除了分配的网络地址之外还存储多个附加网络地址。地址过滤逻辑包括响应于附加网络地址的电路，例如当在存储在所述多个数据信道中的附加地址中找到特定帧的源和目的地址时，用于阻塞所述多个数据信道中的至少一个上的特定帧的逻辑记忆。由媒体访问控制设备服务的多个数据信道可以驻留在单个物理接口上，或者在独立的物理接口中，以适应特定设计的需要。高性能设计将包括每个数据通道的独立缓冲和排队结构。替代设计可以包括用于连接的计算机中具有独立侧网络地址的多个功能模块的共享缓冲和排队结构。

8. 发明授权

US5428766A Error detection scheme in a multiprocessor environment 失效
标题翻译：多处理器环境中的错误检测方案
公开(公告)号：US5428766A
公开(公告)日：1995-06-27
申请号：US983907
申请日：1992-12-01
申请人： Michael J. Seaman
发明人： Michael J. Seaman
IPC分类号： G06F11/00 , G06F11/34
CPC分类号： G06F11/0751 , G06F11/0724 , G06F11/349
摘要： An error detection scheme to detect a variety of errors, including buffer accesses errors, buffer ownership transfer errors, and address recognition engine access errors, that may occur during the passing of messages between processors in a multi-processor computer system implementing a buffer swapping scheme. The error detection scheme of the present invention provides for the monitoring of bus transactions, maintaining a log of bus activity including buffer access transactions, identifying transactions involving buffer and address recognition operations and checking those operations to insure that they are consistent with the implemented buffer swapping scheme. Upon detection of an error the bus monitoring device asserts an error signal, freezes the log of bus activity and halts buffer swapping activity until the detected error is investigated and dealt with in an appropriate manner.
摘要翻译：用于检测在执行缓冲器交换方案的多处理器计算机系统中的处理器之间的消息传递期间可能发生的各种错误的错误检测方案，包括缓冲器访问错误，缓冲器所有权转移错误和地址识别引擎访问错误。本发明的错误检测方案提供了对总线事务的监视，维护包括缓冲器访问事务的总线活动记录，识别涉及缓冲器和地址识别操作的事务，并检查这些操作以确保它们与实现的缓冲器交换一致方案。在检测到错误时，总线监控设备断言错误信号，冻结总线活动的日志并停止缓冲区交换活动，直到检测到的错误被调查并以适当的方式处理。

9. 发明授权

US06934263B1 Spanning tree with protocol for bypassing port state transition timers 有权
标题翻译：生成树，用于绕过端口状态转换定时器
公开(公告)号：US06934263B1
公开(公告)日：2005-08-23
申请号：US10769177
申请日：2004-01-30
申请人： Michael J. Seaman
发明人： Michael J. Seaman
IPC分类号： H04L12/46 , H04L12/28
CPC分类号： H04L12/4625
摘要： Mechanisms for use on designated ports in spanning tree protocol entities allow such ports to transition to a forwarding state on the basis of actual communication delays between neighboring bridges, rather than upon expiration of forwarding delay timers. The logic that manages transition of states in the spanning tree protocol entity identifies ports which are changing to a designated port role, and issues a message on such ports informing the downstream port that the issuing port is able to assume a forwarding state. The logic begins the standard delay timer for entry to the listening state and then the learning state, prior to assuming the forwarding state. However, when a reply from the downstream port is received, then the issuing port reacts by changing immediately to the forwarding state without continuing to await expiration of the delay timer and without traversing transitional listening and learning states. A downstream port which receives a message from an upstream port indicating that it is able to assume a forwarding state, reacts by ensuring that no loop will be formed by the change in state of the upstream port. In one embodiment, the downstream port changes the state of designated ports on the protocol entity which were recently root ports to a blocking state, and then issues messages downstream indicating that such designated ports are ready to resume the forwarding state. The designated ports on the downstream protocol entity await a reply from ports further downstream. In this way, loops are blocked step-by-step through the network, as the topology of the tree settles.
摘要翻译：在生成树协议实体中的指定端口上使用的机制允许这样的端口基于相邻网桥之间的实际通信延迟而不是在转发延迟定时器到期时转换到转发状态。管理生成树协议实体中状态转换的逻辑标识正在改变为指定端口角色的端口，并在这些端口上发出消息，通知下游端口发布端口能够承担转发状态。逻辑开始标准延迟定时器进入侦听状态，然后开始学习状态，然后再采取转发状态。然而，当接收到来自下游端口的应答时，发送端口通过立即改变到转发状态而不继续等待延迟定时器的期满而不经过过渡的监听和学习状态来做出反应。从上游端口接收到表示能够承担转发状态的消息的下行端口通过确保上游端口的状态变化不会形成环路而做出反应。在一个实施例中，下游端口将最近根端口的协议实体上的指定端口的状态改变为阻塞状态，然后向下游发送指示这些指定端口准备好恢复转发状态的消息。下游协议实体上的指定端口等待来自下游端口的回复。以这种方式，循环通过网络逐步阻止，因为树的拓扑结构。

10. 发明授权

US5790808A Active topology maintenance in reconfiguring bridged local area networks with state transition with forgetting interval 失效
标题翻译：在遗留间隔状态转换的情况下重新配置桥接局域网的主动拓扑维护
公开(公告)号：US5790808A
公开(公告)日：1998-08-04
申请号：US498944
申请日：1995-07-06
申请人： Michael J. Seaman
发明人： Michael J. Seaman
IPC分类号： H04L12/46 , H04L12/56 , G06F13/14
CPC分类号： H04L12/462 , H04L45/48
摘要： Resources for computing an active network topology in a system having a plurality of ports coupled to respective local area networks include a protocol entity coupled to the plurality of ports which communicates with protocol entities in other systems on the networks to establish the active network topology. Port state logic, coupled with the protocol entity and the plurality of ports establishes active network states for the plurality of ports. The active network states include a first network state for forwarding data and a second network state for blocking data, wherein a transition from a first network state to a second network state is executed after receiving information from the protocol entity indicating a change to the second network state. A transition from the second network state back to the first network state is executed upon expiry of a waiting interval after receiving information from the protocol entity indicating a change to the first network state, unless information indicating a change to the first network state is received within a forgetting interval after a change from the first network state to the second network state. If the information indicating such change is received prior to expiry of the forgetting interval, then the transition is executed immediately.
摘要翻译：用于在具有耦合到相应局域网的多个端口的系统中计算活动网络拓扑的资源包括耦合到多个端口的协议实体，其与网络上的其他系统中的协议实体通信以建立活动网络拓扑。端口状态逻辑与协议实体和多个端口相结合，为多个端口建立活动的网络状态。活动网络状态包括用于转发数据的第一网络状态和用于阻止数据的第二网络状态，其中在从协议实体接收到指示对第二网络的改变的信息之后，执行从第一网络状态到第二网络状态的转变州。除非在第一网络状态的改变之前收到指示对第一网络状态的改变的信息，否则在接收到来自协议实体的指示对第一网络状态的改变的信息之后，等待间隔期满后，执行从第二网络状态到第一网络状态的转换在从第一网络状态改变到第二网络状态之后的遗忘间隔。如果在遗忘间隔到期之前接收到指示这种改变的信息，则立即执行转换。

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