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1. 发明授权

US5590285A Network station with multiple network addresses 失效
标题翻译：具有多个网络地址的网络站
公开(公告)号：US5590285A
公开(公告)日：1996-12-31
申请号：US513167
申请日：1995-08-09
申请人： Jeffrey Krause , Niles E. Strohl , Michael J. Seaman , Steven P. Russell , John H. Hart
发明人： Jeffrey Krause , Niles E. Strohl , Michael J. Seaman , Steven P. Russell , John H. Hart
IPC分类号： G06F13/374 , G06F13/00 , G06F13/376 , H04L12/46 , H04L29/06
CPC分类号： H04L12/4625 , H04L29/06 , H04L45/742 , H04L69/18
摘要： DLL devices are built with multiple MAC address instead of a single MAC address, and provide a multiple virtual DLL interfaces to the upper layers (3-7) in a computer. This results in a new class of multi-function computers for attachment to a network system which take advantage of the multiple virtual DLL interfaces, to increase performance of the respective functions executed by the computer. Thus, a new network interface control apparatus and a new class of multi-function computer systems for attachments to networks are provided. The memory in the medium access control device stores a plurality of additional network addresses in addition to the assigned network addresses. The address filtering logic includes circuits responsive to the additional network addresses, such as logic for blocking a particular frame on at least one of the plurality of data channels when the source and destination address of a particular frame are found in the additional addresses stored in the memory. The plurality of data channels served by the media access control device may reside on a single physical interface, or in independent physical interfaces as suits the needs of a particular design. A high performance design would include independent buffering and queuing structures for each of the data channels. An alternative design may include shared buffering and queuing structures for a plurality of functional modules in the connected computer which have independent side network addresses.
摘要翻译： DLL设备构建有多个MAC地址而不是单个MAC地址，并且在计算机中向上层（3-7）提供多个虚拟DLL接口。这导致了一类新的多功能计算机，用于连接到利用多个虚拟DLL接口的网络系统，以提高计算机执行的相应功能的性能。因此，提供了一种新的网络接口控制装置和用于附接到网络的新类型的多功能计算机系统。介质访问控制装置中的存储器除了分配的网络地址之外还存储多个附加网络地址。地址过滤逻辑包括响应于附加网络地址的电路，例如当在存储在所述多个数据信道中的附加地址中找到特定帧的源和目的地址时，用于阻塞所述多个数据信道中的至少一个上的特定帧的逻辑记忆。由媒体访问控制设备服务的多个数据信道可以驻留在单个物理接口上，或者在独立的物理接口中，以适应特定设计的需要。高性能设计将包括每个数据通道的独立缓冲和排队结构。替代设计可以包括用于连接的计算机中具有独立侧网络地址的多个功能模块的共享缓冲和排队结构。

2. 发明授权

US5535338A Multifunction network station with network addresses for functional units 失效
标题翻译：具有功能单元网络地址的多功能网络站
公开(公告)号：US5535338A
公开(公告)日：1996-07-09
申请号：US452498
申请日：1995-05-30
申请人： Jeffrey Krause , Niles E. Strohl , Michael J. Seaman , Steven P. Russell , John H. Hart
发明人： Jeffrey Krause , Niles E. Strohl , Michael J. Seaman , Steven P. Russell , John H. Hart
IPC分类号： G06F13/374 , G06F13/00 , G06F13/376 , H04L12/46 , H04L29/06
CPC分类号： H04L12/4625 , H04L29/06 , H04L45/742 , H04L69/18
摘要： DLL devices are built with multiple MAC address instead of a single MAC address, and provide a multiple virtual DLL interfaces to the upper layers (3-7) in a computer. This results in a new class of multi-function computers for attachment to a network system which take advantage of the multiple virtual DLL interfaces, to increase performance of the respective functions executed by the computer. Thus, a new network interface control apparatus and a new class of multi-function computer systems for attachments to networks are provided. The memory in the medium access control device stores a plurality of additional network addresses in addition to the assigned network addresses. The address filtering logic includes circuits responsive to the additional network addresses, such as logic for blocking a particular frame on at least one of the plurality of data channels when the source and destination address of a particular frame are found in the additional addresses stored in the memory. The plurality of data channels served by the media access control device may reside on a single physical interface, or in independent physical interfaces as suits the needs of a particular design. A high performance design would include independent buffering and queuing structures for each of the data channels. An alternative design may include shared buffering and queuing structures for a plurality of functional modules in the connected computer which have independent side network addresses.
摘要翻译： DLL设备构建有多个MAC地址而不是单个MAC地址，并且在计算机中向上层（3-7）提供多个虚拟DLL接口。这导致了一类新的多功能计算机，用于连接到利用多个虚拟DLL接口的网络系统，以提高计算机执行的相应功能的性能。因此，提供了一种新的网络接口控制装置和用于附接到网络的新类型的多功能计算机系统。介质访问控制装置中的存储器除了分配的网络地址之外还存储多个附加网络地址。地址过滤逻辑包括响应于附加网络地址的电路，例如当在存储在所述多个数据信道中的附加地址中找到特定帧的源和目的地址时，用于阻塞所述多个数据信道中的至少一个上的特定帧的逻辑记忆。由媒体访问控制设备服务的多个数据信道可以驻留在单个物理接口上，或者在独立的物理接口中，以适应特定设计的需要。高性能设计将包括每个数据通道的独立缓冲和排队结构。替代设计可以包括用于连接的计算机中具有独立侧网络地址的多个功能模块的共享缓冲和排队结构。

3. 发明授权

US07899937B1 Programmed I/O ethernet adapter with early interrupts for accelerating data transfer 失效
标题翻译：带有早期中断的编程I / O以太网适配器，用于加速数据传输
公开(公告)号：US07899937B1
公开(公告)日：2011-03-01
申请号：US09488942
申请日：2000-01-21
申请人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
发明人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
IPC分类号： G06F15/16 , G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00
CPC分类号： H04L49/9078 , G06F13/385 , H04L12/40032 , H04L49/90 , H04L49/9068
摘要： In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.
摘要翻译：在局域网（LAN）系统中，以太网适配器通过编程I / O（PIO）和FIFO缓冲器与主机交换数据。接收PIO采用DMA环形缓冲区备份，因此当PIO FIFO缓冲区已满时，传入的数据包可以直接复制到主机存储器中。当只有一部分分组已经从网络接收到时，适配器可以被编程为产生早期接收中断，以便减少等待时间。适配器也可以被编程为产生第二早期中断，使得将大数据包复制到主机可能重叠接收分组端。在数据包完全从主机传输到适配器之前，适配器开始分组传输，这进一步减少了延迟。适配器的最小延迟允许其使用足够小的接收和发送FIFO缓冲器，以将其包含在包含收发器，以太网控制器，FIFO控制电路和主机接口的专用集成电路（ASIC）内部的RAM内部。

4. 发明授权

US08239580B2 Programmed I/O ethernet adapter with early interrupts for accelerating data transfer 失效
标题翻译：带有早期中断的编程I / O以太网适配器，用于加速数据传输
公开(公告)号：US08239580B2
公开(公告)日：2012-08-07
申请号：US12939604
申请日：2010-11-04
申请人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
发明人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
IPC分类号： G06F15/16 , G06F3/00 , G06F9/44 , G06F9/46 , G06F13/00
CPC分类号： H04L49/9068 , G06F13/385 , H04L12/40013 , H04L12/40032 , H04L12/413 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9078
摘要： In a Local Area Network (LAN) system, an Ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.
摘要翻译：在局域网（LAN）系统中，以太网适配器通过编程的I / O（PIO）和FIFO缓冲器与主机交换数据。接收PIO采用DMA环形缓冲区备份，因此当PIO FIFO缓冲区已满时，传入的数据包可以直接复制到主机存储器中。当只有一部分分组已经从网络接收到时，适配器可以被编程为产生早期接收中断，以便减少等待时间。适配器也可以被编程为产生第二早期中断，使得将大数据包复制到主机可能重叠接收分组端。在数据包完全从主机传输到适配器之前，适配器开始分组传输，这进一步减少了延迟。适配器的最小延迟允许其使用足够小的接收和发送FIFO缓冲器，以将其包含在包含收发器，以太网控制器，FIFO控制电路和主机接口的专用集成电路（ASIC）内部的RAM内部。

5. 发明授权

US5459840A Input/output bus architecture with parallel arbitration 失效
标题翻译：具有并行仲裁的输入/输出总线结构
公开(公告)号：US5459840A
公开(公告)日：1995-10-17
申请号：US23008
申请日：1993-02-26
申请人： Mark S. Isfeld , Michael H. Bowman , Niles E. Strohl
发明人： Mark S. Isfeld , Michael H. Bowman , Niles E. Strohl
IPC分类号： G06F13/374 , G06F13/14
CPC分类号： G06F13/374
摘要： A high performance bus suitable for high speed internetworking applications which is based on three bus phase types, including an arbitration phase, an address phase, and a data phase. The arbitration, address, and data phases share a single set of lines. Distributed arbitration logic on each of the interface devices supplies local arbitration codes to a particular line in the set of lines in the arbitration cycle, and detects an arbitration win during the same phase in response to the local arbitration code, and other arbitration codes driven on the set of lines during the arbitration cycle. Each module coupled to the bus also assigned a local priority code. During the arbitration cycle, both the arbitration code and the priority code are driven on respective subsets of the shared sets of lines. Assertion of the local priority code overrides normal requests for the bus. The arbitration logic on each module includes a bus request logic which has the effect of defining arbitration cycles, such that in a particular arbitration phase, a group of modules that asserts a bus request signal controls the bus request signal until all modules in the group have won arbitration.
摘要翻译：适用于基于三总线相位类型的高速互联网应用的高性能总线，包括仲裁阶段，地址阶段和数据阶段。仲裁，地址和数据阶段共享一组单行。每个接口设备上的分布式仲裁逻辑将本地仲裁代码提供给仲裁周期中的一组线路中的特定线路，并且响应于本地仲裁代码在相同阶段期间检测到仲裁胜诉，并且其他仲裁代码被驱动仲裁周期内的一组线路。耦合到总线的每个模块也分配了本地优先级代码。在仲裁周期期间，仲裁代码和优先级代码都是在共享线路组的各个子集上驱动的。断言本地优先级代码将覆盖总线的正常请求。每个模块上的仲裁逻辑包括总线请求逻辑，其具有定义仲裁周期的效果，使得在特定仲裁阶段中，断言总线请求信号的一组模块控制总线请求信号，直到该组中的所有模块具有赢得仲裁

6. 发明授权

US5485584A Apparatus for simulating a stack structure using a single register and a counter to provide transmit status in a programmed I/O ethernet adapter with early interrupts 失效
标题翻译：用于使用单个寄存器和计数器模拟堆栈结构的装置，以在具有早期中断的编程I / O以太网适配器中提供发送状态
公开(公告)号：US5485584A
公开(公告)日：1996-01-16
申请号：US374491
申请日：1995-01-17
申请人： Richard Hausman , Paul W. Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
发明人： Richard Hausman , Paul W. Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
IPC分类号： G06F13/00 , G06F13/38 , H04L12/413 , H04L12/56 , H04L29/10 , G06F13/32
CPC分类号： H04L49/9068 , G06F13/385 , H04L12/40013 , H04L12/413 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9078 , H04L12/40032
摘要： In a Local Area Network (LAN) system, an ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.
摘要翻译：在局域网（LAN）系统中，以太网适配器通过编程I / O（PIO）和FIFO缓冲器与主机交换数据。接收PIO采用DMA环形缓冲区备份，因此当PIO FIFO缓冲区已满时，传入的数据包可以直接复制到主机存储器中。当只有一部分分组已经从网络接收到时，适配器可以被编程为产生早期接收中断，以便减少等待时间。适配器也可以被编程为产生第二早期中断，使得将大数据包复制到主机可能重叠接收分组端。在数据包完全从主机传输到适配器之前，适配器开始分组传输，这进一步减少了延迟。适配器的最小延迟允许其使用足够小的接收和发送FIFO缓冲器，以将其包含在包含收发器，以太网控制器，FIFO控制电路和主机接口的专用集成电路（ASIC）内部的RAM内部。

7. 发明授权

US4152671A Oscillator-modulator apparatus and method therefor 失效
标题翻译：振荡器调制装置及其方法
公开(公告)号：US4152671A
公开(公告)日：1979-05-01
申请号：US818838
申请日：1977-07-25
申请人： Wade B. Tuma , Niles E. Strohl
发明人： Wade B. Tuma , Niles E. Strohl
IPC分类号： H03C1/54 , H03B1/00 , H03B5/04 , H03B5/12 , H03L1/00 , H05K7/14 , H05K9/00 , H02B1/02
CPC分类号： H05K9/006 , H05K7/14 , Y10S174/34
摘要： A radio frequency oscillator-modulator for use in a video game includes a folded metal shield box having a slot on one of its ends in which a similarly slotted printed circuit board containing the oscillator and modulator is mated with. Circuitry of the oscillator and modulator provides for great linearity and low R.F. radiation. The slot arrangement provides for effective grounding of the ground metallization of the external portion of the printed circuit board which contains the radio frequency output terminal along with the various input terminals. This portion contains ground metallization which makes very effective electrical contact with the slot of the shield box thus again containing R.F. radiation.
摘要翻译：用于视频游戏的射频振荡器调制器包括折叠的金属屏蔽盒，在其端部之一上具有槽，其中包含振荡器和调制器的相似的带槽印刷电路板与之配合。振荡器和调制器的电路提供极大的线性度和较低的R.F. 辐射。插槽布置提供了包含射频输出端子的印刷电路板的外部部分的接地金属化与各种输入端子的有效接地。该部分包含地面金属化，其使得与屏蔽盒的槽非常有效地电接触，从而再次包含R.F. 辐射。

8. 发明授权

US4337444A Radio frequency oscillator-modulator circuit 失效
标题翻译：射频振荡器调制电路
公开(公告)号：US4337444A
公开(公告)日：1982-06-29
申请号：US114816
申请日：1980-01-24
申请人： Wade B. Tuma , Niles E. Strohl
发明人： Wade B. Tuma , Niles E. Strohl
IPC分类号： H05K9/00 , H03B5/12 , H03C1/44
CPC分类号： H05K9/006
摘要： A radio frequency oscillator-modulator for use in a video game includes an oscillator circuit, formed from a first differentially connected, emitter-coupled transistor pair having base/collector cross-coupling, that is dc coupled to the differential inputs of a second differentially connected, emitter-coupled transistor pair that forms the modulator circuit. The modulation signal is applied through a resistance to the connected emitters of the modulator circuit to vary the drive current thereof. The radio frequency oscillator-modulator includes bias circuitry that establishes a low level of operation that provides for great linearity and low R.F. radiation.
摘要翻译：用于视频游戏的射频振荡器调制器包括由具有基极/集电极交叉耦合的第一差分连接的发射极耦合晶体管对形成的振荡器电路，其直流耦合到第二差分连接的差分输入，形成调制器电路的发射极耦合晶体管对。通过对调制器电路的连接的发射极的电阻施加调制信号以改变其驱动电流。射频振荡器调制器包括偏置电路，其建立低电平的操作，提供极大的线性度和低的R.F。辐射。

9. 发明授权

US4214360A Method of making a radio frequency oscillator-modulator with ground metallization 失效
标题翻译：制造具有地面金属化的射频振荡器调制器的方法
公开(公告)号：US4214360A
公开(公告)日：1980-07-29
申请号：US949848
申请日：1978-10-10
申请人： Wade B. Tuma , Niles E. Strohl
发明人： Wade B. Tuma , Niles E. Strohl
IPC分类号： H05K9/00 , H01R43/00
CPC分类号： H05K9/006 , Y10T29/49124
摘要： A radio frequency oscillator-modulator for use in a video game includes a folded metal shield box having a slot on one of its ends with which a similarly slotted printed circuit board containing the oscillator and modulator is mated. Circuitry of the oscillator and modulator provides for great linearity and low R.F. radiation. The slot arrangement provides for effective grounding of the ground metallization of the external portion of the printed circuit board which contains the radio frequency output terminal along with the various input terminals. This portion contains ground metallization which makes very effective electrical contact with the slot of the shield box thus again containing R.F. radiation.
摘要翻译：用于视频游戏的射频振荡器调制器包括折叠的金属屏蔽盒，其在其一端具有狭缝，与其配合包含振荡器和调制器的类似狭缝的印刷电路板。振荡器和调制器的电路提供极大的线性度和较低的R.F. 辐射。插槽布置提供了包含射频输出端子的印刷电路板的外部部分的接地金属化与各种输入端子的有效接地。该部分包含地面金属化，其使得与屏蔽盒的槽非常有效地电接触，从而再次包含R.F. 辐射。

10. 发明申请

US20110047302A1 PROGRAMMED I/O ETHERNET ADAPTER WITH EARLY INTERRUPTS FOR ACCELERATING DATA TRANSFER 失效
标题翻译：具有加速数据传输的早期中断的编程I / O以太网适配器
公开(公告)号：US20110047302A1
公开(公告)日：2011-02-24
申请号：US12939604
申请日：2010-11-04
申请人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
发明人： Richard Hausman , Paul William Sherer , James P. Rivers , Cynthia Zikmund , Glenn W. Connery , Niles E. Strohl , Richard S. Reid
IPC分类号： G06F13/28 , G06F5/00 , G06F13/24
CPC分类号： H04L49/9068 , G06F13/385 , H04L12/40013 , H04L12/40032 , H04L12/413 , H04L49/90 , H04L49/901 , H04L49/9031 , H04L49/9078
摘要： In a Local Area Network (LAN) system, an Ethernet adapter exchanges data with a host through programmed I/O (PIO) and FIFO buffers. The receive PIO employs a DMA ring buffer backup so incoming packets can be copied directly into host memory when the PIO FIFO buffer is full. The adapter may be programmed to generate early receive interrupts when only a portion of a packet has been received from the network, so as to decrease latency. The adapter may also be programmed to generate a second early interrupt so that the copying of a large packet to the host may overlap reception of the packet end. The adapter to begin packet transmission before the packet is completely transferred from the host to the adapter, which further reduces latency. The minimal latency of the adapter allows it to employ receive and transmit FIFO buffers which are small enough to be contained within RAM internal to an Application Specific Integrated Circuit (ASIC) containing the transceiver, ethernet controller, FIFO control circuitry and the host interface as well.
摘要翻译：在局域网（LAN）系统中，以太网适配器通过编程的I / O（PIO）和FIFO缓冲器与主机交换数据。接收PIO采用DMA环形缓冲区备份，因此当PIO FIFO缓冲区已满时，传入的数据包可以直接复制到主机存储器中。当只有一部分分组已经从网络接收到时，适配器可以被编程为产生早期接收中断，以便减少等待时间。适配器也可以被编程为产生第二早期中断，使得将大数据包复制到主机可能重叠接收分组端。在数据包完全从主机传输到适配器之前，适配器开始分组传输，这进一步减少了延迟。适配器的最小延迟允许其使用足够小的接收和发送FIFO缓冲器，以将其包含在包含收发器，以太网控制器，FIFO控制电路和主机接口的专用集成电路（ASIC）内部的RAM内部。

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