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1. 发明授权

US5404474A Apparatus and method for addressing a variable sized block of memory 失效
标题翻译：用于寻址可变大小的存储器块的装置和方法
公开(公告)号：US5404474A
公开(公告)日：1995-04-04
申请号：US819393
申请日：1992-01-10
申请人： Neal A. Crook , Stewart F. Bryant , Michael J. Seaman , John M. Lenthall
发明人： Neal A. Crook , Stewart F. Bryant , Michael J. Seaman , John M. Lenthall
IPC分类号： G06F12/02 , G06F12/06
CPC分类号： G06F12/0223
摘要： A method and apparatus for aliasing an address for a location in a memory system. The aliasing permits an address generating unit to access a memory block of variable size based upon an address space of fixed size so that the size of the memory block can be changed without changing the address generating software of the address generating unit. The invention provides an address aliasing device arranged to receive an address from the address generating unit. The address aliasing device includes a register that stores memory block size information. The memory block size information is read by the address aliasing device and decoded to provide bit information representative of the size of the memory block. The address aliasing device logically combines the bit information with appropriate corresponding bits of the input address to provide an alias address that is consistent with the size of the memory block.
摘要翻译：一种用于对存储器系统中的位置进行混叠的地址的方法和装置。混叠允许地址生成单元基于固定大小的地址空间访问可变大小的存储块，使得可以改变存储块的大小而不改变地址生成单元的地址生成软件。本发明提供了一种地址混叠装置，其被布置成从地址生成单元接收地址。地址混叠装置包括存储存储器块大小信息的寄存器。存储器块大小信息由地址混叠器件读取并被解码以提供表示存储块大小的位信息。地址混叠设备逻辑地将位信息与输入地址的适当对应位组合，以提供与存储块大小一致的别名地址。

2. 发明授权

US5202999A Access request prioritization and summary device 失效
标题翻译：访问请求优先级和摘要设备
公开(公告)号：US5202999A
公开(公告)日：1993-04-13
申请号：US819186
申请日：1992-01-10
申请人： John M. Lenthall , Neal A. Crook , Helen C. McGreal , Michael J. Seaman
发明人： John M. Lenthall , Neal A. Crook , Helen C. McGreal , Michael J. Seaman
IPC分类号： G06F13/37
CPC分类号： G06F13/37
摘要： An access request prioritization and summary device for determining the current highest priority among n entities. The device includes a bitmap having n bit storage locations. Each one of the n bit storage locations corresponds to one of the entities and is used to store a value which represents when the corresponding entity is available for prioritization. A plurality of combinational logic blocks are connected to the bitmap so that each one of the combinational logic blocks receives a preselected portion of the values stored in the n bit storage locations of the bitmap. Each one of the combinational logic blocks has a token signal input and a token signal output. The token signal inputs and outputs are coupled together to form a series of token signal links between the combinational logic blocks. When certain preselected highest priority determination conditions occur within one of the combinational logic blocks, the combinational logic block generates a token signal which serves as the token signal to the respective succeeding combinational logic block. Each combinational logic block is capable of receiving a token signal from the previous combinational logic block and is responsive to the input of a token signal to determine a current highest priority from the values which it received as input signals.
摘要翻译：用于确定n个实体当前最高优先级的访问请求优先级和摘要设备。该设备包括具有n位存储位置的位图。 n位存储位置中的每一个对应于一个实体，并且用于存储表示当对应实体可用于优先化的时间的值。多个组合逻辑块连接到位图，使得组合逻辑块中的每一个接收存储在位图的n位存储位置中的值的预选部分。组合逻辑块中的每一个具有令牌信号输入和令牌信号输出。令牌信号输入和输出耦合在一起以在组合逻辑块之间形成一系列令牌信号链路。当在组合逻辑块之一内发生某些预选的最高优先级确定条件时，组合逻辑块产生令牌信号，令牌信号用作相应的后续组合逻辑块的令牌信号。每个组合逻辑块能够从先前的组合逻辑块接收令牌信号，并响应于令牌信号的输入，以从作为输入信号接收的值确定当前最高优先级。

3. 发明授权

US5615382A Data transfer system for buffering and selectively manipulating the size of data blocks being transferred between a processor and a system bus of a computer system 失效
标题翻译：用于缓冲和选择性地操纵在计算机系统的处理器和系统总线之间传送的数据块的大小的数据传输系统
公开(公告)号：US5615382A
公开(公告)日：1997-03-25
申请号：US468486
申请日：1995-06-06
申请人： Vincent G. Gavin , Michael J. Seaman , Neal A. Crook , Bipin Mistry
发明人： Vincent G. Gavin , Michael J. Seaman , Neal A. Crook , Bipin Mistry
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4018
摘要： A data transfer device for coupling a processor to a system bus. The data transfer device includes data packers and unpackers for converting between data blocks of a first size and data blocks of a second size, e.g. between bytes or words and longwords. The data transfer device also includes an internal buffer memory system for storing the data being transferred. The processor and system bus are selectively coupled, each one at a time, via a direct data path, to the internal buffer memory system permitting both the processor and the system bus to independently read and write data, each at their normal data transfer rate.
摘要翻译：一种用于将处理器耦合到系统总线的数据传送装置。数据传输设备包括用于在第一大小的数据块和第二大小的数据块之间进行转换的数据打包器和解包器。字节或单词和长词之间。数据传送装置还包括用于存储被传送的数据的内部缓冲存储器系统。处理器和系统总线通过直接数据路径被选择性地耦合到内部缓冲存储器系统，允许处理器和系统总线独立地以其正常数据传输速率读取和写入数据。

4. 发明授权

US5471632A System for transferring data between a processor and a system bus including a device which packs, unpacks, or buffers data blocks being transferred 失效
标题翻译：用于在处理器和系统总线之间传送数据的系统，包括打包，解包或缓冲被传输的数据块的设备
公开(公告)号：US5471632A
公开(公告)日：1995-11-28
申请号：US819468
申请日：1992-01-10
申请人： Vincent G. Gavin , Michael J. Seaman , Neal A. Crook , Bipin Mistry
发明人： Vincent G. Gavin , Michael J. Seaman , Neal A. Crook , Bipin Mistry
IPC分类号： G06F13/40 , G06F13/38
CPC分类号： G06F13/4018
摘要： A data transfer device for coupling a processor to a system bus. The data transfer device includes data packers and unpackers for converting between data blocks of a first size and data blocks of a second size, e.g. between bytes or words and longwords. The data transfer device also includes an internal buffer memory system for storing the data being transferred. The processor and system bus are selectively coupled, each one at a time, via a direct data path, to the internal buffer memory system permitting both the processor and the system bus to independently read and write data, each at their normal data transfer rate.
摘要翻译：一种用于将处理器耦合到系统总线的数据传送装置。数据传输设备包括用于在第一大小的数据块和第二大小的数据块之间进行转换的数据打包器和解包器。字节或单词和长词之间。数据传送装置还包括用于存储被传送的数据的内部缓冲存储器系统。处理器和系统总线通过直接数据路径被选择性地耦合到内部缓冲存储器系统，允许处理器和系统总线独立地以其正常数据传输速率读取和写入数据。

5. 发明授权

US5386523A Addressing scheme for accessing a portion of a large memory space 失效
标题翻译：用于访问大内存空间的一部分的寻址方案
公开(公告)号：US5386523A
公开(公告)日：1995-01-31
申请号：US818607
申请日：1992-01-10
申请人： Neal A. Crook , Michael J. Seaman , David L. A. Brash
发明人： Neal A. Crook , Michael J. Seaman , David L. A. Brash
IPC分类号： G06F9/30 , G06F9/308 , G06F9/355 , G06F12/02 , G06F12/00 , G06F12/06
CPC分类号： G06F9/30018 , G06F12/0215 , G06F9/30112 , G06F9/342
摘要： A method for generating an address for addressable locations of a computer system where two registers are overlapped. Those bits of the two registers that overlap are logically combined together using a boolean operation when generating the address. Using this method, the higher order register can be used to select a segment of the addressable space of the computer system. Then, all accesses to that portion of the addressable space can be controlled by changing only the lower order register. This results in a saving of time since only one of the registers need be reloaded for each subsequent access.
摘要翻译：一种用于产生其中两个寄存器重叠的计算机系统的可寻址位置的地址的方法。重叠的两个寄存器的那些位在生成地址时使用布尔运算来逻辑地组合在一起。使用这种方法，可以使用高阶寄存器来选择计算机系统的可寻址空间的一段。然后，可以通过仅更改低阶寄存器来控制对可寻址空间的该部分的所有访问。这导致节省时间，因为每次后续访问只需要重新加载一个寄存器。

6. 发明授权

US5315707A Multiprocessor buffer system 失效
标题翻译：多处理器缓冲系统
公开(公告)号：US5315707A
公开(公告)日：1994-05-24
申请号：US818608
申请日：1992-01-10
申请人： Michael J. Seaman , Stewart F. Bryant
发明人： Michael J. Seaman , Stewart F. Bryant
IPC分类号： G06F13/38 , G06F9/46 , G06F15/16 , G06F15/167 , G06F13/00 , G06F12/00
CPC分类号： G06F9/544 , G06F15/167
摘要： The present invention is directed to a buffer swapping scheme to communicate a message from a first device to a second device wherein a pointer to a free buffer is returned to the first device by the second device as a condition for the first device to pass a pointer to a buffer containing a message intended for the second device.
摘要翻译：本发明涉及一种用于将消息从第一设备传送到第二设备的缓冲器交换方案，其中由第二设备将指向空闲缓冲区的指针返回到第一设备作为第一设备传递指针的条件到包含旨在用于第二设备的消息的缓冲器。

7. 发明授权

US5524254A Scheme for interlocking line card to an address recognition engine to support plurality of routing and bridging protocols by using network information look-up database 失效
标题翻译：将互联线卡与地址识别引擎相结合的方案，通过使用网络信息查找数据库来支持多个路由和桥接协议
公开(公告)号：US5524254A
公开(公告)日：1996-06-04
申请号：US269997
申请日：1994-07-01
申请人： Fearghal Morgan , Joseph O'Callaghan , Michael J. Seaman , John Rigby , Andrew Walton , Una M. Quinlan , Stewart F. Bryant
发明人： Fearghal Morgan , Joseph O'Callaghan , Michael J. Seaman , John Rigby , Andrew Walton , Una M. Quinlan , Stewart F. Bryant
IPC分类号： G06F13/00 , H04L12/46 , H04L29/06 , H04L29/12
CPC分类号： H04L29/12801 , H04L12/46 , H04L29/12009 , H04L29/12839 , H04L45/742 , H04L61/6004 , H04L61/6022 , H04L69/18 , H04L69/22
摘要： The present invention provides an interlock scheme for use between a line card and an address recognition apparatus. The interlock scheme reduces the total number of read/write operations over a backplane bus coupling the line card to the address recognition apparatus required to complete a request/response transfer. Thus, the line card and address recognition apparatus are able to perform a large amount of request/response transfers with a high level of system efficiency. Generally, the interlocking scheme according to the present invention merges each ownership information storage location into the location of the request/response memory utilized to store the corresponding request/response pair to reduce data transfer traffic over the backplane bus. According to another feature of the interlock scheme of the present invention, each of the line card and the address recognition engine includes a table for storing information relating to a plurality of database specifiers. Each of the database specifiers contains control information for the traversal of a lookup database used by the address recognition apparatus. At the time the processor of a line card generates a request for the address recognition apparatus, it will analyze the protocol type information contained in the header of a data packet. The processor will utilize the protocol type information as a look-up index to its table of database specifiers for selection of one of the database specifiers. The processor will then insert an identification of the selected database specifier into the request with the network address extracted from the data packet.
摘要翻译：本发明提供了一种用于线卡和地址识别装置之间的互锁方案。互锁方案减少了通过将线卡耦合到完成请求/响应传输所需的地址识别装置的背板总线上的读/写操作的总数。因此，线卡和地址识别装置能够以高水平的系统效率执行大量的请求/响应传送。通常，根据本发明的联锁方案将每个所有权信息存储位置合并到用于存储相应的请求/响应对的请求/响应存储器的位置，以减少背板总线上的数据传输流量。根据本发明的联锁方案的另一特征，线卡和地址识别引擎中的每一个都包括用于存储与多个数据库说明符有关的信息的表。每个数据库说明符包含用于遍历由地址识别装置使用的查找数据库的控制信息。当线卡的处理器产生对地址识别装置的请求时，它将分析包含在数据分组头部中的协议类型信息。处理器将利用协议类型信息作为其数据库说明符表的查找索引，以选择其中一个数据库说明符。然后处理器将所选择的数据库说明符的标识插入到从数据包中提取的网络地址的请求中。

8. 发明授权

US5519858A Address recognition engine with look-up database for storing network information 失效
标题翻译：地址识别引擎，具有用于存储网络信息的查找数据库
公开(公告)号：US5519858A
公开(公告)日：1996-05-21
申请号：US819490
申请日：1992-01-10
申请人： Andrew Walton , Una M. Quinlan , Stewart F. Bryant , Michael J. Seaman , John Rigby , Fearghal Morgan , Joseph O'Callaghan
发明人： Andrew Walton , Una M. Quinlan , Stewart F. Bryant , Michael J. Seaman , John Rigby , Fearghal Morgan , Joseph O'Callaghan
IPC分类号： G06F17/30 , H04L12/56 , H04L29/06
CPC分类号： H04L29/06
摘要： The present invention is directed to an address recognition apparatus including an address recognition engine coupled to a look-up database. The look-up database is arranged to store network information relating to network addresses. The look-up database includes a primary database and a secondary database. The address recognition engine accepts as an input a network address for which network information is required. The address recognition engine uses the network address as an index to the primary database. The primary database comprises a multiway tree node structure (TRIE) arranged for traversal of the nodes as a function of preselected segments of the network address and in a fixed sequence of the segments to locate a pointer to an entry in the secondary database. The entry in the secondary database pointed to by the primary database pointer contains the network information corresponding to the network address. The address recognition engine includes a table for storing a plurality of database specifiers. Each of the database specifiers contains control information for the traversal of the primary and secondary databases. In addition, each of the nodes in the primary database and each of the entries in the secondary database is provided with control data structures that are programmable to control the traversal of the database.
摘要翻译：本发明涉及包括耦合到查找数据库的地址识别引擎的地址识别装置。查找数据库被设置为存储与网络地址有关的网络信息。查找数据库包括主数据库和辅助数据库。地址识别引擎接受需要网络信息的网络地址作为输入。地址识别引擎使用网络地址作为主数据库的索引。主数据库包括多路树节点结构（TRIE），其被布置为根据网络地址的预选段的顺序遍历节点，并且在段的固定序列中定位到辅助数据库中的条目的指针。主数据库指针指向的辅助数据库中的条目包含与网络地址对应的网络信息。地址识别引擎包括用于存储多个数据库说明符的表。每个数据库说明符都包含用于遍历主数据库和辅助数据库的控制信息。此外，主数据库中的每个节点和辅助数据库中的每个条目都具有可编程以控制数据库遍历的控制数据结构。

9. 发明授权

US5590366A Packet forwarding system for measuring the age of data packets flowing through a computer network 失效
标题翻译：分组转发系统，用于测量流经计算机网络的数据包的年龄
公开(公告)号：US5590366A
公开(公告)日：1996-12-31
申请号：US421141
申请日：1995-04-13
申请人： Stewart F. Bryant , Michael J. Seaman , Christopher R. Szmidt
发明人： Stewart F. Bryant , Michael J. Seaman , Christopher R. Szmidt
IPC分类号： H04L12/56 , G06F13/00
CPC分类号： H04L47/10 , Y10S370/902
摘要： A packet forwarding node for a computer network comprises at least one receiving module and at least one output module including packet list (21) for maintaining a list of packets to be transmitted therefrom. The time for which a packet remains in the node is determined by grouping the packets into groups or "buckets" which are created at regular intervals, each bucket containing packets arriving within the same time interval, and keeping track of the age of each bucket. A bucket counter (33) counts the total number of buckets in existence, so indicating the age of the oldest packet. This counter is incremented by 1 at regular intervals and decremented by 1 each time the oldest bucket is emptied (or found to be empty). A bucket list shift register (30) has its contents shifted at each change of time interval, and its the bottom stage accumulates the number of packets arriving in a time interval, and an overflow accumulator (31) accumulates counts shifted out of its top end. The bucket list shift register may comprise a plurality of sections each of which is shifted at an exact submultiple of the rate of shifting of the previous section, the bottom stage of each section accumulating counts shifted out of the previous section. In an alternative embodiment, bucket boundary markers are inserted into the packet list at each change of time interval.
摘要翻译：用于计算机网络的分组转发节点包括至少一个接收模块和至少一个输出模块，所述至少一个输出模块包括用于维护要从其发送的分组的列表的分组列表（21）。分组保留在节点中的时间通过将分组分组为以规则间隔创建的分组或“分组”来确定，每个分组包含在相同时间间隔内到达的分组，并且跟踪每个分组的年龄。桶计数器（33）对存在的桶的总数进行计数，从而指示最旧包的年龄。该计数器以规则的间隔递增1，每当最旧的桶被清空（或发现为空）时减1。桶列表移位寄存器（30）的每个时间间隔的变化都有其内容，并且其底部段累积以时间间隔到达的分组的数量，并且溢出累加器（31）累积从其顶端移出的计数。铲斗列表移位寄存器可以包括多个部分，每个部分以前一部分的移位速率的精确多项移位，每个部分的底部累积计数从前一部分移出。在替代实施例中，每个时间间隔的每次更改都将桶边界标记插入到分组列表中。

10. 发明授权

US5195181A Message processing system having separate message receiving and transmitting processors with message processing being distributed between the separate processors 失效
标题翻译：消息处理系统具有分离的消息接收和发送处理器，其中消息处理被分配在各个处理器之间
公开(公告)号：US5195181A
公开(公告)日：1993-03-16
申请号：US820299
申请日：1992-01-10
申请人： Stewart F. Bryant , Michael J. Seaman
发明人： Stewart F. Bryant , Michael J. Seaman
IPC分类号： G06F13/00
CPC分类号： G06F13/00
摘要： A scheme for efficient implementation of workload partitioning between separate receive and transmit processors is provided so that a message can be effectively moved through a multiprocessor router. Generally, each receiving processor collects, into a digest, information relating to network protocol processing of a particular message, obtained via sequential byte processing of the message at the time of reception of the message. The information placed into the digest is information that is necessary for the completion of the processing tasks to be performed by the processor of the transmitting line card. The digest is passed to the transmit processor through a buffer exchange between the receive and transmit processors. The transmit processor reads the digest before processing of the related message for transmission and uses the information in the network protocol processing of the message. Thus, the transmit processor does not have to "look ahead" to bytes of the message needed to complete certain processing functions already completed by the receive processor and does require extra buffering and/or memory bandwidth to make the modifications to the message.
摘要翻译：提供了一种用于在单独的接收和发送处理器之间有效实施工作负载划分的方案，使得可以通过多处理器路由器有效地移动消息。通常，每个接收处理器在摘要中收集与在消息接收时通过消息的连续字节处理获得的特定消息的网络协议处理有关的信息。放入摘要的信息是完成由传输线卡的处理器执行的处理任务所必需的信息。摘要通过接收和发送处理器之间的缓冲区交换传递给发送处理器。发送处理器在处理相关消息以进行传输之前读取摘要，并使用消息的网络协议处理中的信息。因此，发送处理器不必向前瞻地看到完成由接收处理器已经完成的某些处理功能所需的消息的字节，并且需要额外的缓冲和/或存储器带宽来对消息进行修改。

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