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1. 发明授权

US5615382A Data transfer system for buffering and selectively manipulating the size of data blocks being transferred between a processor and a system bus of a computer system 失效
标题翻译：用于缓冲和选择性地操纵在计算机系统的处理器和系统总线之间传送的数据块的大小的数据传输系统
公开(公告)号：US5615382A
公开(公告)日：1997-03-25
申请号：US468486
申请日：1995-06-06
申请人： Vincent G. Gavin , Michael J. Seaman , Neal A. Crook , Bipin Mistry
发明人： Vincent G. Gavin , Michael J. Seaman , Neal A. Crook , Bipin Mistry
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4018
摘要： A data transfer device for coupling a processor to a system bus. The data transfer device includes data packers and unpackers for converting between data blocks of a first size and data blocks of a second size, e.g. between bytes or words and longwords. The data transfer device also includes an internal buffer memory system for storing the data being transferred. The processor and system bus are selectively coupled, each one at a time, via a direct data path, to the internal buffer memory system permitting both the processor and the system bus to independently read and write data, each at their normal data transfer rate.
摘要翻译：一种用于将处理器耦合到系统总线的数据传送装置。数据传输设备包括用于在第一大小的数据块和第二大小的数据块之间进行转换的数据打包器和解包器。字节或单词和长词之间。数据传送装置还包括用于存储被传送的数据的内部缓冲存储器系统。处理器和系统总线通过直接数据路径被选择性地耦合到内部缓冲存储器系统，允许处理器和系统总线独立地以其正常数据传输速率读取和写入数据。

2. 发明授权

US5471632A System for transferring data between a processor and a system bus including a device which packs, unpacks, or buffers data blocks being transferred 失效
标题翻译：用于在处理器和系统总线之间传送数据的系统，包括打包，解包或缓冲被传输的数据块的设备
公开(公告)号：US5471632A
公开(公告)日：1995-11-28
申请号：US819468
申请日：1992-01-10
申请人： Vincent G. Gavin , Michael J. Seaman , Neal A. Crook , Bipin Mistry
发明人： Vincent G. Gavin , Michael J. Seaman , Neal A. Crook , Bipin Mistry
IPC分类号： G06F13/40 , G06F13/38
CPC分类号： G06F13/4018
摘要： A data transfer device for coupling a processor to a system bus. The data transfer device includes data packers and unpackers for converting between data blocks of a first size and data blocks of a second size, e.g. between bytes or words and longwords. The data transfer device also includes an internal buffer memory system for storing the data being transferred. The processor and system bus are selectively coupled, each one at a time, via a direct data path, to the internal buffer memory system permitting both the processor and the system bus to independently read and write data, each at their normal data transfer rate.
摘要翻译：一种用于将处理器耦合到系统总线的数据传送装置。数据传输设备包括用于在第一大小的数据块和第二大小的数据块之间进行转换的数据打包器和解包器。字节或单词和长词之间。数据传送装置还包括用于存储被传送的数据的内部缓冲存储器系统。处理器和系统总线通过直接数据路径被选择性地耦合到内部缓冲存储器系统，允许处理器和系统总线独立地以其正常数据传输速率读取和写入数据。

3. 发明授权

US5357619A Paged memory scheme 失效
标题翻译：分页内存方案
公开(公告)号：US5357619A
公开(公告)日：1994-10-18
申请号：US819267
申请日：1992-01-10
申请人： Neal A. Crook , Vincent G. Gavin , Robert J. Galuszka , John M. Lenthall , Bipin Mistry , Clinton Choi , Paul L. Bruce
发明人： Neal A. Crook , Vincent G. Gavin , Robert J. Galuszka , John M. Lenthall , Bipin Mistry , Clinton Choi , Paul L. Bruce
IPC分类号： G06F12/02 , G06F12/06 , G06F13/00
CPC分类号： G06F12/0215 , G06F12/0623
摘要： An apparatus and method for supplying an address and data to an external memory device. The number of pins available for supplying the address is less than the number of address lines required at the external memory device. A register is used to store the high order bits of the address and is pre-loaded with a default page value. An output of the register is coupled to an address input of the external memory. If the high order bits of the address are equal to the default page value, a control device couples the data lines directly to the external memory device and a read or write operation follows. If the two values are different, a paging cycle is performed where the high order address bits are latched through the register to the address input of the external memory and then the data bits are coupled to the external memory device. If the default page value points to the most accessed portion of the external memory device, no paging is performed during access to that portion of the external memory and processing time is saved when reads or writes of data are made to that portion of the external memory.
摘要翻译：一种用于向外部存储器件提供地址和数据的装置和方法。可用于提供地址的引脚数小于外部存储器件所需的地址线数量。寄存器用于存储地址的高位，并且预加载了默认页面值。寄存器的输出耦合到外部存储器的地址输入。如果地址的高位等于默认页面值，则控制设备将数据线直接耦合到外部存储器件，并进行读取或写入操作。如果两个值不同，则执行寻呼周期，其中高位地址位通过寄存器锁存到外部存储器的地址输入，然后数据位耦合到外部存储器件。如果默认页面值指向外部存储器件最常访问的部分，则在访问外部存储器的该部分期间不执行寻呼，并且当对外部存储器的该部分进行数据的读取或写入时，保存处理时间。

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