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1. 发明授权

US5386523A Addressing scheme for accessing a portion of a large memory space 失效
标题翻译：用于访问大内存空间的一部分的寻址方案
公开(公告)号：US5386523A
公开(公告)日：1995-01-31
申请号：US818607
申请日：1992-01-10
申请人： Neal A. Crook , Michael J. Seaman , David L. A. Brash
发明人： Neal A. Crook , Michael J. Seaman , David L. A. Brash
IPC分类号： G06F9/30 , G06F9/308 , G06F9/355 , G06F12/02 , G06F12/00 , G06F12/06
CPC分类号： G06F9/30018 , G06F12/0215 , G06F9/30112 , G06F9/342
摘要： A method for generating an address for addressable locations of a computer system where two registers are overlapped. Those bits of the two registers that overlap are logically combined together using a boolean operation when generating the address. Using this method, the higher order register can be used to select a segment of the addressable space of the computer system. Then, all accesses to that portion of the addressable space can be controlled by changing only the lower order register. This results in a saving of time since only one of the registers need be reloaded for each subsequent access.
摘要翻译：一种用于产生其中两个寄存器重叠的计算机系统的可寻址位置的地址的方法。重叠的两个寄存器的那些位在生成地址时使用布尔运算来逻辑地组合在一起。使用这种方法，可以使用高阶寄存器来选择计算机系统的可寻址空间的一段。然后，可以通过仅更改低阶寄存器来控制对可寻址空间的该部分的所有访问。这导致节省时间，因为每次后续访问只需要重新加载一个寄存器。

2. 发明授权

US5485586A Queue based arbitration using a FIFO data structure 失效
标题翻译：使用FIFO数据结构进行基于队列的仲裁
公开(公告)号：US5485586A
公开(公告)日：1996-01-16
申请号：US222500
申请日：1994-04-05
申请人： David L. A. Brash , Neal A. Crook , John M. Lenthall
发明人： David L. A. Brash , Neal A. Crook , John M. Lenthall
IPC分类号： G06F13/364 , G06F13/36
CPC分类号： G06F13/364
摘要： A queue based arbiter to arbitrate between N devices of a computer system for access to a system bus which eliminates the need to maintain a history of bus transactions by queuing bus requests to track when a bus request is posted. The arbiter provides fair access to the bus by maintaining a queue of requests that come in from each resource in the computer system. This is accomplished by continually sampling the individual request lines of the devices to determine if a device is requesting access to the bus. Each time the arbiter detects a request from a device it puts an entry representative of the specific device that has requested the bus into a queue that has at least N entries. Requests are granted in the order that they are queued.
摘要翻译：一种基于队列的仲裁器，用于对用于访问系统总线的计算机系统的N个设备之间进行仲裁，从而消除了通过排队总线请求来跟踪总线请求被发布时的总线事务的维护历史。仲裁器通过维护来自计算机系统中的每个资源的请求的队列来提供公共访问总线。这是通过对设备的各个请求线进行连续采样来确定设备是否请求访问总线来实现的。每当仲裁器检测到来自设备的请求时，它将表示已经请求总线的特定设备的条目代表具有至少N个条目的队列。请求按排队的顺序授予。

3. 发明授权

US5615382A Data transfer system for buffering and selectively manipulating the size of data blocks being transferred between a processor and a system bus of a computer system 失效
标题翻译：用于缓冲和选择性地操纵在计算机系统的处理器和系统总线之间传送的数据块的大小的数据传输系统
公开(公告)号：US5615382A
公开(公告)日：1997-03-25
申请号：US468486
申请日：1995-06-06
申请人： Vincent G. Gavin , Michael J. Seaman , Neal A. Crook , Bipin Mistry
发明人： Vincent G. Gavin , Michael J. Seaman , Neal A. Crook , Bipin Mistry
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4018
摘要： A data transfer device for coupling a processor to a system bus. The data transfer device includes data packers and unpackers for converting between data blocks of a first size and data blocks of a second size, e.g. between bytes or words and longwords. The data transfer device also includes an internal buffer memory system for storing the data being transferred. The processor and system bus are selectively coupled, each one at a time, via a direct data path, to the internal buffer memory system permitting both the processor and the system bus to independently read and write data, each at their normal data transfer rate.
摘要翻译：一种用于将处理器耦合到系统总线的数据传送装置。数据传输设备包括用于在第一大小的数据块和第二大小的数据块之间进行转换的数据打包器和解包器。字节或单词和长词之间。数据传送装置还包括用于存储被传送的数据的内部缓冲存储器系统。处理器和系统总线通过直接数据路径被选择性地耦合到内部缓冲存储器系统，允许处理器和系统总线独立地以其正常数据传输速率读取和写入数据。

4. 发明授权

US5202999A Access request prioritization and summary device 失效
标题翻译：访问请求优先级和摘要设备
公开(公告)号：US5202999A
公开(公告)日：1993-04-13
申请号：US819186
申请日：1992-01-10
申请人： John M. Lenthall , Neal A. Crook , Helen C. McGreal , Michael J. Seaman
发明人： John M. Lenthall , Neal A. Crook , Helen C. McGreal , Michael J. Seaman
IPC分类号： G06F13/37
CPC分类号： G06F13/37
摘要： An access request prioritization and summary device for determining the current highest priority among n entities. The device includes a bitmap having n bit storage locations. Each one of the n bit storage locations corresponds to one of the entities and is used to store a value which represents when the corresponding entity is available for prioritization. A plurality of combinational logic blocks are connected to the bitmap so that each one of the combinational logic blocks receives a preselected portion of the values stored in the n bit storage locations of the bitmap. Each one of the combinational logic blocks has a token signal input and a token signal output. The token signal inputs and outputs are coupled together to form a series of token signal links between the combinational logic blocks. When certain preselected highest priority determination conditions occur within one of the combinational logic blocks, the combinational logic block generates a token signal which serves as the token signal to the respective succeeding combinational logic block. Each combinational logic block is capable of receiving a token signal from the previous combinational logic block and is responsive to the input of a token signal to determine a current highest priority from the values which it received as input signals.
摘要翻译：用于确定n个实体当前最高优先级的访问请求优先级和摘要设备。该设备包括具有n位存储位置的位图。 n位存储位置中的每一个对应于一个实体，并且用于存储表示当对应实体可用于优先化的时间的值。多个组合逻辑块连接到位图，使得组合逻辑块中的每一个接收存储在位图的n位存储位置中的值的预选部分。组合逻辑块中的每一个具有令牌信号输入和令牌信号输出。令牌信号输入和输出耦合在一起以在组合逻辑块之间形成一系列令牌信号链路。当在组合逻辑块之一内发生某些预选的最高优先级确定条件时，组合逻辑块产生令牌信号，令牌信号用作相应的后续组合逻辑块的令牌信号。每个组合逻辑块能够从先前的组合逻辑块接收令牌信号，并响应于令牌信号的输入，以从作为输入信号接收的值确定当前最高优先级。

5. 发明授权

US5471632A System for transferring data between a processor and a system bus including a device which packs, unpacks, or buffers data blocks being transferred 失效
标题翻译：用于在处理器和系统总线之间传送数据的系统，包括打包，解包或缓冲被传输的数据块的设备
公开(公告)号：US5471632A
公开(公告)日：1995-11-28
申请号：US819468
申请日：1992-01-10
申请人： Vincent G. Gavin , Michael J. Seaman , Neal A. Crook , Bipin Mistry
发明人： Vincent G. Gavin , Michael J. Seaman , Neal A. Crook , Bipin Mistry
IPC分类号： G06F13/40 , G06F13/38
CPC分类号： G06F13/4018
摘要： A data transfer device for coupling a processor to a system bus. The data transfer device includes data packers and unpackers for converting between data blocks of a first size and data blocks of a second size, e.g. between bytes or words and longwords. The data transfer device also includes an internal buffer memory system for storing the data being transferred. The processor and system bus are selectively coupled, each one at a time, via a direct data path, to the internal buffer memory system permitting both the processor and the system bus to independently read and write data, each at their normal data transfer rate.
摘要翻译：一种用于将处理器耦合到系统总线的数据传送装置。数据传输设备包括用于在第一大小的数据块和第二大小的数据块之间进行转换的数据打包器和解包器。字节或单词和长词之间。数据传送装置还包括用于存储被传送的数据的内部缓冲存储器系统。处理器和系统总线通过直接数据路径被选择性地耦合到内部缓冲存储器系统，允许处理器和系统总线独立地以其正常数据传输速率读取和写入数据。

6. 发明授权

US5404474A Apparatus and method for addressing a variable sized block of memory 失效
标题翻译：用于寻址可变大小的存储器块的装置和方法
公开(公告)号：US5404474A
公开(公告)日：1995-04-04
申请号：US819393
申请日：1992-01-10
申请人： Neal A. Crook , Stewart F. Bryant , Michael J. Seaman , John M. Lenthall
发明人： Neal A. Crook , Stewart F. Bryant , Michael J. Seaman , John M. Lenthall
IPC分类号： G06F12/02 , G06F12/06
CPC分类号： G06F12/0223
摘要： A method and apparatus for aliasing an address for a location in a memory system. The aliasing permits an address generating unit to access a memory block of variable size based upon an address space of fixed size so that the size of the memory block can be changed without changing the address generating software of the address generating unit. The invention provides an address aliasing device arranged to receive an address from the address generating unit. The address aliasing device includes a register that stores memory block size information. The memory block size information is read by the address aliasing device and decoded to provide bit information representative of the size of the memory block. The address aliasing device logically combines the bit information with appropriate corresponding bits of the input address to provide an alias address that is consistent with the size of the memory block.
摘要翻译：一种用于对存储器系统中的位置进行混叠的地址的方法和装置。混叠允许地址生成单元基于固定大小的地址空间访问可变大小的存储块，使得可以改变存储块的大小而不改变地址生成单元的地址生成软件。本发明提供了一种地址混叠装置，其被布置成从地址生成单元接收地址。地址混叠装置包括存储存储器块大小信息的寄存器。存储器块大小信息由地址混叠器件读取并被解码以提供表示存储块大小的位信息。地址混叠设备逻辑地将位信息与输入地址的适当对应位组合，以提供与存储块大小一致的别名地址。

7. 发明授权

US06754772B2 Distributed cache 失效
标题翻译：分布式缓存
公开(公告)号：US06754772B2
公开(公告)日：2004-06-22
申请号：US09987765
申请日：2001-11-15
申请人： Neal A. Crook , Alan Wootton
发明人： Neal A. Crook , Alan Wootton
IPC分类号： G06F1208
CPC分类号： G06T15/005 , G06F12/0855 , G06T1/20
摘要： A system and method for distributed cache. Cache tag storage and cache data storage are maintained in separate pipeline stages. Cache tag storage is operated by a data producer. Cache data storage is operated by a data consumer. Cache hits and misses are determined by the data producer prior to any operations being performed by the processor. In the event of a cache miss, produced data is sent to the processor to be processed. In the event of a cache hit, the cache address of the corresponding previously processed data is sent to the data consumer so that the corresponding processed data unit can be retrieved from cache data storage.
摘要翻译：一种用于分布式缓存的系统和方法。缓存标签存储和高速缓存数据存储保持在不同的流水线阶段。缓存标签存储由数据生成器操作。缓存数据存储由数据消费者操作。在处理器执行任何操作之前，数据生成器确定缓存命中和丢失。在出现高速缓存未命中的情况下，产生的数据被发送到要处理的处理器。在高速缓存命中的情况下，相应的先前处理的数据的高速缓存地址被发送到数据消费者，从而可以从高速缓存数据存储中检索相应的处理数据单元。

8. 发明授权

US07505317B2 Method, apparatus, and system for providing initial state random access memory 有权
标题翻译：用于提供初始状态随机存取存储器的方法，装置和系统
公开(公告)号：US07505317B2
公开(公告)日：2009-03-17
申请号：US11449755
申请日：2006-06-09
申请人： Neal A. Crook , David J. Warner
发明人： Neal A. Crook , David J. Warner
IPC分类号： G11C11/34 , G11C14/00
CPC分类号： G11C7/20 , G11C11/412
摘要： A memory device comprising memory cells having volatile and non-volatile memory portions. The volatile memory portion of each cell includes circuitry for performing RAM functions while the non-volatile memory portion comprises circuitry defining pre-coded data. The memory device comprises a mechanism to operate an initialization sequence, which sets the initial state of the volatile memory portion of each memory cell to the pre-coded data defined in the associated non-volatile memory portion. The initialization sequence allows the initial state of each memory cell's volatile portion to be re-established after power has been applied to the memory device.
摘要翻译：一种包括具有易失性和非易失性存储器部分的存储单元的存储器件。每个单元的易失性存储器部分包括用于执行RAM功能的电路，而非易失性存储器部分包括定义预编码数据的电路。存储器件包括一个操作初始化序列的机制，该初始化序列将每个存储器单元的易失性存储器部分的初始状态设置为在相关联的非易失性存储器部分中定义的预编码数据。初始化顺序允许在向存储器件施加电力之后，重新建立每个存储单元的易失性部分的初始状态。

9. 发明授权

US06889289B2 Method of distributed caching 有权
标题翻译：分布式缓存方法
公开(公告)号：US06889289B2
公开(公告)日：2005-05-03
申请号：US10861499
申请日：2004-06-07
申请人： Neal A. Crook , Alan Wootton
发明人： Neal A. Crook , Alan Wootton
IPC分类号： G06F12/08 , G06F13/00 , G06T1/20 , G06T15/00 , G09G5/36
CPC分类号： G06T15/005 , G06F12/0855 , G06T1/20
摘要： A system and method for distributed cache. Cache tag storage and cache data storage are maintained in separate pipeline stages. Cache tag storage is operated by a data producer. Cache data storage is operated by a data consumer. Cache hits and misses are determined by the data producer prior to any operations being performed by the processor. In the event of a cache miss, produced data is sent to the processor to be processed. In the event of a cache hit, the cache address of the corresponding previously processed data is sent to the data consumer so that the corresponding processed data unit can be retrieved from cache data storage.
摘要翻译：一种用于分布式缓存的系统和方法。缓存标签存储和高速缓存数据存储保持在不同的流水线阶段。缓存标签存储由数据生成器操作。缓存数据存储由数据消费者操作。在处理器执行任何操作之前，数据生成器确定缓存命中和丢失。在出现高速缓存未命中的情况下，产生的数据被发送到要处理的处理器。在高速缓存命中的情况下，相应的先前处理的数据的高速缓存地址被发送到数据消费者，从而可以从高速缓存数据存储中检索相应的处理数据单元。

10. 发明申请

US20070263443A1 Method, apparatus, and system for providing initial state random access memory 有权
标题翻译：用于提供初始状态随机存取存储器的方法，装置和系统
公开(公告)号：US20070263443A1
公开(公告)日：2007-11-15
申请号：US11449755
申请日：2006-06-09
申请人： Neal A. Crook , David J. Warner
发明人： Neal A. Crook , David J. Warner
IPC分类号： G11C14/00
CPC分类号： G11C7/20 , G11C11/412
摘要： A memory device comprising memory cells having volatile and non-volatile memory portions. The volatile memory portion of each cell includes circuitry for performing RAM functions while the non-volatile memory portion comprises circuitry defining pre-coded data. The memory device comprises a mechanism to operate an initialization sequence, which sets the initial state of the volatile memory portion of each memory cell to the pre-coded data defined in the associated non-volatile memory portion. The initialization sequence allows the initial state of each memory cell's volatile portion to be re-established after power has been applied to the memory device.
摘要翻译：一种包括具有易失性和非易失性存储器部分的存储单元的存储器件。每个单元的易失性存储器部分包括用于执行RAM功能的电路，而非易失性存储器部分包括定义预编码数据的电路。存储器件包括一个操作初始化序列的机制，该初始化序列将每个存储器单元的易失性存储器部分的初始状态设置为在相关联的非易失性存储器部分中定义的预编码数据。初始化顺序允许在向存储器件施加电力之后，重新建立每个存储单元的易失性部分的初始状态。

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