专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5202999A Access request prioritization and summary device 失效
标题翻译：访问请求优先级和摘要设备
公开(公告)号：US5202999A
公开(公告)日：1993-04-13
申请号：US819186
申请日：1992-01-10
申请人： John M. Lenthall , Neal A. Crook , Helen C. McGreal , Michael J. Seaman
发明人： John M. Lenthall , Neal A. Crook , Helen C. McGreal , Michael J. Seaman
IPC分类号： G06F13/37
CPC分类号： G06F13/37
摘要： An access request prioritization and summary device for determining the current highest priority among n entities. The device includes a bitmap having n bit storage locations. Each one of the n bit storage locations corresponds to one of the entities and is used to store a value which represents when the corresponding entity is available for prioritization. A plurality of combinational logic blocks are connected to the bitmap so that each one of the combinational logic blocks receives a preselected portion of the values stored in the n bit storage locations of the bitmap. Each one of the combinational logic blocks has a token signal input and a token signal output. The token signal inputs and outputs are coupled together to form a series of token signal links between the combinational logic blocks. When certain preselected highest priority determination conditions occur within one of the combinational logic blocks, the combinational logic block generates a token signal which serves as the token signal to the respective succeeding combinational logic block. Each combinational logic block is capable of receiving a token signal from the previous combinational logic block and is responsive to the input of a token signal to determine a current highest priority from the values which it received as input signals.
摘要翻译：用于确定n个实体当前最高优先级的访问请求优先级和摘要设备。该设备包括具有n位存储位置的位图。 n位存储位置中的每一个对应于一个实体，并且用于存储表示当对应实体可用于优先化的时间的值。多个组合逻辑块连接到位图，使得组合逻辑块中的每一个接收存储在位图的n位存储位置中的值的预选部分。组合逻辑块中的每一个具有令牌信号输入和令牌信号输出。令牌信号输入和输出耦合在一起以在组合逻辑块之间形成一系列令牌信号链路。当在组合逻辑块之一内发生某些预选的最高优先级确定条件时，组合逻辑块产生令牌信号，令牌信号用作相应的后续组合逻辑块的令牌信号。每个组合逻辑块能够从先前的组合逻辑块接收令牌信号，并响应于令牌信号的输入，以从作为输入信号接收的值确定当前最高优先级。

2. 发明授权

US5357619A Paged memory scheme 失效
标题翻译：分页内存方案
公开(公告)号：US5357619A
公开(公告)日：1994-10-18
申请号：US819267
申请日：1992-01-10
申请人： Neal A. Crook , Vincent G. Gavin , Robert J. Galuszka , John M. Lenthall , Bipin Mistry , Clinton Choi , Paul L. Bruce
发明人： Neal A. Crook , Vincent G. Gavin , Robert J. Galuszka , John M. Lenthall , Bipin Mistry , Clinton Choi , Paul L. Bruce
IPC分类号： G06F12/02 , G06F12/06 , G06F13/00
CPC分类号： G06F12/0215 , G06F12/0623
摘要： An apparatus and method for supplying an address and data to an external memory device. The number of pins available for supplying the address is less than the number of address lines required at the external memory device. A register is used to store the high order bits of the address and is pre-loaded with a default page value. An output of the register is coupled to an address input of the external memory. If the high order bits of the address are equal to the default page value, a control device couples the data lines directly to the external memory device and a read or write operation follows. If the two values are different, a paging cycle is performed where the high order address bits are latched through the register to the address input of the external memory and then the data bits are coupled to the external memory device. If the default page value points to the most accessed portion of the external memory device, no paging is performed during access to that portion of the external memory and processing time is saved when reads or writes of data are made to that portion of the external memory.
摘要翻译：一种用于向外部存储器件提供地址和数据的装置和方法。可用于提供地址的引脚数小于外部存储器件所需的地址线数量。寄存器用于存储地址的高位，并且预加载了默认页面值。寄存器的输出耦合到外部存储器的地址输入。如果地址的高位等于默认页面值，则控制设备将数据线直接耦合到外部存储器件，并进行读取或写入操作。如果两个值不同，则执行寻呼周期，其中高位地址位通过寄存器锁存到外部存储器的地址输入，然后数据位耦合到外部存储器件。如果默认页面值指向外部存储器件最常访问的部分，则在访问外部存储器的该部分期间不执行寻呼，并且当对外部存储器的该部分进行数据的读取或写入时，保存处理时间。

3. 发明授权

US5485586A Queue based arbitration using a FIFO data structure 失效
标题翻译：使用FIFO数据结构进行基于队列的仲裁
公开(公告)号：US5485586A
公开(公告)日：1996-01-16
申请号：US222500
申请日：1994-04-05
申请人： David L. A. Brash , Neal A. Crook , John M. Lenthall
发明人： David L. A. Brash , Neal A. Crook , John M. Lenthall
IPC分类号： G06F13/364 , G06F13/36
CPC分类号： G06F13/364
摘要： A queue based arbiter to arbitrate between N devices of a computer system for access to a system bus which eliminates the need to maintain a history of bus transactions by queuing bus requests to track when a bus request is posted. The arbiter provides fair access to the bus by maintaining a queue of requests that come in from each resource in the computer system. This is accomplished by continually sampling the individual request lines of the devices to determine if a device is requesting access to the bus. Each time the arbiter detects a request from a device it puts an entry representative of the specific device that has requested the bus into a queue that has at least N entries. Requests are granted in the order that they are queued.
摘要翻译：一种基于队列的仲裁器，用于对用于访问系统总线的计算机系统的N个设备之间进行仲裁，从而消除了通过排队总线请求来跟踪总线请求被发布时的总线事务的维护历史。仲裁器通过维护来自计算机系统中的每个资源的请求的队列来提供公共访问总线。这是通过对设备的各个请求线进行连续采样来确定设备是否请求访问总线来实现的。每当仲裁器检测到来自设备的请求时，它将表示已经请求总线的特定设备的条目代表具有至少N个条目的队列。请求按排队的顺序授予。

4. 发明授权

US5404474A Apparatus and method for addressing a variable sized block of memory 失效
标题翻译：用于寻址可变大小的存储器块的装置和方法
公开(公告)号：US5404474A
公开(公告)日：1995-04-04
申请号：US819393
申请日：1992-01-10
申请人： Neal A. Crook , Stewart F. Bryant , Michael J. Seaman , John M. Lenthall
发明人： Neal A. Crook , Stewart F. Bryant , Michael J. Seaman , John M. Lenthall
IPC分类号： G06F12/02 , G06F12/06
CPC分类号： G06F12/0223
摘要： A method and apparatus for aliasing an address for a location in a memory system. The aliasing permits an address generating unit to access a memory block of variable size based upon an address space of fixed size so that the size of the memory block can be changed without changing the address generating software of the address generating unit. The invention provides an address aliasing device arranged to receive an address from the address generating unit. The address aliasing device includes a register that stores memory block size information. The memory block size information is read by the address aliasing device and decoded to provide bit information representative of the size of the memory block. The address aliasing device logically combines the bit information with appropriate corresponding bits of the input address to provide an alias address that is consistent with the size of the memory block.
摘要翻译：一种用于对存储器系统中的位置进行混叠的地址的方法和装置。混叠允许地址生成单元基于固定大小的地址空间访问可变大小的存储块，使得可以改变存储块的大小而不改变地址生成单元的地址生成软件。本发明提供了一种地址混叠装置，其被布置成从地址生成单元接收地址。地址混叠装置包括存储存储器块大小信息的寄存器。存储器块大小信息由地址混叠器件读取并被解码以提供表示存储块大小的位信息。地址混叠设备逻辑地将位信息与输入地址的适当对应位组合，以提供与存储块大小一致的别名地址。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式