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1. 发明授权

US06600190B2 Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions 有权
标题翻译：形成电容器的方法，形成电容器 - 位线存储器电路的方法以及相关的集成电路结构
公开(公告)号：US06600190B2
公开(公告)日：2003-07-29
申请号：US09730865
申请日：2000-12-05
申请人： Tyler A. Lowrey , Luan C. Tran , Alan R. Reinberg , D. Mark Durcan
发明人： Tyler A. Lowrey , Luan C. Tran , Alan R. Reinberg , D. Mark Durcan
IPC分类号： H01L27108
CPC分类号： H01L28/90 , H01L27/10814 , H01L27/10852 , H01L27/10894 , H01L28/84 , H01L28/91
摘要： Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material.
摘要翻译：描述形成电容器的方法，形成电容器 - 位线存储器电路的方法以及相关的集成电路结构。在一个实施例中，形成在最上表面上具有最上表面和上覆绝缘材料的电容器存储节点。随后，电容器电介质功能区域从可覆盖的电容器存储节点的至少一部分可操作地从上覆的绝缘材料离散形成。在电容器电介质功能区域和上覆绝缘材料上形成电池电极层。

2. 发明授权

US06312988B1 Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions 失效
标题翻译：形成电容器的方法，形成电容器 - 位线存储器电路的方法以及相关的集成电路结构
公开(公告)号：US06312988B1
公开(公告)日：2001-11-06
申请号：US09389532
申请日：1999-09-02
申请人： Tyler A. Lowrey , Luan C. Tran , Alan R. Reinberg , D. Mark Durcan
发明人： Tyler A. Lowrey , Luan C. Tran , Alan R. Reinberg , D. Mark Durcan
IPC分类号： H01L218242
CPC分类号： H01L28/90 , H01L27/10814 , H01L27/10852 , H01L27/10894 , H01L28/84 , H01L28/91
摘要： Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material. In another embodiment, a capacitor storage node is formed having an uppermost surface and a side surface joined therewith. A protective cap is formed over the uppe-most surface and a capacitor dielectric layer is formed over the side surface and protective cap. A cell electrode layer is formed over the side surface of the capacitor storage node. In yet another embodiment, a plurality of capacitor storage nodes are formed arranged in columns. A common cell electrode layer is formed over the plurality of capacitor storage nodes. Cell electrode layer material is removed from between the columns and isolates individual cell electrodes over individual respective capacitor storage nodes. After the removing of the cell electrode layer material, conductive material is formed over portions of remaining cell electrode material thereby placing some of the individual cell electrodes into electrical communication with one another.
摘要翻译：描述形成电容器的方法，形成电容器 - 位线存储器电路的方法以及相关的集成电路结构。在一个实施例中，形成在最上表面上具有最上表面和上覆绝缘材料的电容器存储节点。随后，电容器电介质功能区域从可覆盖的电容器存储节点的至少一部分可操作地从上覆的绝缘材料离散形成。在电容器电介质功能区域和上覆绝缘材料上形成电池电极层。在另一个实施例中，电容器存储节点形成为具有与其接合的最上表面和侧表面。在最大表面上形成保护帽，并且在侧表面和保护盖上形成电容器电介质层。在电容器存储节点的侧表面上形成电池电极层。在另一个实施例中，形成多列电容器存储节点。在多个电容器存储节点上形成公共电极电极层。从柱之间移除电极电极层材料，并在各个电容器存储节点上隔离各个电池电极。在除去电池电极层材料之后，在剩余的电池电极材料的部分上形成导电材料，从而使一些单个电池电极彼此电连通。

3. 发明授权

US06599800B2 Methods of forming capacitors, and methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions 有权
标题翻译：形成电容器的方法以及形成电容器对位线存储器电路的方法以及相关的集成电路结构
公开(公告)号：US06599800B2
公开(公告)日：2003-07-29
申请号：US09954340
申请日：2001-09-14
申请人： Tyler A. Lowrey , Luan C. Tran , Alan R. Reinberg , Mark Durcan
发明人： Tyler A. Lowrey , Luan C. Tran , Alan R. Reinberg , Mark Durcan
IPC分类号： A01L218242
CPC分类号： H01L28/90 , H01L27/10814 , H01L27/10852 , H01L27/10894 , H01L28/84 , H01L28/91
摘要： Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material.
摘要翻译：描述形成电容器的方法，形成电容器 - 位线存储器电路的方法以及相关的集成电路结构。在一个实施例中，形成在最上表面上具有最上表面和上覆绝缘材料的电容器存储节点。随后，电容器电介质功能区域从可覆盖的电容器存储节点的至少一部分可操作地从上覆的绝缘材料离散形成。在电容器电介质功能区域和上覆绝缘材料上形成电池电极层。

4. 发明授权

US06995059B2 Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions 失效
公开(公告)号：US06995059B2
公开(公告)日：2006-02-07
申请号：US10627468
申请日：2003-07-25
申请人： Tyler A. Lowrey , Luan C. Tran , Alan R. Reinberg , Mark Durcan
发明人： Tyler A. Lowrey , Luan C. Tran , Alan R. Reinberg , Mark Durcan
IPC分类号： H01L21/8242
CPC分类号： H01L28/90 , H01L27/10814 , H01L27/10852 , H01L27/10894 , H01L28/84 , H01L28/91
摘要： Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material.

5. 发明授权

US06456535B2 Dynamic flash memory cells with ultra thin tunnel oxides 有权
标题翻译：具有超薄隧道氧化物的动态闪存单元
公开(公告)号：US06456535B2
公开(公告)日：2002-09-24
申请号：US09882920
申请日：2001-06-15
申请人： Leonard Forbes , Luan C. Tran , Alan R. Reinberg , Joseph E. Geusic , Kie Y. Ahn , Paul A. Farrar , Eugene H. Cloud , David J. McElroy
发明人： Leonard Forbes , Luan C. Tran , Alan R. Reinberg , Joseph E. Geusic , Kie Y. Ahn , Paul A. Farrar , Eugene H. Cloud , David J. McElroy
IPC分类号： G11C1604
CPC分类号： G11C16/0416
摘要： Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (Å). According to the teachings of the present invention, the floating gate is adapted to hold a charge of the order of 10−17 Coulombs at for at least 1.0 second at 85 degrees Celsius. The method includes applying a potential of less than 3.0 Volts across the floating gate oxide which is less than 50 Angstroms, in order to add or remove a charge from a floating gate. The method further includes reading the n-channel memory cell by applying a potential to a control gate of the n-channel memory cell of less than 1.0 Volt.
摘要翻译：已经提供了涉及具有超薄隧道氧化物厚度的n通道闪速存储器的结构和方法。写和擦除操作都通过隧道执行。根据本发明的教导，具有薄隧道氧化物的n沟道闪存单元将在动态的基础上操作。存储的数据可以根据需要每隔几秒刷新一次。然而，写入和擦除操作现在将比传统的n通道快闪存储器快几个数量级，并且电池提供了大的增益。本发明还提供了可以避免n沟道阈值电压偏移并实现源极侧漏极擦除的n沟道浮栅晶体管的结构和方法。 n沟道存储单元结构包括通过小于50埃（A）的氧化物层与沟道区分离的浮栅。根据本发明的教导，浮动门适于在85摄氏度下将10-17库仑的电荷持续至少1.0秒。该方法包括在小于50埃的浮栅上施加小于3.0伏特的电位，以从浮栅中增加或去除电荷。该方法还包括通过向n沟道存储单元的控制栅极施加小于1.0伏的电位来读取n沟道存储单元。

6. 发明授权

US06249460B1 Dynamic flash memory cells with ultrathin tunnel oxides 有权
标题翻译：具有超薄隧道氧化物的动态闪存单元
公开(公告)号：US06249460B1
公开(公告)日：2001-06-19
申请号：US09513938
申请日：2000-02-28
申请人： Leonard Forbes , Luan C. Tran , Alan R. Reinberg , Joseph E. Geusic , Kie Y. Ahn , Paul A. Farrar , Eugene H. Cloud , David J. McElroy
发明人： Leonard Forbes , Luan C. Tran , Alan R. Reinberg , Joseph E. Geusic , Kie Y. Ahn , Paul A. Farrar , Eugene H. Cloud , David J. McElroy
IPC分类号： G11C1604
CPC分类号： G11C16/0416
摘要： Structures and methods involving n-channel flash memories with an ultrathin tunnel oxide thickness, have been provided. Both the write and erase operations are performed by tunneling. According to the teachings of the present invention, the n-channel flash memory cell with thin tunnel oxides will operate on a dynamic basis. The stored data can be refreshed every few seconds as necessary. However, the write and erase operations will however now be orders of magnitude faster than traditional n-channel flash memory and the cell provides a large gain. The present invention further provides structures and methods for n-channel floating gate transistors which avoid n-channel threshold voltage shifts and achieve source side tunneling erase. The n-channel memory cell structure includes a floating gate separated from a channel region by an oxide layer of less than 50 Angstroms (Å). According to the teachings of the present invention, the floating gate is adapted to hold a charge of the order of 10−17 Coulombs at for at least 1.0 second at 85 degrees Celsius. The method includes applying a potential of less than 3.0 Volts across the floating gate oxide which is less than 50 Angstroms, in order to add or remove a charge from a floating gate. The method further includes reading the n-channel memory cell by applying a potential to a control gate of the n-channel memory cell of less than 1.0 Volt.
摘要翻译：已经提供了涉及具有超薄隧道氧化物厚度的n通道闪速存储器的结构和方法。写和擦除操作都通过隧道执行。根据本发明的教导，具有薄隧道氧化物的n沟道闪存单元将在动态的基础上操作。存储的数据可以根据需要每隔几秒刷新一次。然而，写入和擦除操作现在将比传统的n通道快闪存储器快几个数量级，并且电池提供了大的增益。本发明还提供了可以避免n沟道阈值电压偏移并实现源极侧漏极擦除的n沟道浮栅晶体管的结构和方法。 n沟道存储单元结构包括通过小于50埃（A）的氧化物层与沟道区分离的浮栅。根据本发明的教导，浮动门适于在85摄氏度下将10-17库仑的电荷持续至少1.0秒。该方法包括在小于50埃的浮栅上施加小于3.0伏特的电位，以从浮栅中增加或去除电荷。该方法还包括通过向n沟道存储单元的控制栅极施加小于1.0伏的电位来读取n沟道存储单元。

7. 发明授权

US5360992A Two piece assembly for the selection of pinouts and bond options on a semiconductor device 失效
标题翻译：用于在半导体器件上选择管脚和焊接选项的两件式组件
公开(公告)号：US5360992A
公开(公告)日：1994-11-01
申请号：US221974
申请日：1994-04-01
申请人： Tyler A. Lowrey , Alan R. Reinberg , Kevin D. Martin
发明人： Tyler A. Lowrey , Alan R. Reinberg , Kevin D. Martin
IPC分类号： H01L23/495 , H01L23/48 , H01L29/44 , H01L29/52 , H01L29/60
CPC分类号： H01L23/49537 , H01L23/49517 , H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L24/48 , H01L2924/00014 , H01L2924/01014 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/181
摘要： The invention comprises a semiconductor package which allows pinouts and bond options to be customized after the encasement of a die in plastic, ceramic, or other suitable materials. A first embodiment of the invention has a first assembly comprising an encapsulated die having bond pads connected to bond wires which terminate in exterior pad portions on the exterior of the encapsulant. Conductive paths which are part of a second assembly electrically connect with the exterior pad portions of the first assembly and pass signals to device pinouts, which can be leads or other connecting means, to an electronic device into which the module is installed. By selectively connecting the exterior pad portions of the first assembly to the connection points of the conductive paths of the second assembly, the device pinouts and bond options can be selected. To manufacture a device having different pinouts or bond options, a bottom section having a different design is used.
摘要翻译：本发明包括一种半导体封装，其允许在将塑料，陶瓷或其它合适材料封装在一起之后定制引脚和焊接选项。本发明的第一实施例具有第一组件，其包括具有连接到接合线的封装管芯，该接合焊接终止于密封剂外部的外部焊盘部分。作为第二组件的一部分的导电路径与第一组件的外部焊盘部分电连接，并将信号传递到可以是引线或其他连接装置的装置引线引导到安装模块的电子装置。通过选择性地将第一组件的外部焊盘部分连接到第二组件的导电路径的连接点，可以选择装置引脚分布和焊接选项。为了制造具有不同引脚或接合选项的器件，使用具有不同设计的底部部分。

8. 发明授权

US06356500B1 Reduced power DRAM device and method 有权
标题翻译：降低功耗的DRAM器件和方法
公开(公告)号：US06356500B1
公开(公告)日：2002-03-12
申请号：US09643945
申请日：2000-08-23
申请人： Eugene H. Cloud , Kie Y. Ahn , Leonard Forbes , Paul A. Farrar , Kevin G. Donohoe , Alan R. Reinberg , David J. Mcelroy , Luan C. Tran , Joseph Geusic
发明人： Eugene H. Cloud , Kie Y. Ahn , Leonard Forbes , Paul A. Farrar , Kevin G. Donohoe , Alan R. Reinberg , David J. Mcelroy , Luan C. Tran , Joseph Geusic
IPC分类号： G11C700
CPC分类号： G11C8/12 , G11C5/14 , G11C11/4074
摘要： A memory device and method employing a scheme for reduced power consumption is disclosed. By dividing a memory array sector into memory sub arrays, the memory device can provide power to memory sub arrays that need to be powered up or, in the alternative, powered down. This reduces the power consumption and heat generation associated with high speed and high capacity memory devices.
摘要翻译：公开了一种采用降低功耗的方案的存储器件和方法。通过将存储器阵列扇区划分成存储器子阵列，存储器件可以为需要上电的存储器子阵列或替代地断电提供电力。这降低了与高速和高容量存储器件相关联的功耗和发热。

9. 发明申请

US20100055871A1 MEMORY IN LOGIC CELL 有权
标题翻译：存储在逻辑单元
公开(公告)号：US20100055871A1
公开(公告)日：2010-03-04
申请号：US12615961
申请日：2009-11-10
申请人： Hussein I. Hanafi , Leonard Forbes , Alan R. Reinberg
发明人： Hussein I. Hanafi , Leonard Forbes , Alan R. Reinberg
IPC分类号： H01L21/28 , H01L21/30
CPC分类号： G11C16/0408 , H01L21/28273 , H01L27/11803 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： Methods, devices, and systems for a memory in logic cell are provided. One or more embodiments include using a cell structure having a first gate, a second gate, and a third gate, e.g., a control gate, a back gate, and a floating gate, as a memory in logic cell. The method includes programming the floating gate to a first state to cause the memory in logic cell to operate as a first logic gate type. The method further includes programming the floating gate to a second state to cause the memory in logic cell to operate as a second logic gate type.
摘要翻译：提供了逻辑单元中存储器的方法，设备和系统。一个或多个实施例包括使用具有第一栅极，第二栅极和第三栅极（例如，控制栅极，背栅极和浮置栅极）的单元结构作为逻辑单元中的存储器。该方法包括将浮动栅极编程为第一状态以使逻辑单元中的存储器作为第一逻辑门类型工作。该方法还包括将浮动栅极编程到第二状态以使逻辑单元中的存储器作为第二逻辑门类型工作。

10. 发明申请

US20080316828A1 Memory in logic cell 有权
标题翻译：内存在逻辑单元格中
公开(公告)号：US20080316828A1
公开(公告)日：2008-12-25
申请号：US11821462
申请日：2007-06-21
申请人： Hussein I. Hanafi , Leonard Forbes , Alan R. Reinberg
发明人： Hussein I. Hanafi , Leonard Forbes , Alan R. Reinberg
IPC分类号： G11C11/34 , H01L21/336
CPC分类号： G11C16/0408 , H01L21/28273 , H01L27/11803 , H01L29/42324 , H01L29/66825 , H01L29/7881
摘要： Methods, devices, and systems for a memory in logic cell are provided. One or more embodiments include using a cell structure having a first gate, a second gate, and a third gate, e.g., a control gate, a back gate, and a floating gate, as a memory in logic cell. The method includes programming the floating gate to a first state to cause the memory in logic cell to operate as a first logic gate type. The method further includes programming the floating gate to a second state to cause the memory in logic cell to operate as a second logic gate type.
摘要翻译：提供了逻辑单元中存储器的方法，设备和系统。一个或多个实施例包括使用具有第一栅极，第二栅极和第三栅极（例如，控制栅极，背栅极和浮置栅极）的单元结构作为逻辑单元中的存储器。该方法包括将浮动栅极编程为第一状态以使逻辑单元中的存储器作为第一逻辑门类型工作。该方法还包括将浮动栅极编程到第二状态以使逻辑单元中的存储器作为第二逻辑门类型工作。

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