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1. 发明授权

US5977620A Lead frame having a Ni-Mn alloy layer and a Pd layer 失效
标题翻译：具有Ni-Mn合金层和Pd层的引线框架
公开(公告)号：US5977620A
公开(公告)日：1999-11-02
申请号：US81436
申请日：1998-05-19
申请人： Joong-do Kim , Young-ho Baek , Kyoung-soon Bok
发明人： Joong-do Kim , Young-ho Baek , Kyoung-soon Bok
IPC分类号： C25D3/56 , C23C28/02 , C25D5/34 , C25D7/12 , H01L21/50 , H01L23/495 , H01L23/50 , H01L23/48 , H01L23/52 , H01L23/34 , H01L29/52
CPC分类号： C23C28/021 , C23C28/023 , H01L23/49582 , H01L2224/48247 , H01L2224/85464 , H01L24/48 , H01L2924/00014 , H01L2924/01025 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/12044
摘要： A method for manufacturing a lead frame includes degreasing and activating the surface of a metal sheet, providing the plating solution containing nickel(II) sulfamate tetrahydrate, (Ni(H.sub.2 NSO.sub.3).sub.2.4H.sub.2 O), manganese(II) sulfamate tetrahydrate (Mn(H.sub.2 NSO.sub.3).sub.2.4H.sub.2), nickel (II) chloride hexahydrate (NiCl.sub.2.6H.sub.2 O) and boric acid, plating the metal sheet in the plating solution to form a Ni--Mn alloy layer, and forming a Pd or Pd alloy layer on the Ni--Mn alloy layer.
摘要翻译：制造引线框架的方法包括：对金属片的表面进行脱脂和活化，提供含有硝酸氨基磺酸盐（II），（Ni（H 2 NSO 3）2·4H 2 O），氨基磺酸锰（II）四水合物（Mn（H 2 NSO 3） 2.4H2），氯化镍（II）六水合物（NiCl 2·6H 2 O）和硼酸，在电镀液中镀覆金属片以形成Ni-Mn合金层，并在Ni-Mn合金上形成Pd或Pd合金层层。

2. 发明授权

US5691571A Semiconductor device having fine contact hole with high aspect ratio 失效
标题翻译：具有高纵横比的细小接触孔的半导体装置
公开(公告)号：US5691571A
公开(公告)日：1997-11-25
申请号：US578318
申请日：1995-12-26
申请人： Kazuyuki Hirose , Kuniko Kikuta
发明人： Kazuyuki Hirose , Kuniko Kikuta
IPC分类号： H01L23/485 , H01L23/532 , H01L29/45 , H01L23/48 , H01L29/46 , H01L29/52 , H01L29/64
CPC分类号： H01L23/485 , H01L23/53223 , H01L29/456 , H01L2924/0002
摘要： A semiconductor device includes at least one hole formed on a semiconductor substrate. A barrier metal is formed on at least one portion in contact with the semiconductor substrate in the hole. A metal interconnection is constituted by two layers including a first Al-containing metal film formed on the barrier metal, and a second Al-containing metal film formed on the first Al-containing metal film and having a melting point lower than the melting point of the first Al-containing metal film.
摘要翻译：半导体器件包括形成在半导体衬底上的至少一个孔。在与孔中的半导体衬底接触的至少一个部分上形成阻挡金属。金属互连由两层构成，包括形成在阻挡金属上的第一含Al金属膜和形成在第一含Al金属膜上的第二含Al金属膜，其熔点低于第一含Al金属膜。

3. 发明授权

US5497013A Semi-conductor chip having interdigitated gate runners with gate bonding pads 失效
标题翻译：半导体芯片具有带栅极焊盘的交错栅极流道
公开(公告)号：US5497013A
公开(公告)日：1996-03-05
申请号：US276464
申请日：1994-07-18
申请人： Victor A. K. Temple
发明人： Victor A. K. Temple
IPC分类号： H01L23/051 , H01L23/482 , H01L29/423 , H01L29/78 , H01L23/48 , H01L29/44 , H01L29/52 , H01L29/60
CPC分类号： H01L29/7802 , H01L23/051 , H01L23/4824 , H01L24/06 , H01L29/4238 , H01L2924/01079 , H01L2924/12042 , H01L2924/1301 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/3011
摘要： A semiconductor chip having a cellular topography and a method of packaging a cellular semiconductor chip, includes plural interdigitated metal gate runners that overlie and contact selected gate electrodes on the chip surface, each of the gate runners having an integral widened area to enable a package-carried gate electrode contact foil to be bonded thereto. The gate runner widened areas are relatively small and have little impact on chip active area. The plural gate runners have portions that underlie a package-carried power electrode contact foil and that are separated therefrom by a nonbondable, insulating layer. The gate runners may be deposited on the chip in the same step and from the name material am the power electrode. The portion of the power electrode on the chip surface that underlies the package-carried gate electrode contact foil is separated therefrom and available for use as active area of the chip, Package lid-to-chip alignment tolerances may be relaxed as they are not dictated by alignment of the lid-carried gate contact foil with the gate electrode on the chip.
摘要翻译：具有细胞形貌的半导体芯片和封装蜂窝半导体芯片的方法包括多个叉指的金属栅极流道，其覆盖并接触芯片表面上的选定的栅电极，每个栅极流道具有整体加宽的区域，携带的栅电极接触箔与其键合。闸口加宽区域相对较小，对芯片活动区域影响不大。多个栅极流道具有位于封装携带的电极接触箔的下方的部分，并且通过非粘结的绝缘层与其分离。栅极流道可以以相同的步骤和来自电源电极的名称材料沉积在芯片上。芯片表面上位于封装载体栅极电极接触箔下方的功率电极部分与芯片分离，可用作芯片的有源区域，封装盖到芯片对准公差可能会因为未被规定而放宽通过将盖带电的栅极接触箔与芯片上的栅电极对准。

4. 发明授权

US5471097A Resin encapsulated semiconductor device with an electrically insulating support and distortion preventing member 失效
标题翻译：具有电绝缘支撑和变形防止构件的树脂封装半导体器件
公开(公告)号：US5471097A
公开(公告)日：1995-11-28
申请号：US303597
申请日：1994-09-09
申请人： Kazutaka Shibata
发明人： Kazutaka Shibata
IPC分类号： H01L21/66 , H01L23/495 , H01L23/50 , H05K3/34 , H01L23/48 , H01L29/44 , H01L29/52 , H01L29/60
CPC分类号： H01L23/49558 , H05K3/3426 , H01L2924/0002 , H05K2201/10424 , H05K2201/10689 , Y02P70/613
摘要： A semiconductor device encapsulated with a synthetic resin portion, includes a semiconductor chip, a plurality of leads each electrically connected at one end thereof to the semiconductor chip and bent to have a gull-wing like shape extending outwardly from the synthetic resin portion, and an insulating support member provided in a flat portion nearer to the resin portion than a bottom soldering face of the leads of the gull-wing like shape. The leads are fixed to each other by means of the insulating support member. The semiconductor device has an improved lead alignment even if the leads are each very thin and aligned with fine pitch. Such a semiconductor device can be assuredly mounted on a printed board or the like with ease together with mounting the semiconductor device on the printed board type components, thereby contributing to acquisition of a highly reliable electronic device.
摘要翻译：封装有合成树脂部分的半导体器件包括半导体芯片，多个引线，其一端电连接到半导体芯片并弯曲成具有从合成树脂部分向外延伸的鸥翼状，绝缘支撑构件设置在比鸥翼形状的引线的底部焊接面更靠近树脂部分的平坦部分中。引线通过绝缘支撑构件相互固定。即使引线非常薄并且精细的间距对准，半导体器件也具有改进的引线对准。这样的半导体器件可以容易地安装在印刷电路板等上，同时将半导体器件安装在印刷电路板型部件上，从而有助于获取高可靠性的电子器件。

5. 发明授权

US5466966A Lead frame with leads projecting alternately from opposite sides of a lead frame block 失效
标题翻译：引线框架，其引线从引线框架块的相对侧交替突出
公开(公告)号：US5466966A
公开(公告)日：1995-11-14
申请号：US422647
申请日：1995-04-14
申请人： Seigo Ito
发明人： Seigo Ito
IPC分类号： C23F1/00 , H01L21/48 , H01L23/495 , H01L23/50 , H01L23/48 , H01L29/44 , H01L29/52 , H01L29/60
CPC分类号： H01L21/4828 , H01L23/49548 , H01L2224/05554 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01079 , H01L2924/14
摘要： The first step is forming belt-like resist films having a predetermined width on one and the other surfaces of a metal plate material alternately at a predetermined interval. The second step is etching the metal plate material from the one and other surfaces thereof to dissolve and remove portions of the metal plate material where the resist films are not formed, thereby forming a plurality of leads having a width corresponding to the resist films.
摘要翻译：第一步是以预定间隔交替地在金属板材料的一个和另一个表面上形成具有预定宽度的带状抗蚀剂膜。第二步是从其一个表面蚀刻金属板材料，以溶解和去除未形成抗蚀剂膜的金属板材料的部分，从而形成具有对应于抗蚀剂膜的宽度的多个引线。

6. 发明授权

US5455454A Semiconductor lead frame having a down set support member formed by inwardly extending leads within a central aperture 失效
标题翻译：半导体引线框架具有通过向内延伸中心孔内的引线而形成的下降支撑构件
公开(公告)号：US5455454A
公开(公告)日：1995-10-03
申请号：US125036
申请日：1993-09-21
申请人： Seh H. Oh , Do S. Jeung
发明人： Seh H. Oh , Do S. Jeung
IPC分类号： H01L23/495 , H01L23/48 , H01L29/44 , H01L29/52 , H01L29/62
CPC分类号： H01L23/49503 , H01L23/49506 , H01L23/49558 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/85439 , H01L24/48 , H01L24/49 , H01L2924/00014
摘要： A semiconductor lead frame is disclosed. An adhesive tape is attached on one end part of inner leads and a bus bar, and a semiconductor chip is mounted on the adhesive tape without using a conventional die pad, wherein the inner leads is formed with a gap to be separated from neighboring leads by etching and the adhesive tape is supported by the bus bar so that the reliability of a semiconductor package is enhanced, and a labor for the development and production of the semiconductor package is saved because semiconductor chips of a variable size can be mounted on the same kind of the semiconductor package by changing only the adhesive tape without preparing another lead frame.
摘要翻译：公开了一种半导体引线框架。在内引线和汇流条的一端附着粘合带，并且不使用传统的芯片焊盘将半导体芯片安装在粘合带上，其中内引线形成有与相邻引线分离的间隙，以便通过蚀刻和胶带由母线支撑，使得半导体封装的可靠性增强，并且由于可变尺寸的半导体芯片可以安装在同一种类上，因此可以节省半导体封装的开发和生产的劳动通过仅改变粘合带而不准备另一个引线框架来实现半导体封装。

7. 发明授权

US5408127A Method of and arrangement for preventing bonding wire shorts with certain integrated circuit components 失效
标题翻译：用某些集成电路部件防止接合线短路的方法和装置
公开(公告)号：US5408127A
公开(公告)日：1995-04-18
申请号：US215493
申请日：1994-03-21
申请人： Shahram Mostafazadeh
发明人： Shahram Mostafazadeh
IPC分类号： H01L23/495 , H01L23/48 , H01L29/44 , H01L29/52 , H01L29/60
CPC分类号： H01L23/49575 , H01L24/48 , H01L2224/48091 , H01L2224/48095 , H01L2224/48247 , H01L2224/48465 , H01L2224/48471 , H01L2224/4899 , H01L2224/49171 , H01L2224/85207 , H01L24/49 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2924/181
摘要： An integrated circuit package is disclosed herein including one or more dies, each of which has an array of input/output bond pads, a leadframe which includes an array of electrically conductive leads, and an array of bonding wires, each of which extends along its length between and is connected at its opposite ends to a respective die bond pad and a corresponding lead on the leadframe or a corresponding die bond pad on another die. There is also disclosed a technique for using a bridge arrangement to prevent the bonding wires from contacting the die or dies along the length of each of the wires. In fabricating the package just described, the bridge arrangement is provided as part of either the leadframe or part of a heater block which is a component of the equipment that may be used in manufacturing the integrated circuit package.
摘要翻译：本文公开了一种集成电路封装，其包括一个或多个管芯，每个管芯具有输入/输出接合焊盘的阵列，包括导电引线阵列的引线框架和接合线阵列，每个引线框架沿其长度在其相对端处连接到相应的管芯接合焊盘和引线框架上的对应引线或另一管芯上的相应管芯接合焊盘。还公开了一种使用桥接装置来防止接合线沿着每根导线的长度接触模具或模具的技术。在制造刚刚描述的封装中，桥接装置被提供为引线框架的一部分或作为可用于制造集成电路封装的设备的部件的加热器块的一部分。

8. 发明授权

US5408126A Manufacture of semiconductor devices and novel lead frame assembly 失效
标题翻译：半导体器件和新型引线框组件的制造
公开(公告)号：US5408126A
公开(公告)日：1995-04-18
申请号：US168706
申请日：1993-12-17
申请人： Yang C. Chen
发明人： Yang C. Chen
IPC分类号： H01L23/50 , H01L23/498 , H01L25/065 , H01L23/48 , H01L29/44 , H01L29/52 , H01L29/60
CPC分类号： H01L25/0657 , H01L23/49861 , H01L2224/48091 , H01L2224/48465 , H01L2225/0651 , H01L24/48 , H01L2924/00014 , H01L2924/01078 , H01L2924/3025
摘要： A lead frame assembly comprises a lead frame having cantilevered leads. Combined with the lead frame is a rigid, elongated base member having a U-shaped cross-section and laterally outwardly extending flanges at the upper ends of side walls of the base member. The leads of the lead frame overlie the base member flanges and are bonded to conductive paths on the flanges which extend along the flanges, along the base member side walls and onto the bottom wall of the base member. In use, a semiconductor chip is mounted on the bottom wall and wire bonded to respective ones of the conductive paths. Two base members can be used in flange-to-flange contacting relationship to provide a tubular enclosure for the chip.
摘要翻译：引线框架组件包括具有悬臂引线的引线框架。与引线框结合是刚性的细长基部构件，其在基部构件的侧壁的上端处具有U形横截面和横向向外延伸的凸缘。引线框架的引线覆盖在基部构件凸缘上，并且沿着凸缘沿着基部构件侧壁并延伸到基底构件的底壁上的导向路径接合。在使用中，半导体芯片安装在底壁上，并且引线键合到相应的导电路径上。两个基座构件可用于法兰到法兰的接触关系，以提供用于芯片的管状外壳。

9. 发明授权

US5381036A Lead-on chip semiconductor device having peripheral bond pads 失效
标题翻译：具有外围接合焊盘的引线式芯片半导体器件
公开(公告)号：US5381036A
公开(公告)日：1995-01-10
申请号：US107412
申请日：1993-08-16
申请人： Charles G. Bigler , James J. Casto , Michael B. McShane , David D. Afshar
发明人： Charles G. Bigler , James J. Casto , Michael B. McShane , David D. Afshar
IPC分类号： H01L21/52 , H01L21/60 , H01L23/495 , H01L23/50 , H01L23/544 , H01L23/48 , H01L29/44 , H01L29/52 , H01L29/60
CPC分类号： H01L23/544 , H01L23/4951 , H01L23/50 , H01L2223/54473 , H01L2224/05554 , H01L2224/48245 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/07802 , H01L2924/14 , Y10S228/904 , Y10T29/49121
摘要： A semiconductor device (10) has a lead-on-chip (LOC) configuration. Leads (24) of the device have central portions (36) which are electrically coupled to peripheral bond pads (14) by conductive wires (30). Inner portions (38) of the leads extend from the central portions toward centerline A--A for improved adhesion and to provide an internal clamping area (41) which stabilizes the leads during wire bonding. In one embodiment, tie bar (22) of leadframe (16) is used to distribute power across semiconductor chip (12). The leadframe may also include chip alignment features (50) and tape alignment features (52) to align chip (12) and insulating tape (18) to the leadframe, respectively.
摘要翻译：半导体器件（10）具有片上引线（LOC）配置。器件的引线（24）具有通过导线（30）电耦合到外围接合焊盘（14）的中心部分（36）。引线的内部部分（38）从中心部分向中心线A-A延伸，以提高粘附力，并提供在引线接合期间稳定引线的内部夹紧区域（41）。在一个实施例中，引线框架（16）的连接杆（22）用于跨半导体芯片（12）分配功率。引线框架还可以包括分别将芯片（12）和绝缘带（18）对准引线框的芯片对准特征（50）和带对准特征（52）。

10. 发明授权

US5378925A Routing method and arrangement for power lines and signal lines in a microelectronic device 失效
标题翻译：微电子器件中电源线和信号线的布线方法和布置
公开(公告)号：US5378925A
公开(公告)日：1995-01-03
申请号：US842352
申请日：1992-05-18
申请人： Minoru Sasaki
发明人： Minoru Sasaki
IPC分类号： H01L21/768 , H01L27/02 , H01L27/04 , H01L27/108 , H01L23/48 , H01L29/44 , H01L29/52 , H01L29/60
CPC分类号： H01L27/0214
摘要： In a semiconductor integrated circuit device such as a memory chip, the number of wirings is increasing as the memory capacity and the like increase. In improving the reliability and obtaining high access speed of a common bus in which these wirings are arranged, wirings in a second layer and via holes at jumpers used for interference portions of signal wirings and power supply wirings in a congested region of a common bus have become an issue. Accordingly, in the present invention, it is made possible to form wirings in the second layer having wide width and a plurality of via holes per one connecting point, thus realizing a semiconductor integrated circuit which has high reliability and high access speed by arranging a mother power supply wiring branched to the common bus line along the vicinity of processing circuits of signal wirings arranged in the common bus.
摘要翻译： PCT No.PCT / JP91 / 00970 Sec。 371 Date 1992 Sec。 102（e）日期1992年5月18日PCT提交1991年7月19日PCT公布。第WO92 / 02043号公报日期：1992年2月6日。在诸如存储器芯片的半导体集成电路器件中，随着存储器容量等增加，布线数量增加。在提高可靠性和获得布置这些布线的公共总线的高访问速度的情况下，在公共总线的拥挤区域中用于信号布线和电源布线的干扰部分的跳线中的布线中的布线和通孔中的布线具有成为一个问题。因此，在本发明中，可以在每个连接点的宽度宽的多个通孔的第二层中形成布线，并且通过布置母体来实现具有高可靠性和高访问速度的半导体集成电路电源布线沿着布置在公共总线中的信号布线的处理电路的附近分支到公共总线。

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