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1. 发明授权

US06513146B1 Method of designing semiconductor integrated circuit device, method of analyzing power consumption of circuit and apparatus for analyzing power consumption 有权
标题翻译：设计半导体集成电路器件的方法，分析电路功耗的方法和功耗分析仪器
公开(公告)号：US06513146B1
公开(公告)日：2003-01-28
申请号：US09711885
申请日：2000-11-15
申请人： Tomonori Yonezawa , Takayuki Sasaki , Takahiro Kondo , Hiroki Otsuki , Tsuyoshi Nakamura
发明人： Tomonori Yonezawa , Takayuki Sasaki , Takahiro Kondo , Hiroki Otsuki , Tsuyoshi Nakamura
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F17/5022 , G06F2217/78
摘要： The processing quantity of each description part is estimated through a source code analysis of a system operation description language or through simulation, or power consumption of each function is estimated through an operation description analysis of functions. Predetermined threshold values are set with respect to the processing quantity and the power consumption of each description part or function, so as to determine S/W and H/W implementation, and then, S/W and H/W partitioning is carried out. Thereafter, it is determined whether or not the total processing quantity or the total power consumption satisfies a desired design condition. Also, the S/W and H/W partitioning can be adjusted again in comprehensive consideration of the power consumption and the processing quantity, and the accuracy in the S/W and H/W partitioning can be improved by providing an instruction set simulator with a function to analyze power consumption. Moreover, an interface between S/W and H/W can be generated in the S/W and H/W partitioning so as to be automatically inserted into a S/W implemented part or a H/W implemented part.
摘要翻译：每个描述部分的处理量通过系统操作描述语言的源代码分析或通过仿真来估计，或者通过功能的操作描述分析来估计每个功能的功耗。相对于每个描述部分或功能的处理量和功耗来设置预定阈值，以便确定S / W和H / W实现，然后执行S / W和H / W分区。此后，确定总处理量或总功耗是否满足期望的设计条件。此外，可以综合考虑功耗和处理量来再次调整S / W和H / W分区，并且可以通过提供一个指令集模拟器来提高S / W和H / W分区的精度分析功耗的功能。此外，可以在S / W和H / W分区中产生S / W和H / W之间的接口，以便自动插入到S / W实现部分或H / W实现部分。

2. 发明授权

US07577557B2 Simulator and simulation method for behaviors of processors 失效
标题翻译：处理器行为的模拟器和仿真方法
公开(公告)号：US07577557B2
公开(公告)日：2009-08-18
申请号：US10969027
申请日：2004-10-21
申请人： Takahiro Kondo , Tsuyoshi Nakamura , Maiko Taruki , Tomonori Yonezawa
发明人： Takahiro Kondo , Tsuyoshi Nakamura , Maiko Taruki , Tomonori Yonezawa
IPC分类号： G06F17/50 , G06F9/44
CPC分类号： G06F17/5022
摘要： A simulator operable to simulate behaviors of a processor using software is provided. The simulator includes a command input unit, a memory element, a register element, a control element, a resource information storage unit, and a resource access-analyzing unit. The command input unit is operable to analyze/process entered commands. The memory element is operable to store executive instructions issued by the processor and data treated by the processor. The register element is operable to contain data for use in calculation. The control element is operable to access the memory element and register element in accordance with the executive instructions. The resource information storage unit is operable to contain specified resource information and a piece of read/write information for each piece of the resource information. The resource access-analyzing unit is operable to compare access destinations (the memory element and register element to be accessed by the control element) and a read/write classification with the resource information and read/write information contained in the resource information storage unit, thereby practicing a resource access analysis as to whether or not the access destinations are allowed by the resource information and read/write information.
摘要翻译：提供了一种可以使用软件模拟处理器行为的模拟器。模拟器包括命令输入单元，存储元件，寄存器元件，控制元件，资源信息存储单元和资源访问分析单元。命令输入单元用于分析/处理输入的命令。存储元件可操作以存储处理器发出的执行指令和由处理器处理的数据。寄存器元件可操作地包含用于计算的数据。控制元件可操作以根据执行指令访问存储器元件和寄存器元件。资源信息存储单元可操作以对于每个资源信息包含指定的资源信息和一条读/写信息。资源访问分析单元可操作以将资源信息存储单元中包含的资源信息和读取/写入信息的访问目的地（由控制元素访问的存储元件和注册元素）与读/写分类进行比较，从而对资源信息和读/写信息是否允许访问目的地进行资源访问分析。

3. 发明申请

US20050091028A1 Simulator and simulation method 失效
标题翻译：模拟器和仿真方法
公开(公告)号：US20050091028A1
公开(公告)日：2005-04-28
申请号：US10969027
申请日：2004-10-21
申请人： Takahiro Kondo , Tsuyoshi Nakamura , Maiko Taruki , Tomonori Yonezawa
发明人： Takahiro Kondo , Tsuyoshi Nakamura , Maiko Taruki , Tomonori Yonezawa
IPC分类号： G06F11/28 , G06F9/455 , G06F11/30 , G06F17/50 , G06F9/45
CPC分类号： G06F17/5022
摘要： A simulator operable to simulate behaviors of a processor using software is provided. The simulator includes a command input unit, a memory element, a register element, a control element, a resource information storage unit, and a resource access-analyzing unit. The command input unit is operable to analyze/process entered commands. The memory element is operable to store executive instructions issued by the processor and data treated by the processor. The register element is operable to contain data for use in calculation. The control element is operable to access the memory element and register element in accordance with the executive instructions. The resource information storage unit is operable to contain specified resource information and a piece of read/write information for each piece of the resource information. The resource access-analyzing unit is operable to compare access destinations (the memory element and register element to be accessed by the control element) and a read/write classification with the resource information and read/write information contained in the resource information storage unit, thereby practicing a resource access analysis as to whether or not the access destinations are allowed by the resource information and read/write information.
摘要翻译：提供了一种可以使用软件模拟处理器行为的模拟器。模拟器包括命令输入单元，存储元件，寄存器元件，控制元件，资源信息存储单元和资源访问分析单元。命令输入单元用于分析/处理输入的命令。存储元件可操作以存储处理器发出的执行指令和由处理器处理的数据。寄存器元件可操作地包含用于计算的数据。控制元件可操作以根据执行指令访问存储器元件和寄存器元件。资源信息存储单元可操作以对于每个资源信息包含指定的资源信息和一条读/写信息。资源访问分析单元可操作以将资源信息存储单元中包含的资源信息和读取/写入信息的访问目的地（由控制元素访问的存储元件和注册元素）与读/写分类进行比较，从而对资源信息和读/写信息是否允许访问目的地进行资源访问分析。

4. 发明授权

US07062633B1 Conditional vector arithmetic method and conditional vector arithmetic unit 失效
标题翻译：条件向量算法和条件向量运算单元
公开(公告)号：US07062633B1
公开(公告)日：2006-06-13
申请号：US09868048
申请日：1999-12-15
申请人： Mana Hamada , Shunichi Kuromaru , Tomonori Yonezawa , Tsuyoshi Nakamura
发明人： Mana Hamada , Shunichi Kuromaru , Tomonori Yonezawa , Tsuyoshi Nakamura
IPC分类号： G06F9/302 , G06F9/38
CPC分类号： G06F17/16
摘要： It is decided whether a first source data from the memory 101 is a data which is to be subjected to arithmetic or not by a state flag detection means 150, the result of the decision is retained as a state flag, and it is decided by a condition decision means 109 whether or not the state flag satisfies a condition for performing the arithmetic. A control means 110 controls whether an ALU 100 should perform the arithmetic or not on the basis of the condition satisfaction/dissatisfaction information.
摘要翻译：决定来自存储器101的第一源数据是否是由状态标志检测装置150进行算术的数据，判定结果被保留为状态标志，并且由条件判定单元109，判断状态标志是否满足进行运算的条件。控制装置110基于条件满足/不满意信息来控制ALU 100是否应该执行算术。

5. 发明授权

US06671708B1 Processor and image processing device 有权
标题翻译：处理器和图像处理设备
公开(公告)号：US06671708B1
公开(公告)日：2003-12-30
申请号：US09600247
申请日：2000-08-31
申请人： Shunichi Kuromaru , Mana Hamada , Tomonori Yonezawa , Masatoshi Matsuo , Tsuyoshi Nakamura , Masahiro Oohashi
发明人： Shunichi Kuromaru , Mana Hamada , Tomonori Yonezawa , Masatoshi Matsuo , Tsuyoshi Nakamura , Masahiro Oohashi
IPC分类号： G06F738
CPC分类号： G06F9/3885 , G06F9/30036 , G06F17/10 , G06T1/20
摘要： An image processing apparatus according to the present invention comprises a general arithmetic circuit 101 comprising a program control circuit 103, a first address generator 104, a first data memory 105, a first pipeline operation circuit 106, a second address generator 113, a second data memory 114 and a second pipeline operation circuit 112, and a dedicated arithmetic circuit 102 comprising a control circuit 115, a first dedicated pipeline operation circuit 107, a second dedicated pipeline operation circuit 108, . . . , an N-th dedicated pipeline operation circuit 110, as shown in FIG. 1. The arithmetic unit having the above-described structure, for example, can realize an arithmetic unit which can be applied to various applications. Further, considering the age of IP (Intellectual Property) which will come in the future, the arithmetic unit can exhibit the flexibility toward the applications.
摘要翻译：根据本发明的图像处理装置包括通用运算电路101，其包括程序控制电路103，第一地址生成器104，第一数据存储器105，第一流水线运算电路106，第二地址发生器113，第二数据存储器114和第二流水线操作电路112，以及专用运算电路102，包括控制电路115，第一专用流水线运行电路107，第二专用流水线运行电路108。。。，第N专用流水线运算电路110，如图1所示。例如，具有上述结构的运算单元可以实现可应用于各种应用的算术单元。此外，考虑到将来会出现的知识产权（知识产权）的年龄，算术单位可以展现出应用的灵活性。

6. 发明授权

US06332152B1 Arithmetic unit and data processing unit 失效
标题翻译：算术单元和数据处理单元
公开(公告)号：US06332152B1
公开(公告)日：2001-12-18
申请号：US09201720
申请日：1998-11-30
申请人： Masahiro Ohashi , Mana Hamada , Tomonori Yonezawa , Shunichi Kurohmaru , Yasuo Kouhashi , Masatoshi Matsuo , Masayoshi Toujima
发明人： Masahiro Ohashi , Mana Hamada , Tomonori Yonezawa , Shunichi Kurohmaru , Yasuo Kouhashi , Masatoshi Matsuo , Masayoshi Toujima
IPC分类号： G06F738
CPC分类号： H03M7/4006 , G06F7/02 , G06F2207/025 , H03M7/46
摘要： For every data, the number of data matches that occurred consecutively is written to a memory together with nonmatching data, and data from the memory is read out to continuously perform subsequent data processing and detect, at the same time, the last data written to the memory. To achieve this, a desired value is set in a data register, and a comparison instruction is issued by which the value set in the register is compared with a value set in a second register, and the number of matches that occurred consecutively is output together with nonmatching data; upon the output of a retrieval counter reaching a predetermined value, the comparison instruction is terminated, whereupon the number of consecutive matches, the nonmatching data, and an end flag signal are written to the memory at the same address.
摘要翻译：对于每个数据，连续发生的数据匹配数量与非匹配数据一起写入存储器，并且读出来自存储器的数据以连续执行后续数据处理，同时检测写入到记忆。为了实现这一点，在数据寄存器中设置期望值，并且发出比较指令，通过该比较指令将寄存器中设置的值与在第二寄存器中设置的值进行比较，并且连续发生的匹配次数一起输出具有不匹配的数据; 在检索计数器的输出达到预定值的情况下，比较指令被终止，因此连续匹配的数量，非匹配数据和结束标志信号被写入同一地址的存储器。

7. 发明申请

US20050066093A1 Real-time processor system and control method 审中-公开
标题翻译：实时处理器系统和控制方法
公开(公告)号：US20050066093A1
公开(公告)日：2005-03-24
申请号：US10942893
申请日：2004-09-17
申请人： Ryuji Fuchikami , Tomonori Yonezawa , Yoichi Nishida
发明人： Ryuji Fuchikami , Tomonori Yonezawa , Yoichi Nishida
IPC分类号： G06F13/362 , G06F9/46 , G06F13/00 , G06F13/14 , G06F13/24 , G06F13/26 , G06F15/16
CPC分类号： G06F13/26 , G06F13/362
摘要： A real time processor system comprises: a bus arbiter; a plurality of calculating units, each having a processor and an interruption processing unit; a DMA controller; a plurality of priority registers; a memory; and an SCI. The bus arbiter comprises: a priority comparing unit; and a bus assignment unit. Each of the plurality of priority registers stores an I/O access priority value corresponding to each of the calculating units. Priority values are compared, and then right of I/O use is determined. The values of the plurality of priority registers are changed, thereby adaptively performing multiple interruption processing.
摘要翻译：实时处理器系统包括：总线仲裁器; 多个计算单元，每个具有处理器和中断处理单元; 一个DMA控制器多个优先级寄存器; 记忆和SCI。总线仲裁器包括：优先级比较单元; 和总线分配单元。多个优先级寄存器中的每一个存储对应于每个计算单元的I / O访问优先级值。比较优先级值，然后确定I / O使用权。改变多个优先级寄存器的值，从而自适应地执行多个中断处理。

8. 发明授权

US06775716B2 High-performance DMA controller 失效
标题翻译：高性能DMA控制器
公开(公告)号：US06775716B2
公开(公告)日：2004-08-10
申请号：US09859802
申请日：2001-05-18
申请人： Masayoshi Tojima , Yasuo Kohashi , Tomonori Yonezawa
发明人： Masayoshi Tojima , Yasuo Kohashi , Tomonori Yonezawa
IPC分类号： G06F1328
CPC分类号： G06F13/30 , Y02D10/14
摘要： A high-performance DMA controller for controlling data transfer between a main storage means holding various kinds of data and a plurality of local storage means, comprises: an interface for generating a control signal for the main storage means; a data I/O unit for controlling I/O of data; a parameter holding unit for holding various kinds of parameters that are required for execution of data transfer; a data transfer request receiver for receiving requests of data transfer; and a start command receiver for receiving a start/stop command of the data transfer controller. The data transfer request receiver receives, from a data transfer request source, reservations of plural data transfer requests comprising execution priority information and local storage means type information, each information being arbitrarily set by the data transfer request source, and holds the local storage means type information in association with each execution priority information. The data transfer controller receives only the reservations of data transfer requests until a start command is issued from a system controller and, when a start command is issued, the data transfer controller sequentially decodes the local storage means type information of the reserved data transfer requests having relatively high execution priorities, in chronological order of the data transfer requests, and then sequentially takes parameters required for data transfer from the parameter holding unit, according to the decoding result, to execute data transfer.
摘要翻译：一种用于控制保持各种数据的主存储装置与多个本地存储装置之间的数据传输的高性能DMA控制器，包括：用于产生主存储装置的控制信号的接口; 用于控制数据的I / O的数据I / O单元; 用于保持执行数据传送所需的各种参数的参数保持单元; 用于接收数据传送请求的数据传送请求接收器; 以及用于接收数据传送控制器的启动/停止命令的启动命令接收器。数据传输请求接收器从数据传输请求源接收包括执行优先级信息和本地存储装置类型信息的多个数据传输请求的预留，每个信息由数据传送请求源任意设置，并且保存本地存储装置类型与每个执行优先级信息相关联的信息。数据传输控制器仅接收数据传输请求的预留，直到从系统控制器发出启动命令，并且当发出启动命令时，数据传送控制器对本地存储装置的类型信息进行顺序解码，相对高的执行优先级，按照数据传输请求的时间顺序，然后根据解码结果顺序地从参数保存单元接收数据传输所需的参数，以执行数据传送。

9. 发明授权

US06564237B2 Arithmetic unit and data processing unit 失效
公开(公告)号：US06564237B2
公开(公告)日：2003-05-13
申请号：US09978204
申请日：2001-10-17
申请人： Masahiro Ohashi , Mana Hamada , Tomonori Yonezawa , Shunichi Kurohmaru , Yasuo Kouhashi , Masatoshi Matsuo , Masayoshi Toujima
发明人： Masahiro Ohashi , Mana Hamada , Tomonori Yonezawa , Shunichi Kurohmaru , Yasuo Kouhashi , Masatoshi Matsuo , Masayoshi Toujima
IPC分类号： G06F738
CPC分类号： H03M7/4006 , G06F7/02 , G06F2207/025 , H03M7/46
摘要： For every data, the number of data matches that occurred consecutively is written to a memory together with nonmatching data, and data from the memory is read out to continuously perform subsequent data processing and detect, at the same time, the last data written to the memory. To achieve this, a desired value is set in a data register, and a comparison instruction is issued by which the value set in the register is compared with a value set in a second register, and the number of matches that occurred consecutively is output together with nonmatching data; upon the output of a retrieval counter reaching a predetermined value, the comparison instruction is terminated, whereupon the number of consecutive matches, the nonmatching data, and an end flag signal are written to the memory at the same address.

10. 发明授权

US07006153B2 Image composition method, and image composition apparatus 失效
标题翻译：图像组合方法和图像合成装置
公开(公告)号：US07006153B2
公开(公告)日：2006-02-28
申请号：US10231377
申请日：2002-08-30
申请人： Hiroki Ohtsuki , Tomonori Yonezawa , Satoshi Kajita , Ryuji Fuchikami
发明人： Hiroki Ohtsuki , Tomonori Yonezawa , Satoshi Kajita , Ryuji Fuchikami
IPC分类号： H04N7/01 , G06K9/36
CPC分类号： G06T11/60 , H04N5/44504 , H04N21/431 , H04N21/44012
摘要： An image composition apparatus includes a composition processing unit comprising a composition position determination unit for receiving a shape signal and an image signal which are outputted from an image decoding unit, and determining a composition position of an object as a foreground image; a shape boundary determination unit for determining the shape and boundary of the object; an arbitrary-shaped frame generation unit for generating an outline or frame of the object on the basis of information relating to the shape and boundary of the object; and a pixel composition unit for compositing a target pixel (pixel to be processed) of the object or an arbitrary-shaped frame pixel that is generated by the arbitrary-shaped frame generation unit 4c, with the corresponding pixel in the background image. Therefore, a composite image, in which an outline or an arbitrary-shaped shape is added to an arbitrary-shaped object, can be generated.
摘要翻译：一种图像合成装置，包括：合成处理单元，包括：组合位置确定单元，用于接收从图像解码单元输出的形状信号和图像信号;以及确定作为前景图像的对象的构图位置; 形状边界确定单元，用于确定所述物体的形状和边界; 任意形状的帧生成单元，用于根据与对象的形状和边界相关的信息生成对象的轮廓或框架; 以及像素合成单元，用于将对象的目标像素（待处理像素）或由任意形状的帧生成单元4c生成的任意形状的像素与背景图像中的对应像素进行合成。因此，可以生成其中轮廓或任意形状被添加到任意形状的对象的合成图像。

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